KR101071255B1 - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

An amorphous silicon thin film is crystallized on the insulating substrate to form a polycrystalline silicon film. Subsequently, an insulating film is formed over the polycrystalline silicon film, and then the polycrystalline silicon film and the first insulating film are patterned together to form a semiconductor layer and a first gate insulating film, and a second gate insulating film is laminated on the substrate to complete the gate insulating film. do. Forming a gate electrode over the second gate insulating layer of the semiconductor layer, implanting impurities into the semiconductor layer to form source and drain regions in both of the semiconductor layers around the gate electrode, and covering the gate electrode; Form. Subsequently, source and drain electrodes electrically connected to the source and drain regions are respectively formed, a second interlayer insulating layer covering the source and drain electrodes is formed, and a pixel electrode connected to the drain electrode is formed.

Amorphous, Gate Insulation, Crystal, Thin Film Transistor, Alignment Key

Description

Thin film transistor array panel and manufacturing method thereof {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, according to a process sequence thereof.

3A and 3B are cross-sectional views of a method of manufacturing a thin film transistor array panel according to another exemplary embodiment of the present invention, in the order of their processes;

4A and 4B are layout views sequentially illustrating a method of aligning a multilayer thin film using alignment keys in a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 4C is a cross-sectional view of the thin film transistor array panel of FIG. 4B taken along the line IVc-IVc '.

5A and 5C are layout views illustrating structures of alignment keys used in a method of manufacturing a thin film transistor array panel according to another exemplary embodiment of the present invention.

6A is a layout view illustrating a method of aligning a multilayer thin film using an alignment key in a method of manufacturing a thin film transistor array panel according to another exemplary embodiment of the present invention.                 

FIG. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb ′.

7 is a layout view illustrating a structure of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

8 and 9 are cross-sectional views of the thin film transistor array panel of FIG. 7 taken along lines VIII-VIII 'and IX-IX',

10, 12, 14, 16, 18, 20, and 22 are layout views illustrating intermediate steps in the method of manufacturing the thin film transistor array panel of FIGS. 7 to 9.

11A and 11B are cross-sectional views taken along the lines XIa-XIa 'and XIb-XIb' of FIG. 10.

13A and 13B are cross-sectional views taken along the lines XIIIa-XIIIa 'and XIIIb-XIIIb' in FIG. 12,

15A and 15B are cross-sectional views taken along lines XVa-XVa 'and XVb-XVb' in FIG. 14,

17A and 17B are cross-sectional views taken along the lines XVIIa-XVIIa 'and XVIIb-XVIIb' in FIG. 16,

19A and 19B are cross-sectional views taken along the lines XIXa-XIXa 'and XIXb-XIXb' in FIG. 18,

21A and 21B are cross-sectional views taken along the lines XXIa-XXIa 'and XXIb-XXIb' in FIG. 20,                 

23A and 23B are cross-sectional views taken along the lines XXIIIa-XXIIIa 'and XXIIIb-XXIIIb' of FIG. 22.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method for manufacturing the same.

In general, the thin film transistor array panel is used as a substrate such as a liquid crystal display device or an organic EL display device having pixels having a matrix array. At this time, each pixel is provided with a thin film transistor as a switching element to selectively drive the R, G, B pixels, it is possible to implement a screen of various colors.

A liquid crystal display is an apparatus that displays an image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two display panels by using an electrode, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. . In this case, a thin film transistor is used as the switching element to control the image signal transmitted to the electrode.

Organic electro-luminescence is a display device that displays an image by electrically exciting and emitting a fluorescent organic material, and includes a hole injection electrode (anode), an electron injection electrode (cathode), and an organic light emitting layer formed therebetween. When charge is injected into the organic light emitting layer, electrons and holes are paired and extinguished to emit light. Each pixel includes a driving thin film transistor and a switching transistor. In this case, the amount of current of the driving thin film transistor that supplies the current for light emission is controlled by the data voltage applied through the switching transistor, and the gate and source of the switching transistor and the gate signal line (or scan line) are disposed to cross each other. It is connected to the data signal line.

The most common thin film transistor used in such a display device uses amorphous silicon as a semiconductor layer.

Such amorphous silicon thin film transistors are approximately 0.5 占 ??. It has a mobility of about 1 cm 2 / Vsec, so that it can be used as a switching element of a liquid crystal display device, but the mobility is small and a direct drive circuit in a display device such as a liquid crystal panel or an organic electroluminescence (EL). There is an inadequate disadvantage of forming it.

Therefore, to overcome this problem, the current mobility is approximately 20 ??. A liquid crystal display device or an organic EL (electro luminescence) using a polycrystalline silicon thin film transistor using a polycrystalline silicon of about 150 cm 2 / Vsec as a semiconductor layer as a switching element or a driving element has been developed. Because of the current mobility, it is possible to implement a chip in glass in which a driving circuit is embedded in a panel for a display device.

Currently, the most commonly used method of crystallizing a thin film of polycrystalline silicon on a glass substrate having a low melting point is the technique of annealing by irradiating an excimer laser to amorphous silicon. The excimer laser is irradiated and the amorphous silicon is melted to a temperature of about 1400 ° C. to crystallize into polycrystal.

In addition, a sequential lateral solidification process has been developed that can artificially control the distribution of grain boundaries, which means that the grains of polycrystalline silicon are interspersed at the boundary between the liquid-irradiated and laser-free solid-state regions. It is a technique that takes advantage of the fact that it grows in the vertical direction. This sequential lateral solid crystal has the advantage of growing the grain size by the width of the slit.

In order to improve the characteristics of the polycrystalline silicon thin film transistor using the polycrystalline silicon film crystallized through such a crystallization process as a semiconductor, it is important to stably secure the grain size and the interfacial characteristics of the gate insulating film and the polycrystalline silicon film. At this time, the size of the crystal grains can be adjusted using the crystallization method as described above, and the interfacial properties are controlled through the cleaning process.

However, in the manufacturing method of crystallizing a polycrystalline silicon film, patterning it by a photolithography process, forming a semiconductor, and then stacking a gate insulating film, a photoresist film is applied on top of the polycrystalline silicon film and the photoresist film is baked. The problem of surface contamination occurs. In order to solve this problem, the polysilicon film is patterned and then cleaned, but the contamination is not completely removed, resulting in deterioration or non-uniformity of the thin film transistor, thereby degrading the display device.                         

Meanwhile, in the method of manufacturing a display panel for a display device including a thin film transistor, a multilayer thin film including a conductive film or an insulating film is formed by photolithography, and an alignment key is used to align the layers. The position of the alignment key between layers in the manufacturing process is detected by the step by the alignment key, through which the thin film pattern between the layers are aligned.

However, in the process of crystallizing amorphous silicon, grains grow, but at the point where the grains meet each other, grain growth stops, and protrusions are formed at this portion, which causes mis-alignment between layers. That is, when the projection of the polysilicon film has a severe step in the crystallization process, it acts as a noise in the process of detecting the alignment key in the manufacturing process, thereby preventing the detection of the alignment key, resulting in misalignment between layers.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array panel and a method of manufacturing the same that can uniformly improve the characteristics of the thin film transistor.

In addition, another object of the present invention is to provide a method for manufacturing a thin film transistor array panel which can prevent misalignment by minimizing noise caused by projections.

In order to solve the above problems, in the present invention, the polysilicon film is laminated with the gate insulating film and then patterned together. The measurement part of the alignment keys of the polysilicon film is embossed, and the peripheral part defining the boundary of the measurement part is formed intaglio.                     

More specifically, in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the amorphous silicon thin film is crystallized on the insulating substrate to form a polycrystalline silicon film. Next, an insulating film is formed on the polycrystalline silicon film, and then the polycrystalline silicon film and the first insulating film are patterned together to form a semiconductor layer and a first gate insulating film, and a second gate insulating film is laminated on the substrate to complete the gate insulating film. . Forming a gate electrode over the second gate insulating layer of the semiconductor layer, implanting impurities into the semiconductor layer to form source and drain regions in both of the semiconductor layers around the gate electrode, and covering the gate electrode; Form. Subsequently, source and drain electrodes electrically connected to the source and drain regions are respectively formed, a second interlayer insulating layer covering the source and drain electrodes is formed, and a pixel electrode connected to the drain electrode is formed.

Prior to forming the second gate insulating layer, the method may further include etching the first gate insulating layer, and the thin film transistor array panel may be formed of one substrate of a liquid crystal display or an organic light emitting display.

In a method of manufacturing a thin film transistor array panel according to another exemplary embodiment of the present invention, an amorphous silicon thin film is crystallized on an insulating substrate to form a polycrystalline silicon film, and a polycrystalline silicon film is patterned to form a semiconductor layer. Subsequently, a gate insulating film covering the semiconductor layer is formed, a gate electrode is formed over the gate insulating film of the semiconductor layer, and impurities are injected into the semiconductor layer to form source and drain regions on both sides of the gate electrode. Subsequently, a first interlayer insulating film is formed to cover the gate electrode, a source and drain electrode electrically connected to the source and drain regions are respectively formed, and a second interlayer insulating film is formed to cover the source and drain electrodes. And a pixel electrode connected to each other. In this case, in at least one of the semiconductor layer, the gate electrode, the source and drain electrodes, and the pixel electrode forming step, a first alignment key including an outer portion, an embossed measuring unit, a measuring unit defining a boundary, and an engraved peripheral part To form.

At least one of the steps of forming the semiconductor layer, the gate electrode, the source and drain electrodes, and the pixel electrode may use a photolithography process using the photoresist pattern as an etching mask. It is preferable to form a second alignment key having a boundary with a spacing. Here, the second alignment key may be formed as an embossed or a trench.

The alignment key is embossed in the periphery and preferably has a display unit for displaying the shape of the first alignment key, and the measurement unit may be formed in a plurality of points, lines, or bars.

The gate insulating film is preferably formed of a first gate insulating film having the same shape as the semiconductor layer and a second gate insulating film covering the first gate insulating film. The first gate insulating film may be formed by forming an insulating film on the polycrystalline silicon film and then etching the insulating film together in the semiconductor layer forming step.

In this case, the thin film transistor array panel may be formed of one substrate of a liquid crystal display or an organic light emitting display.                     

In the thin film transistor array panel according to the exemplary embodiment of the present invention, a semiconductor layer having a source region and a drain region doped with impurities and a channel region positioned between the source region and the drain region is formed on the insulating substrate, and the semiconductor layer is formed thereon. A gate insulating film including a first gate insulating film and a second gate insulating film formed on the insulating substrate and covering the semiconductor layer and the first gate insulating film having the same shape as that of the substrate is formed. A gate electrode is formed on the gate insulating layer in the channel region, and a source electrode and a drain electrode connected to the source region and the drain region, and a pixel electrode connected to the drain electrode, respectively, on the first interlayer insulating layer covering the gate electrode. Formed.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, the structure of the polysilicon thin film transistor array panel according to the exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, in the thin film transistor array panel according to the exemplary embodiment of the present invention, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and the blocking layer 111 is disposed on the thin film transistor array panel 110. Is a polycrystalline silicon film 150 of a thin film transistor including a source region 153 and a drain region 155 doped with a high concentration of n-type impurities, and a channel region 154 which is not doped with impurities. Formed. In this case, the polysilicon film 150 is positioned between the source region 153 and the channel region 154, between the drain region 155 and the channel region 154, and has a low concentration doped region in which n-type impurities are lightly doped. It is preferable to include.

The first gate insulating layer 401 having the same shape as the polycrystalline silicon film 150 and made of silicon nitride or silicon oxide is formed on the polycrystalline silicon film 150.

Subsequently, a second gate insulating film 402 made of silicon oxide or silicon nitride is formed on the insulating substrate 110 to cover the polycrystalline silicon film 150 and the first gate insulating film 401. In this case, the gate insulating layer 140 includes a first gate insulating layer 401 and a second gate insulating layer 402.

On the gate insulating layer 140, a gate electrode 124 of a thin film transistor connected to a gate line (not shown) that transmits a scan signal and overlapping the channel region 154 of the polysilicon layer 150 is formed. have.

Meanwhile, a storage electrode for increasing the storage capacitance of the pixel may be disposed in the same layer as the gate electrode 124, and the storage electrode may overlap the polycrystalline silicon film 150.

A first interlayer insulating layer 801 is formed on the gate insulating layer 140 and the semiconductor layer 150 on which the gate electrode 124 is formed, and a source region 153 and a drain region (in the first interlayer insulating layer 801). First and second contact holes 143 and 145 exposing 155, respectively.

The first interlayer insulating layer 801 is connected to a data line (not shown) that crosses a gate line (not shown) and defines a pixel area, and is connected to the source region 153 through the first contact hole 143. The source electrode 173 of the connected thin film transistor is formed.

In addition, the drain electrode, which is connected to the drain region 155 through the second contact hole 145, faces the source electrode 173 at a distance apart from the source electrode 173 at the same layer as the source electrode 173. 175 is formed.

A second interlayer insulating layer 802 is formed on the first interlayer insulating layer 801 on which the source electrode 173, the drain electrode 175, and the data line 171 are formed. The third contact hole 185 exposing the electrode 175 is formed.

The pixel electrode 190 connected to the drain electrode 175 through the third contact hole 185 is formed in each pixel area on the second interlayer insulating layer 802.                     

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.

2A through 2G are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 3A and 3B illustrate a manufacturing method of a thin film transistor array panel according to another exemplary embodiment. 4A and 4B are sectional views illustrating a method of arranging multilayer thin films using alignment keys in a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention. 4C is a cross-sectional view of the thin film transistor array panel of FIG. 4B taken along line IVc-IVc ', and FIGS. 5A and 5C are alignments used in the method of manufacturing the thin film transistor array panel according to another exemplary embodiment of the present invention. FIG. 6A is a layout view illustrating the structure of a key, respectively. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb ′.

First, as shown in FIG. 2A, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO 2) or silicon nitride (SiN x). An amorphous silicon film is deposited on the blocking layer 111 to form an amorphous silicon film.

Thereafter, the amorphous silicon film is crystallized into amorphous silicon through laser annealing, furnace annealing, or solid crystallization to form a polycrystalline silicon film 150.

Subsequently, as shown in FIG. 2B, a first insulating film 401 is formed by depositing an insulating material such as silicon nitride or silicon oxide on the substrate 110 and then using a photolithography process using a photoresist pattern as an etching mask. The polysilicon film 150 and the first insulating film 401 are patterned together to form the semiconductor layer 150 and the first gate insulating film 401. In the manufacturing method according to the exemplary embodiment of the present invention, the surface of the semiconductor layer 150 is not exposed to the photolithography process condition by stacking and patterning the first insulating layer 401 on the polysilicon layer 150. Therefore, the surface of the semiconductor layer 150 can be completely prevented from being contaminated by the photosensitive material used in the photolithography process, thereby improving the characteristics of the thin film transistor and at the same time inducing uniform characteristics. As a result, the characteristics of the display device can be improved.

Meanwhile, in the method of manufacturing a thin film transistor array panel according to another exemplary embodiment of the present invention, as shown in FIG. 3A, the polysilicon film 150 and the first insulating film 401 are patterned together, and then the first insulating film 401 is formed. Can be removed. In the method of manufacturing a semiconductor device, when forming a semiconductor device with a multi-layered thin film, when the respective thin films are patterned, alignment keys are formed in the same layer as the thin film for alignment between layers, and the alignment key has a step. Detect and align between layers. By the way, in the process of crystallizing the amorphous silicon thin film with the polycrystalline silicon film 150 (see FIG. 2A), the grains grow and stop the growth of the grains at the portions where the grains meet each other, and in this portion the projections on the polysilicon film 150 ( 151, see FIG. 3A). The protrusion 151 has a step so that the protrusion formed on the alignment key made of polysilicon when performing the alignment between the layers acts as a noise when detecting the step of the alignment key to generate mis-alignment between the layers. Act as a cause. Therefore, in another embodiment of the present invention, as described above, the first insulating layer 401 is etched and removed. Then, a portion having a step in the etching process and a protruding portion are removed when the first insulating layer 401 is etched, so that the step of the protrusion 151 ′ formed in the polysilicon film 150 becomes very low. Therefore, when the alignment between layers is performed, the projection 151 'does not generate noise in the alignment key made of polycrystalline silicon, so that the alignment between layers can be performed accurately.

At this time, also in the manufacturing method according to the present embodiment, as described above, the polycrystalline silicon film 150 and the first gate insulating film 401 for the interlayer alignment of the thin film as shown in FIGS. 4A and 4C at the edge of the substrate 110. The first alignment key 500 is formed of the same layer as. At this time, the first alignment key 500 is embossed, used as a reference for measuring the distance for alignment with other thin films formed thereafter, and defines the outer edge of the first alignment key 500 to emboss Consists of the measuring unit 501 and the embossed to form a boundary between the display unit 502 and the measuring unit 501 to display the shape of the alignment key 500, such as "P" character and the display unit 502 ) And a peripheral portion 503 positioned between the measuring portion 501.

Subsequently, as illustrated in FIG. 2C, an insulating material of silicon nitride and silicon oxide is sequentially deposited on the substrate 110 on which the polycrystalline silicon film 150 is formed, and the second gate insulating film 402 is stacked to form a gate insulating film ( 140). The gate metal layer 120 is formed by depositing a single or multilayer film made of aluminum, chromium, molybdenum, or an alloy thereof on the gate insulating layer 140, and then forming a photoresist layer on the gate metal layer 120. The photoresist film is exposed and developed by a photo process using a mask to form the photoresist pattern 52.

At this time. As shown in FIGS. 4B and 4C, the second alignment key 54 is formed of the same layer as the photoresist pattern 52 to align the gate electrode 124 which is subsequently patterned. At this time, the second alignment key 54 is embossed, and consists of four bar shapes parallel to the sides of the first alignment key 500. The boundary defining the embossment of the second alignment key 54 is substantially parallel to the measurement unit 501 of the first alignment key 500.

Here, the measurement unit of the first alignment key 500 is irradiated with light 801 to the first and second alignment keys 500 and 54 using the alignment detector 800 to detect the state of the alignment between the layers. The distances a, b, c, and d of the 501 and the second alignment key 54 are measured to confirm that the gate pattern mask is correctly aligned to form the photoresist pattern 52 at the correct position. At this time, in the embodiment of the present invention, since the peripheral portion 503 of the first alignment key 500 defining the measurement unit 501 is formed in an intaglio, even when protrusions are formed in the polycrystalline silicon film 150 in the crystallization process, the first portion is formed. When measuring the distance between the alignment key 500 and the second alignment key 54, noise due to projections does not occur. Therefore, in the embodiment of the present invention it is possible to minimize the noise caused by the projections to prevent misalignment.                     

Meanwhile, in another embodiment of the present invention, as shown in FIG. 5A, the measuring units 501 may be arranged in a dot shape, or may be formed linearly as shown in FIG. 5B.

In addition, in another embodiment of the present invention, as shown in Figure 6a and 6b, the measuring unit 501 of the first alignment key 500 may be formed in the shape of a rod, the second alignment key 55 is the front Unlike the embodiment, the photoresist pattern 550 may be formed in a trench to form an intaglio.

Subsequently, if misalignment occurs when the distance between the measuring unit 501 of the first alignment key 500 and the second alignment keys 54 and 55 is measured, the photoresist patterns 52 and 550 are formed again by a photographic process. If correct, proceed to next step.

In this case, the gate metal film 120 preferably includes two films having different physical properties. One film is made of a low resistivity metal such as aluminum (Al) or an aluminum alloy (eg aluminum-neodymium (AlNd) alloy) to reduce the delay or voltage drop of the gate signal. . In contrast, other membranes have excellent physical, chemical and electrical contact properties with other materials, particularly indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum-tungsten (MoW). ) Alloy], and chromium (Cr).

Next, as shown in FIG. 2D, the gate metal film 120 is patterned using the photoresist pattern 52 as a mask to form a gate line having the gate electrode 124.                     

At this time, the cut surface sidewall of the gate electrode 124 is preferably formed to be inclined in order to increase the adhesion to the upper layer formed later.

Subsequently, the source region 153 and the drain region 155 are formed in the semiconductor layer 150 by doping the n-type impurity ions at high concentration using the gate electrode 124 as a doping mask while the photoresist pattern 52 is removed or left as it is. ) And define the channel region 154. Subsequently, it is preferable to form a low concentration doped region by doping the n-type conductive impurities on both sides of the channel region 154 at a low concentration using a scanning apparatus or an ion beam apparatus.

Subsequently, as shown in FIG. 2E, an insulating material is stacked on the entire surface of the substrate 110 to cover the gate electrode 124 to form a first interlayer insulating film 801. Afterwards, the first interlayer insulating layer 801 is patterned together with the gate insulating layer 140 in a photolithography process using a mask to expose the first contact hole 143 and the second contact to expose the source region 153 and the drain region 155. Sphere 145 is formed.

Subsequently, as illustrated in FIG. 2F, a data metal layer is formed on the first interlayer insulating layer 801, and then patterned by a photolithography process using a mask to connect to a source electrode 173 connected to a data line for transmitting a data signal. And a drain electrode 175 is formed. The source electrode 173 is connected to the source region 153 through the first contact hole 143, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 14, respectively.

The data line 171 is formed by depositing a plurality of conductive materials including a single layer of an aluminum-containing metal such as aluminum or an aluminum alloy, molybdenum or molybdenum alloy, an aluminum alloy layer, and a chromium (Cr) or molybdenum (Mo) alloy layer. The metal film for data is formed and then patterned. In this case, the data metal film may also be patterned using the same conductive material and etching method as the gate metal film, and the cut surfaces of the source electrode 173 and the drain electrode 175 may have a tapered structure having a constant inclination for adhesion to the upper layer. It is preferable to form.

As shown in FIG. 2G, an organic material or plasma chemical vapor deposition having excellent planarization characteristics and photosensitivity on the first interlayer insulating layer 801 including the source electrode 173 and the drain electrode 175. A low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by enhanced chemical vapor deposition (PECVD) is stacked to form a second interlayer insulating film 802. Thereafter, the second interlayer insulating layer 802 is patterned by a photolithography process using a mask to form a third contact hole 185 exposing the drain electrode 175.

As shown in FIG. 1, an indium tin oxide (ITO), an indium zinc oxide (IZO), or the like, which is a transparent material, is deposited on the second interlayer insulating layer 802 including the third contact hole 185, and then patterned. A connection member (not shown) for electrically connecting the pixel electrode 190 and the plurality of signal lines is formed. The pixel electrode 190 is connected to the drain electrode 175d through the third contact hole 143. The contact auxiliary member is disposed over the fourth contact hole (not shown) formed over the first and second interlayer insulating films 801 and 802, the first and second interlayer insulating films 801 and 802, and the gate insulating layer 140. It is connected to the connection part electrically connected to the data line 171 and the gate line 121 through the fifth contact hole (not shown) formed.

In this embodiment, the method of forming the first aligner and the second alignment key can be equally applied to the step of forming the other silicon as well as the step of forming the polycrystalline silicon film.

Next, the manufacturing method according to the exemplary embodiment of the present invention will be described by applying to the manufacturing method of the thin film transistor array panel for an organic light emitting display device.

First, the structure of the thin film transistor array panel for an organic light emitting display device will be described with reference to FIGS. 7 to 9.

A blocking layer 111 made of silicon oxide, silicon nitride, or the like is formed on the insulating substrate 110, and first and second polycrystalline silicon films 150a and 150b are formed on the blocking layer 111, and a second layer is formed on the insulating layer 110. A capacitor polycrystalline silicon film 157 is connected to the polycrystalline silicon film 150b. The first polycrystalline silicon film 150a includes first transistor parts 153a, 154a, and 155a, and the second polycrystalline silicon film 150b includes second transistor parts 153b, 154b, and 155b. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. In this case, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be doped with n-type impurities. . Here, the first transistor portions 153a, 154a, and 155a are semiconductors of the switching thin film transistor, and the second transistor portions 153b, 154b, and 155b are semiconductors of the driving thin film transistor.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon films 150a, 150b, and 157. In this case, the gate insulating layer 140 includes the first gate insulating layer 401 formed in the same shape as the polycrystalline silicon layers 150a and 150b and the second gate insulating layer 402 formed on the entire surface. do.

On the gate insulating layer 140, a gate line 121 including a conductive film made of a low resistance conductive material such as aluminum or an aluminum alloy, first and second gate electrodes 124a and 124b, and a storage electrode 133 are formed. have. The first gate electrode 124a is connected to the gate line 121 to have a branch shape, and overlaps the channel portion (first channel portion 154a) of the first transistor, and the second gate electrode 124b is a gate. It is separated from the line 121 and overlaps with the channel portion (second channel portion 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 124b and overlaps the storage electrode portion 157 of the polysilicon film.

A first interlayer insulating layer 801 is formed on the gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133, and transmits a data signal on the first interlayer insulating layer 801. A data line 171, a linear power supply voltage electrode 172 for supplying a power supply voltage, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed. have. The first source electrode 173a is a part of the data line 171 and has a branch shape, and the first source region is formed through the contact hole 181 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. The contact hole 153a is connected to the second source electrode 173b and has a branch shape as part of the electrode 172 for the power supply voltage, and penetrates the first interlayer insulating film 801 and the gate insulating film 140. It is connected to the second source region 153b through 184. The first drain electrode 175a is connected to the first drain region 155a and the second gate electrode 124b through the contact holes 182 and 183 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. They are in electrical contact with each other by contact. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 186 penetrating through the first interlayer insulating layer 801 and the gate insulating layer 140, and the data line 171. It is made of the same material.

A second interlayer insulating layer 802 made of silicon nitride, silicon oxide, or an organic insulating material is formed on the data line 171, the power voltage electrode 172, and the first and second drain electrodes 175a and 175b. The second interlayer insulating film 802 has a contact hole 185 exposing the second drain electrode 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the second interlayer insulating layer 802 through the contact hole 185. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum or silver alloy. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 190 made of a transparent conductive material is applied to a bottom emission organic light emitting diode that displays an image in a downward direction of the display panel. The pixel electrode 190 made of an opaque conductive material is applied to top emission organic light emitting diodes that display an image in an upper direction of the display panel.

An organic insulating material is formed on the second interlayer insulating layer 802, and a partition 803 is formed to separate the organic light emitting cells. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled. The partition wall 803 serves as a light shielding film by exposing and developing a photosensitive agent including a black pigment, and at the same time, the forming process can be simplified. An organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 803. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 may be made of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. .                     

The driving of such an organic light emitting panel will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage or data voltage applied through the data line 171 is transferred to the second gate electrode 124b. When the image signal voltage is applied to the second gate electrode 124b, the second transistor is turned on so that a current caused by the data voltage flows to the pixel electrode 190 and the organic light emitting layer 70, and the organic light emitting layer 70 has a specific wavelength band. Emits light. In this case, the amount of light emitted from the organic light emitting layer 70 varies according to the amount of current flowing through the second thin film transistor, thereby changing the luminance. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the difference between the image signal voltage transmitted through the first transistor and the power supply voltage transmitted through the power supply voltage electrode 172.

Next, a method of manufacturing the thin film transistor array panel for the OLED display will be described with reference to FIGS. 10 to 23B and FIGS. 7 to 9.

First, as shown in FIGS. 10 to 11B, a silicon oxide or the like is deposited on the substrate 110 to form a blocking layer 111, and an amorphous silicon film is deposited on the blocking layer 111. The deposition of the amorphous silicon film may be performed by low temperature chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVE), or sputtering. Next, the amorphous silicon film is irradiated with a laser beam to crystallize into single crystal or polycrystalline silicon. The first insulating film is stacked on the polycrystalline silicon film and patterned together by a photolithography process using a polysilicon film and a mask to form the first and second polycrystalline silicon films 150a and 150b, the storage electrode part 157, and the first gate insulating film. 401 is formed. At this time, the first alignment key 500 (see FIGS. 4A to 6B) is formed as in the previous embodiment.

Next, as shown in FIGS. 12 to 13B, the gate insulating layer 140 is formed by stacking the second insulating layer 402 on the polycrystalline silicon films 150a, 150b, and 157. In this embodiment as well, the surface of the polysilicon films 150a and 150b can be prevented from being contaminated in the same manner as in the previous embodiment.

Subsequently, the gate metal layer 120 is deposited, the photoresist film is applied, exposed and developed to form the first photoresist pattern PR1 and the second alignment key 54 (see the previous embodiment drawings), and then the misalignment is inspected. Subsequently, the gate metal layer 120 is etched using the first photoresist pattern PR1 as a mask to form the second gate electrode 124b and the storage electrode 133, and the exposed polycrystalline silicon of the second transistor unit 150b. The p-type impurity ions are implanted into the film to define the channel region 154b and form the second source region 153b and the second drain region 155b. In this case, the polycrystalline silicon film of the second transistor unit 150a is covered and protected by the first photoresist film pattern PR1 and the gate metal layer 120. Also in this embodiment, an alignment key is formed in the same manner as in the previous embodiment to prevent misalignment.

Next, as shown in FIGS. 14 to 15B, the first photoresist pattern PR1 is removed, the photoresist is newly applied, exposed to light, and developed to form a second photoresist pattern PR2. By etching the gate metal layer 120 using the second photoresist pattern PR2 as a mask, the first gate electrode 124a and the gate line 121 are formed, and the first transistor portion 150a is exposed to the polycrystalline silicon film. The n-type impurity ions are implanted to define the channel region 154a and form the first source region 153a and the first drain region 155a. At this time, the second transistor unit 150a and the storage electrode unit 157 are covered and protected by the second photosensitive film pattern PR2.

Next, as shown in FIGS. 16 to 17B, a first interlayer insulating film 801 is stacked on the gate lines 121 and 124b, the second gate electrode 124b, and the storage electrode 133, and the gate insulating film 140 is formed. Photo-etched together, the contact holes 181, 182, 184, and 186 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively. And a contact hole 183 exposing one end of the second gate electrode 124b.

Next, as shown in FIGS. 18 through 19B, the data metal layer is stacked and photo-etched to form the data line 171, the power voltage electrode 172, and the first and second drain electrodes 175a and 175b. In this case, the pixel electrode 190 to be formed later may be formed together. When the pixel electrode 190 is formed of a transparent conductive material such as ITO or IZO, the pixel electrode 190 is formed through a separate photolithography process.

Next, as shown in FIGS. 20 to 21B, the second interlayer insulating layer 802 is stacked and patterned by a photolithography process using a mask to form a contact hole 185 exposing the second drain electrode 175b.

Subsequently, as shown in FIGS. 22 to 23B, the pixel electrode 190 is formed by stacking and patterning a transparent conductive material or a conductive material having low resistance.

Next, as shown in FIGS. 7 to 9, an organic film including a black pigment is coated on the second interlayer insulating film 802 on which the pixel electrode 190 is formed, and exposed and developed to form a partition 803. The organic emission layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 usually has a multilayer structure. The organic light emitting layer 70 is formed by masking, deposition, and inkjet printing.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. When the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed of a metal having excellent reflectivity.

In the organic light emitting diode display panel according to the exemplary embodiment of the present invention and a method of manufacturing the same, the pixel electrode 190 is formed of an opaque conductive film, and the common electrode 270 is formed of a transparent conductive material to form an image. The top emission method of displaying in the upper direction of the display panel has been described.

On the other hand, in the manufacturing method according to the embodiment of the present invention, when the pixel electrode 190 is formed of the transparent conductive material and the common electrode 270 is formed of the opaque conductive material, the bottom emission of displaying the image below the display. The same applies to the thin film transistor array panel of the system and the manufacturing method thereof.

As described above, in the present invention, the polysilicon layer is covered with the gate insulating film and then patterned to prevent contamination of the surface of the semiconductor layer, thereby ensuring stable and uniform thin film transistors. In addition, by forming the peripheral portion of the alignment key except the display portion intaglio, it is possible to remove the noise caused by the projections to accurately align the alignment between the layers to proceed the photo etching process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (16)

delete delete delete delete Crystallizing the amorphous silicon thin film on the insulating substrate to form a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer, Forming a gate insulating film covering the semiconductor layer; Forming a gate electrode on the gate insulating layer of the semiconductor layer; Implanting impurities into the semiconductor layer to form source and drain regions on both sides of the gate electrode; Forming a first interlayer insulating film covering the gate electrode; Forming source and drain electrodes electrically connected to the source and drain regions, respectively; Forming a second interlayer insulating film covering the source and drain electrodes; Forming a pixel electrode connected to the drain electrode; The forming of the semiconductor layer includes forming a first alignment key, The first alignment key is an embossed display unit that displays the shape of the first alignment key, defines an outline of the first alignment key, and includes an embossed measuring unit, and is disposed between the display unit and the measuring unit. Encompassing and engraved periphery Method of manufacturing a thin film transistor array panel. The method of claim 5, At least one of the semiconductor layer, the gate electrode, the source and drain electrodes, and the pixel electrode forming step may use a photolithography process using a photoresist pattern as an etching mask, and the first alignment key in the photoresist pattern forming step. And forming a second alignment key having a boundary having a predetermined distance from the boundary of the measuring unit. In claim 6, And the second alignment key is embossed or formed in a trench. delete The method of claim 5, The measuring unit is a method of manufacturing a thin film transistor array panel formed in the shape of a plurality of points, lines or bars. The method of claim 5, And the gate insulating film is formed of a first gate insulating film having the same shape as that of the semiconductor layer and a second gate insulating film covering the first gate insulating film. In claim 10, The first gate insulating film, And forming an insulating film on the polycrystalline silicon film and then etching the polycrystalline silicon film and the insulating film together in the semiconductor layer forming step. The method of claim 5, The thin film transistor array panel is formed of a substrate of a liquid crystal display device. The method of claim 5, The thin film transistor array panel is formed of a substrate of an organic light emitting diode display device. delete delete delete

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