KR101209052B1 - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

The present invention improves the characteristics of a thin film transistor. A polycrystalline semiconductor layer formed on the insulating substrate and the insulating substrate and having a channel region, a source region and a drain region, a gate line formed on or below the polycrystalline semiconductor layer, and a first insulating film formed between the polycrystalline semiconductor layer and the gate line. And a storage electrode line formed on the same layer apart from the gate line, and the gate line and the storage electrode line include an amorphous silicon film and a metal film. As such, the contact resistance can be reduced by increasing the adhesion between the metal film and the amorphous silicon film by varying the side slopes by placing the amorphous silicon film and heat treating the substrate, thereby improving the characteristics and reliability of the thin film transistor.

Thin film transistor, contact hole, data line, drain electrode

Description

The manufacturing method of a thin film transistor and a thin film transistor display panel {THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 and 5 are layout views of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

4 and 6 are cross-sectional views of the thin film transistor array panels of FIGS. 3 and 5 taken along lines IV-IV 'and VI-VI', respectively.

7 and 8 are layout views in an intermediate step of manufacturing the thin film transistor array panel illustrated in FIGS. 3 to 6 according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of the thin film transistor array panel of FIGS. 7 and 8 taken along lines IX-IX 'and IX'-IX' '.

10 and 11 are layout views of a thin film transistor array panel in the next step of FIGS. 7 and 8;

FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIGS. 10 and 11 cut along the lines XII-XII 'and XII'-XII' '.

FIG. 13 is a cross-sectional view of the thin film transistor array panel according to the next step of FIG. 12, cut along the lines XII-XII ′ and XII′-XII ″, and

FIG. 14 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the lines XII-XII 'and XII'-XII' ', and

15 and 16 are layout views of a thin film transistor array panel in the next step of FIGS. 10 and 11;

FIG. 17 is a cross-sectional view of the thin film transistor array panel of FIGS. 15 and 16 cut along the lines XVII-XVII ', XVII'-XVII' ', and

18 and 19 are layout views of a thin film transistor array panel in the next step of FIGS. 15 and 16.

20 is a cross-sectional view of the thin film transistor array panel of FIGS. 18 and 19 cut and pasted along lines XX-XX 'and XX'-XX' '.

21 and 22 are layout views of the thin film transistor array panel in the next step of FIGS. 18 and 19, and

FIG. 23 is a cross-sectional view of the thin film transistor array panel of FIGS. 22 and 23 taken along lines XIII-XIII 'and XIII'-XIII' '.

※ Explanation of symbols on main parts of drawing ※

110: insulating substrate 121: gate line

124a: gate electrode 131: sustain electrode line

137: expansion portion 140: gate insulating film

153a: source region 154a: channel region

155a: drain region 171: data line

173a: source electrode 175a: drain electrode

191: pixel electrode

The present invention relates to a method of manufacturing a thin film transistor and a thin film transistor array panel, and more particularly, to a method of manufacturing a polycrystalline silicon thin film transistor array panel.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting diode display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor is formed of a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor layer facing the gate electrode with an insulating layer therebetween. The data signal from the data line is transferred to the pixel electrode in accordance with the scanning signal of. In this case, the semiconductor layer of the thin film transistor is made of polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon).

Since polycrystalline silicon has a large electron mobility used for amorphous silicon, the use of a polycrystalline silicon thin film transistor enables high-speed driving. In addition, the driving circuit for driving the thin film transistor array panel may be formed on the substrate in the form of a thin film transistor without attaching a separate integrated circuit chip.

On the other hand, the gate line and the gate electrode is made of a low-resistance metal such as aluminum, but they do not vary in the side inclination angle, that is, the tapered structure, and may have a large contact resistance with other metals.

For this reason, the characteristic of a thin film transistor may fall.

Therefore, the technical problem of this invention is improving the characteristic of a thin film transistor.

A method of manufacturing a thin film transistor according to the present invention includes an insulating substrate, a polycrystalline semiconductor layer formed on the insulating substrate and having a channel region, a source region and a drain region, a gate line formed above or below the polycrystalline semiconductor layer, A first insulating film formed between the polycrystalline semiconductor layer and the gate line, and a storage electrode line formed on the same layer apart from the gate line, wherein the gate line and the storage electrode line include an amorphous silicon film and a metal film. .

The amorphous silicon film may include conductive impurities.

The metal film may include aluminum or molybdenum, and the metal film may be formed as a single layer.

The polycrystalline semiconductor layer may include polycrystalline silicon.

A semiconductor layer formed over the substrate, a first insulating film formed over the semiconductor layer, a gate line formed over the first insulating film and including a first amorphous silicon film and a metal film, a second insulating film formed over the gate line, And it may be formed on the second insulating film.

The first amorphous silicon film may include conductive impurities.

The metal film may include aluminum or molybdenum, and the metal film may be formed as a single layer.

The metal film may be positioned on the first amorphous silicon film.

The method may further include a second amorphous silicon film formed on the metal film.

The metal film may be located under the first amorphous silicon film.

A sustain electrode formed on the first insulating film and including an amorphous silicon film and a metal film may be further included.

The semiconductor layer may include polycrystalline silicon.

The display device may further include a passivation layer formed on the data line and a pixel electrode formed on the passivation layer.

Forming a semiconductor layer on the substrate, depositing a first insulating film on the semiconductor layer, forming a gate electrode including a first amorphous silicon film and a metal film on the first insulating film, and forming a second electrode on the gate electrode Forming an insulating film, and forming a source electrode and a drain electrode on the second insulating film.

The first amorphous silicon film may include conductive impurities.

The metal film may include aluminum or molybdenum, and the metal film may be formed as a single layer.

The forming of the gate electrode may include stacking the first amorphous silicon film, stacking the metal film on the first amorphous silicon film, and patterning the metal film and the first amorphous silicon film. .

The patterning of the metal layer and the first amorphous silicon layer may include etching the metal layer and the first amorphous silicon layer in order to form an upper layer and a preliminary lower layer of the gate electrode, and implanting impurity ions into the semiconductor layer to form a high concentration. Forming an impurity region, a channel region and a low concentration impurity region, and removing a portion of the preliminary lower layer using the upper layer of the gate electrode as a mask to form a lower layer of the gate electrode.

The width of the preliminary lower layer may be wider than the width of the upper layer of the gate electrode.

The forming of the gate electrode may further include heat treating the metal film and the first amorphous silicon film.

The heat treatment may be carried out at 200 ℃ to 300 ℃.

The semiconductor layer may include polycrystalline silicon.

The method may further include forming a passivation layer on the source electrode and the drain electrode, and forming a pixel electrode on the passivation layer.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

A manufacturing method of a thin film transistor and a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display that is an example of a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel unit 300, a gate driver 400 and a data driver 500 connected thereto. ), A gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

Referring to FIG. 1, the display panel unit 300 is connected to a plurality of display panel lines G ₁ -G _n , D ₁ -D _m when viewed in an equivalent circuit and arranged in a substantially matrix form. And a plurality of pixels PX constituting a display area DA.

Referring to FIG. 2, the display panel 300 of the liquid crystal display includes lower and upper display panels 100 and 200 and a liquid crystal layer 3 therebetween. In the case of an organic light emitting diode display, the display panel 300 may include only one display panel.

The display signal lines G ₁ -G _n and D ₁ -D _m transmit a data signal and a plurality of gate lines G ₁ -G _n that transmit a gate signal (also called a “scan signal”). It includes a data line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes at least one switching element (not shown) such as a thin film transistor and at least one capacitor (not shown).

Referring to FIG. 2, each pixel of the liquid crystal display device (PX) is, for example, i-th gate line (G _i) and j th data lines (D _j) pixel display signal lines (G _i, D _j, defined as ) And a switching element Q connected thereto, and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. The display signal lines G _{i and} D _j are disposed on the lower display panel 100, and the storage capacitor C _ST may be omitted as necessary.

The switching element Q such as the polysilicon thin film transistor is provided on the lower panel 100 and connected to the control terminal and the data line D ₁ -D _m , which are connected to the gate lines G ₁ -G _n , respectively. It is a three-terminal device that has an input terminal and an output terminal connected to a liquid crystal capacitor (C _LC ) and a storage capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, a pixel electrode 191 of the lower panel 100 and a common electrode 270 of the upper panel 200, and a liquid crystal layer 3 between the two electrodes 191 and 270. It functions as a dielectric. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor C _ST is a capacitor that assists the liquid crystal capacitor C _LC . A separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 overlap each other, and the separate signal line A predetermined voltage such as the common voltage Vcom is applied to the. However, the storage capacitor C _ST may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

In order to implement color display, each pixel PX uniquely displays one of a plurality of primary colors (spatial division) or alternately displays a plurality of primary colors (time division), so that the spatial In time, the desired color is indicated. Examples of the primary colors include three primary colors including red, green, and blue. FIG. 2 shows an example of spatial division in which each pixel PX includes a color filter 230 representing one color of the primary colors in a corresponding region facing the pixel electrode 191 in the upper panel 200. have. Alternatively, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the display panel unit 300.

Each pixel PX of the organic light emitting diode display includes a switching transistor (not shown) connected to the display signal lines G ₁ -G _n , D ₁ -D _m , a driving transistor (not shown) connected thereto, A storage capacitor (not shown), and an organic light emitting diode (OLED) (not shown). The light emitting diode includes an anode electrode (not shown) and a cathode electrode (not shown) and an organic light emitting member (not shown) therebetween.

Referring back to FIG. 1, the gray signal generator 800 generates a plurality of gray signals related to the transmittance of the pixel PX. The gray level signal generator 800 for the liquid crystal display generates two gray level voltages each having a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to receive a gate signal having two values equal to the gate on voltage Von and the gate off voltage Voff, respectively. G ₁ -G _n ). The gate driver 400 is integrated in the display panel 300 and includes a plurality of driving circuits (not shown). Each driving circuit constituting the gate driver 400 is connected to one gate line G ₁ -G _n and includes a plurality of N-type, P-type, and complementary polysilicon thin film transistors. However, the gate driver 400 may be mounted on the display panel 300 in the form of an integrated circuit (IC) chip or on a flexible printed circuit (FPC) film. In the latter case, a flexible printed circuit film is attached onto the display panel unit 300.

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 and selects a gray voltage from the gray signal generator 800 to select the gray voltage as the data voltage D ₁ -D _m. ) Is applied. The data driver 500 may also be integrated with the display panel unit 300, or may be mounted on the display panel unit 300 in the form of one or more integrated circuit chips, or may be attached to the display panel unit 300 by a flexible printed circuit. FPC) film can be mounted.

The driving units 400 and 500 or the flexible printed circuit film on which they are mounted are positioned in a peripheral area positioned outside the display area DA in the display panel 300.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like, and may be mounted on a printed circuit board (PCB).

Next, an example of the detailed structure of the liquid crystal display shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 6.

3 and 5 are layout views of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 4 and 6 are IV-IV and VI-VI lines of the thin film transistor array panel of FIGS. 3 and 5, respectively. The cross section is cut along the side.

Here, it is assumed that the thin film transistor of the pixel PX is N type and the thin film transistor of the gate driver 400 is P type.

A blocking film 111 made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is formed on an insulating substrate 110 made of transparent glass or plastic. The blocking film 111 may have a multilayer structure.

A plurality of pixel portion island semiconductors 151a and a driving island island semiconductor 151b are formed on the blocking layer 111.

Each of the semiconductors 151a and 151b includes an extrinsic region containing conductive impurities and an intrinsic region containing little conductive impurities, and a heavily doped region having a high impurity concentration in the impurity region. region and lightly doped region with low impurity concentration.

The intrinsic region of the pixel portion semiconductor 151a includes a channel region 154a, and the high concentration impurity region is sequentially separated from the source region 153a, which is sequentially separated around the channel region 154a. A region 156a and a drain region 155a, wherein the low concentration impurity region 152 is located between the intrinsic regions 154a and 157 and the high concentration impurity regions 153a, 155a and 156a and is wide in width. narrow. In particular, the low concentration impurity region 152 located between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154a is referred to as a lightly doped drain region (LDD region). do. The low concentration doped region 152 prevents leakage current or punch through from the thin film transistor, and can be replaced with an offset region containing no impurities, and such a low concentration doping. The drain region may be omitted.

The intrinsic region of the driver semiconductor 151b includes a channel region 154b, and the high concentration impurity region includes a source region 153b and a drain region 155b.

Examples of the P-type conductive impurity include boron (B) and gallium (Ga), and examples of the N-type impurity include phosphorus (P) and arsenic (As).

A gate insulating layer 140 made of silicon nitride or silicon oxide is formed on the semiconductors 151a and 151b and the blocking layer 111.

A gate conductor including a plurality of gate lines 121 including a gate electrode 124a and a plurality of control electrodes 124b and a plurality of storage electrode lines on the gate insulating layer 140. An electrode line 131 is formed.

The gate line 121 transmits the gate signal and extends mainly in the horizontal direction. The gate electrode 124a extends downward from the gate line 121 to cross the pixel portion semiconductor 151b, and overlaps the channel region 154a. Each gate line 121 may include a wide end portion for connection with another layer or an external driving circuit. When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The control electrode 124b is separated from the gate line 121, and overlaps the channel region 154b of the driver semiconductor 151b and is connected to another signal line (not shown) to which a control signal is applied.

The storage electrode line 131 receives a predetermined voltage such as a common voltage applied to a common electrode (not shown), and is extended upward to extend the wider portion 137 and the vertical portion 133 extending upward. It includes.

The gate conductors 121 and 124b and the storage electrode line 131 include a lower layer and an upper layer. The lower layer is made of amorphous silicon (a-Si), and the amorphous silicon may include conductive impurities. The top layer may be made of an aluminum-based metal such as aluminum-niodymium (AlNd) and a molybdenum-based metal such as molybdenum-tungsten (MoW). The gate conductors 121 and 124b and the storage electrode lines 131 are formed of a double layer of an aluminum (alloy) or molybdenum (alloy) layer and an amorphous silicon upper layer, an amorphous silicon lower layer, and an aluminum (alloy) or molybdenum (alloy) interlayer film It may have a triple film structure of an amorphous silicon upper film.

In the lower layers of the gate conductors 121 and 124b and the storage electrode line 131, aluminum or molybdenum particles of the upper layer may be diffused. This increases the adhesion between the lower layer and the upper layer and lowers the resistance of the lower layer. .

3 to 6, the lower layer p and the upper layer q are denoted by reference numerals for the gate electrode 124a, the control electrode 124b, and the sustain electrode 137.

The gate electrode 124a, the control electrode 124b, and the sustain electrode 137 may overlap the lightly doped region 152.

Side surfaces of the gate conductors 121 and 124b and the storage electrode line 131 may be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

An interlayer insulating film 160 is formed on the gate conductors 121 and 124b and the storage electrode line 131. The interlayer insulating layer 160 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. Among the organic insulators, the interlayer insulating layer 160 may be formed by having photosensitivity, and the surface of the interlayer insulating layer 160 may be flat.

A plurality of contact holes 163, 165, 166, and 167 exposing the source and drain regions 153a, 153b, 155a, and 155b are formed in the interlayer insulating layer 160 and the gate insulating layer 140.

A plurality of data lines 171, a plurality of drain electrodes 175a, a plurality of input electrodes 173b, and a plurality of output electrodes 175b are disposed on the interlayer insulating layer 160. Data conductors are formed.

The data line 171 transmits a data signal and extends mainly in the vertical direction and crosses the gate line 121. Each data line 171 includes a source electrode 173a connected to the source region 153a through the contact hole 163, and includes a wide end portion for connecting to another layer or an external driving circuit. can do. When a data driving circuit (not shown) generating a data signal is integrated on the substrate 110, the data line 171 may be directly connected to the data driving circuit.

The drain electrode 175a is spaced apart from the source electrode 173a and connected to the drain region 155a through the contact hole 165. The drain electrode 175a is connected to the extension 137 and the vertical portion 133 of the storage electrode line 131. An overlapping extension 177 and a vertical portion 176 are included. The vertical portion 133 of the storage electrode line 131 is positioned between the vertical portion 176 of the drain electrode 175 and the boundary line facing the data line 171 to prevent signal interference therebetween.

The input electrode 173b and the output electrode 175b are separated from each other with respect to the control electrode 124b and may be connected to another signal line (not shown).

Like the gate conductors 121 and 121b, the data conductors 171, 172, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to 80 ° with respect to the surface of the substrate 110.

A passivation layer 180 including a lower passivation layer 180p and an upper passivation layer 180q is formed on the data conductors 171, 173b, 175a, and 175b and the interlayer insulating layer 160. The lower passivation layer 180p is made of an inorganic insulator such as silicon nitride or silicon oxide, and the upper passivation layer 180q is made of an organic material having excellent planarization characteristics. The upper passivation layer 180q may have photosensitivity and have a dielectric constant of 4.0 or less, such as a-Si: C: O and a-Si: O: F, which are formed by plasma enhanced chemical vapor deposition (PECVD). It may be made of a low dielectric constant insulating material.

The passivation layer 180 is provided with a plurality of contact holes 185 exposing the extension 177 of the drain electrode 175a. A plurality of contact holes (not shown) may also be formed in the passivation layer 180 to expose an end portion of the data line 171, and an end portion of the gate line 121 may be formed in the passivation layer 180 and the interlayer insulating layer 160. A plurality of contact holes (not shown) may be formed to reveal the gaps. The passivation layer 180 may be omitted in the driver.

A plurality of pixel electrodes 191 are formed on the passivation layer 180. The pixel electrode 191 is physically and electrically connected to the drain electrode 175a through the contact hole 185 and is made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof. Can lose.

The pixel electrode 191 is connected to the drain electrode 175a connected to the drain region 155a through the contact hole 185 to receive a data voltage from the drain region 155a and the drain electrode 175a. The pixel electrode 191 to which the data voltage is applied generates an electric field together with the common electrode 270 to which the common voltage is applied, thereby determining the direction of the liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 191 and 270 or An electric current is made to flow through a light emitting layer (not shown) between electrodes, and light is emitted.

Referring to FIG. 2, the pixel electrode 191 and the common electrode 270 form a liquid crystal capacitor C _LC to maintain an applied voltage even after the thin film transistor Q is turned off, and the storage capacitor C _ST is a pixel. A portion of the electrode 191 and the drain electrode 175a, and the storage electrode line 131 including the storage region 157 and the extension 137 are made to overlap.

When the passivation layer 180 is formed of an organic material having a low dielectric constant, the pixel electrode 191 may be overlapped with the data line 171 and the gate line 121 to improve the aperture ratio.

On the other hand, the gate conductors 121 and 124b and the storage electrode lines 131 may be under the semiconductors 154a and 154b, and the gate insulating layer 140 may also include the semiconductors 154a and 154b and the gate conductors 121 and 124b. ) And the storage electrode line 131.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 6 will be described in detail with reference to FIGS. 7 to 23.

7 and 8 are layout views in an intermediate step of manufacturing the thin film transistor array panel shown in FIGS. 3 to 6 according to an embodiment of the present invention, Figure 9 is a IX of the thin film transistor array panel of Figures 7 and 8 IX 'and IX'-IX' 'are sectional views cut and attached along the lines, FIGS. 10 and 11 are layout views of the thin film transistor array panel in the next steps of FIGS. 7 and 8, and FIGS. 12 and 11 are illustrated in FIGS. Fig. 13 is a cross-sectional view of the thin film transistor array panel cut along the lines XII-XII 'and XII'-XII' ', and FIG. 13 is a cross-sectional view of the thin film transistor array panel in the next step of FIG. 14 is a cross-sectional view taken along the line ″, and FIG. 14 is a cross-sectional view taken along the line XII-XII ′, XII′-XII '' of the thin film transistor array panel in the next step of FIG. FIG. 16 is a view of the thin film transistor array panel in the next step of FIGS. 10 and 11. FIG. 17 is a cross-sectional view of the thin film transistor array panel of FIGS. 15 and 16 cut along the lines XVII-XVII 'and XVII'-XVII' ', and FIGS. 18 and 19 are the next steps of FIGS. 15 and 16. FIG. 20 is a cross-sectional view of the thin film transistor array panel of FIG. 18 and FIG. 19 taken along the lines XX-XX 'and XX'-XX' ', and FIGS. 21 and 22 are shown in FIG. 19 is a layout view of a thin film transistor array panel in the next step of FIG. 19, and FIG. 23 is a cross-sectional view of the thin film transistor array panels of FIGS. 22 and 23 taken along lines XIII-XIII 'and XIII'-XIII' '.

First, as shown in FIGS. 7 to 9, the blocking layer 111 is formed on the transparent insulating substrate 110, and then, as amorphous silicon by chemical vapor deposition (CVD), sputtering, or the like. The formed semiconductor film is formed. The semiconductor film is then crystallized by laser annealing, furnace annealing, or sequential lateral solidification (SLS).

Then, the semiconductor film is patterned to form a plurality of pixel portion and driver island type semiconductors 151a and 151b.

Next, as shown in FIGS. 10 to 12, the gate insulating layer 140 is formed on the semiconductors 151a and 151b by a chemical vapor deposition method, and the like, and a metal made of an amorphous silicon film and an aluminum or molybdenum-based metal thereon. The films are laminated in sequence.

Here, the amorphous silicon film may have a sheet resistance value of 10 ⁹ Ω / □ or more, and n-type impurities such as phosphorus may be doped at a high concentration.

Thereafter, a heat treatment process of 200 ° C to 300 ° C is performed. This process causes the aluminum and molybdenum atoms of the metal film to diffuse into the amorphous silicon film, thereby increasing the adhesion between the metal film and the amorphous silicon film and thus lowering the contact resistance.

[Table 1] shows the contact surface resistance (Ω / □) after heat treatment of amorphous silicon (a-Si) or amorphous silicon (n + a-Si) in which high concentrations of n-type impurities are injected and metal films having different thicknesses. Different values are shown several times.

As shown in Table 1, the heat treatment process lowers the resistance value of the amorphous silicon film to a level of 10 ⁴ Ω / □, and makes the distribution of the sheet resistance value in contact with the metal film and the amorphous silicon film almost uniform.

Then, the photosensitive film 50 is formed on the metal film.

The metal layer is wet-etched using the photoresist layer 50 as an etch mask, thereby forming the upper layer of the plurality of gate lines 121 including the gate electrode 124 and the upper layer of the plurality of storage electrode lines 131 including the extension 137. On the other hand, the upper film 120bq of the driving unit is left. In Fig. 12, reference numerals 124aq, 124bq, and 137q denote upper films of the extended portion 137 of the gate electrode 124a, the control electrode 124b, and the sustain electrode line 131, respectively.

At this time, if the etching time is sufficiently long so that the metal film is overetched than the photosensitive film 50, the widths of the gate line 121 and the storage electrode line 131 are narrower than the photosensitive film 50.

Subsequently, the amorphous silicon film is etched using the photosensitive film 50 as a mask to form a preliminary lower layer of the gate line 121 and the storage electrode line 131, while leaving the lower layer 120bp of the driving unit. In FIG. 12, reference numerals 128 and 134 denote preliminary underlayers of the gate electrode 124a and the extension 137, respectively. The preliminary lower layer of the gate line 121 and the storage electrode line 131 is wider than the upper layer.

Next, as shown in FIG. 13, the photosensitive film 50 is removed and N-type impurity ions are implanted into the semiconductor layers 151a and 151b at a high concentration. At this time, the concentration of impurities in the lower region of the portion covered with only the preliminary lower layers 128 and 134 becomes small. Therefore, the N-type high concentration impurity regions 153a, 155a, and 156a, the intrinsic region 154a, and the low concentration impurity region 152 are simultaneously formed.

Subsequently, as shown in FIG. 14, the exposed portions of the preliminary lower layer are removed by dry etching using the upper layers of the gate line 121 and the storage electrode line 131 as a mask to form the gate line 121 and the storage electrode line 131. A lower film is formed. At this time, the width of the upper layer and the lower layer can be varied, and accordingly various inclined structures are made. In FIG. 14, reference numerals 124ap, 124bp, and 137p denote lower layers of the gate electrode 124a, the control electrode 124b, and the extension 137, respectively.

As a result, a plurality of gate lines 121 including the gate electrode 124 and a plurality of storage electrode lines 131 including the extension 137 are formed.

Next, as shown in FIGS. 15 to 17, the photoresist layer 60 is formed, and the upper layer 120bq and the lower layer 120bp of the driving unit are wet and dry etched, respectively, to form the upper layer 124bq of the control electrode 124b. ) And a lower film 124bp.

Subsequently, the P-type impurity ions are implanted at a high concentration to form the P-type source region 153b and the drain region 155b in the semiconductor 151b.

18 through 20, a plurality of contact holes exposing the source and drain regions 153a, 155a, 153b, and 153b by stacking and etching the interlayer insulating layer 160 on the entire surface of the substrate 110, respectively. (163, 165, 166, 167).

Thereafter, impurities on the surfaces of the semiconductors 153a, 155a, 153b, and 155b exposed through the contact holes 163, 165, 166, and 167 and the interlayer insulating layer 160 are removed using plasma.

Next, a plurality of data lines 171 including the source electrode 173a, the plurality of drain electrodes 175a, the input electrode 173b, and the output electrode 175b are stacked and patterned by stacking and patterning a metal film by a method such as sputtering. Form.

Next, as shown in FIGS. 21 to 23, the lower passivation layer 180p made of inorganic material is laminated by chemical vapor deposition, and the upper passivation layer 180q made of photosensitive organic material is applied. Subsequently, the upper passivation layer 180q is irradiated with light through a photo mask (not shown), and then developed to expose the lower passivation layer 180p, and then the exposed portion of the lower passivation layer 180p and the gate below it by a dry etching method. A portion of the insulating layer 140 is removed to form a plurality of contact holes 185 exposing the extension portion 177 of the drain electrode 175a of the pixel portion.

Finally, as shown in FIGS. 3 and 4, the drain electrode 175a is formed on the passivation layer 180 through the contact hole 185 with a transparent conductive material such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like. A plurality of pixel electrodes 191 connected to each other are formed.

In the method of manufacturing a thin film transistor according to the present invention, an amorphous silicon film is disposed between the gate insulating film and the metal film to vary the side slopes, and the substrate is heat-treated to increase the adhesion between the metal film and the amorphous silicon film, thereby reducing contact resistance. Accordingly, the characteristics and the reliability of the thin film transistor may be improved.

In addition, a high concentration of impurity ions are implanted into the semiconductor with a preliminary lower layer of the gate conductor and the storage electrode line to simultaneously form a high concentration impurity region, a channel region, and a low concentration impurity region, thereby simplifying the process.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (26)

Insulation Board, A polycrystalline semiconductor layer formed on the insulating substrate and having a channel region, a source region and a drain region, A first insulating film formed on the polycrystalline semiconductor layer, A gate line formed on the first insulating film, and A storage electrode line formed on the same layer apart from the gate line, The gate line and the storage electrode line may include an amorphous silicon film and a metal film. In claim 1, The amorphous silicon film includes a conductive impurity. In claim 1, The metal film includes aluminum or molybdenum. In claim 1, And the metal film is formed of a single layer. In claim 1, And the polycrystalline semiconductor layer comprises polycrystalline silicon. A semiconductor layer formed on the substrate, A first insulating film formed over the semiconductor layer, A gate line formed on the first insulating film and including a first amorphous silicon film and a metal film; A second insulating film formed on the gate line, and A data line formed on the second insulating film Thin film transistor array panel comprising a. In claim 6, The first amorphous silicon film includes a conductive impurity. In claim 6, The metal film includes aluminum or molybdenum. In claim 6, And the metal film is formed of a single layer. In claim 6, The metal film is on the first amorphous silicon film. In claim 10, A thin film transistor array panel further comprising a second amorphous silicon film formed on the metal film. In claim 6, The metal film is on the thin film transistor array panel below the first amorphous silicon film. In claim 6, The thin film transistor array panel of claim 1, further comprising a storage electrode formed on the first insulating layer, the sustain electrode including an amorphous silicon layer and a metal layer. The method according to any one of claims 6 to 13, The semiconductor layer is a thin film transistor array panel including polycrystalline silicon. The method according to any one of claims 6 to 13, A protective film formed on the data line, and A pixel electrode formed on the passivation layer Thin film transistor display panel further comprising. Forming a semiconductor layer on the substrate, Stacking a first insulating film on the semiconductor layer, Forming a gate electrode including a first amorphous silicon film and a metal film on the first insulating film, Forming a second insulating film on the gate electrode, and Forming a source electrode and a drain electrode on the second insulating layer Method of manufacturing a thin film transistor array panel comprising a. 17. The method of claim 16, The first amorphous silicon film includes a conductive impurity. 17. The method of claim 16, The metal film may include aluminum or molybdenum. 17. The method of claim 16, And the metal film is formed in a single layer. 17. The method of claim 16, The gate electrode forming step, Stacking the first amorphous silicon film; Stacking the metal film on the first amorphous silicon film, and Patterning the metal film and the first amorphous silicon film Method of manufacturing a thin film transistor array panel comprising a. The method of claim 20, The metal film and the first amorphous silicon film patterning step, Etching the metal layer and the first amorphous silicon layer in order to form an upper layer of the gate electrode and a preliminary lower layer having a wider width than the upper layer of the gate electrode; Implanting impurity ions into the semiconductor layer to form a high concentration impurity region, a channel region and a low concentration impurity region, Forming a lower layer of the gate electrode by removing a portion of the preliminary lower layer exposed by the upper layer of the gate electrode using the upper layer of the gate electrode as a mask; Method of manufacturing a thin film transistor array panel comprising a. delete The method of claim 20, The forming of the gate electrode may further include heat treating the metal film and the first amorphous silicon film. The method of claim 23, The heat treatment is a method of manufacturing a thin film transistor array panel performed at 200 ℃ to 300 ℃. The method according to any one of claims 16 to 21, 23 and 24, And the semiconductor layer comprises polycrystalline silicon. The method according to any one of claims 16 to 21, 23 and 24, Forming a passivation layer on the source electrode and the drain electrode; Forming a pixel electrode on the passivation layer Method of manufacturing a thin film transistor array panel further comprising.

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