KR20060028520A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on an insulating substrate and an insulating substrate, and is positioned between a source region and a drain region, a source region and a drain region, and a source region and a channel region, and a region between the drain region and the channel region. At least a portion of the source region and the drain region having a thickness thinner than other portions, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer and overlapping the channel region. A data line includes a gate line, a data line having a source electrode intersecting with the gate line and connected to the source region, and a pixel electrode insulated from the gate line and electrically connected to the drain region.

Thin film transistor, low concentration doping area

Description

Thin film transistor array panel and method for manufacturing the same {Thin film transistor array panel and method for manufacturing the same}

1 is a layout view schematically illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view illustrating a unit pixel structure formed in a pixel unit in a thin film transistor array panel according to an exemplary embodiment of the present invention.

3A, 4A, 5A, 7A, and 8A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5B is a cross-sectional view taken along the line VV ′ of FIG. 5A;

6 is a cross-sectional view at the next step of FIG. 5B,

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ of FIG. 8A;

9 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

10 is a cross-sectional view taken along the line X-X 'of FIG. 9,

11A is a layout view at an intermediate stage of a method of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A;

12A is a layout view at the next step of FIG. 11A,

12B is a cross-sectional view taken along the line XIIb-XIIb ′ of FIG. 12A;

13 is a layout view of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 14 is a cross-sectional view taken along the line XIV-XIV′-XIV ″ of FIG. 13;

15A, 16A, 17A, and 18A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 15B is a cross-sectional view taken along the line XVb-XVb'-XVb "of FIG. 15A,

FIG. 16B is a cross-sectional view taken along the line XVIb-XVIb'-XVIb "of FIG. 16A;

FIG. 17B is a cross-sectional view taken along the line XVIIb-XVIIb′-XVIIb ″ of FIG. 17A, and FIG.

FIG. 18B is a cross-sectional view taken along the line XVIIIb-XVIIIb'-XVIIIb "of FIG. 18A

19 is a layout view of a thin film transistor array panel according to a fourth exemplary embodiment of the present invention.

20 is a cross-sectional view taken along the line XX-XX 'of FIG. 19,

21A, 22A, and 23A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the present invention;

FIG. 21B is a cross-sectional view taken along the line XXIb-XXIb ′ of FIG. 21A;

FIG. 22B is a cross-sectional view taken along the line XXIIb-XXIIb ′ of FIG. 22A;                 

FIG. 23B is a cross-sectional view taken along the line XXIIIb-XXIIIb 'of FIG. 23A;

24 is a layout view of a thin film transistor array panel according to a fifth exemplary embodiment of the present invention.

25 is a cross-sectional view taken along the line XXV-XXV'-XXV "of FIG. 24,

26A and 27A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a fifth exemplary embodiment of the present invention.

FIG. 26B is a cross-sectional view taken along the line XXVIb-XXVIb'-XXVIb "of FIG. 26A;

FIG. 27B is a cross-sectional view taken along the line XXVIIb-XXVIIb'-XXVIIb "of FIG. 27A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

153: source region 154: channel region

155: drain region 171: data line

173 Source electrode 175 Drain electrode

190: pixel electrode

160, 601, 602: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method for manufacturing the same, and more particularly, to a thin film transistor array panel using polycrystalline silicon as a semiconductor layer and a method for manufacturing the same.

A thin film transistor array panel is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a thin film transistor formed by crossing a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transmitting an image signal, disposed in each pixel, and connected to the gate line and the data line; And a pixel electrode connected to the thin film transistor.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode which is a part of the gate line, a source electrode which is a part of the data line, and a drain electrode facing the source electrode around the semiconductor layer. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

In this case, the semiconductor layer may be formed of amorphous silicon and crystalline silicon according to the crystal state of silicon. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used in semiconductor layers of switching elements of display devices that use glass having a low melting point as a substrate.                         

Since the polysilicon thin film transistor using polycrystalline silicon as a semiconductor layer has a much higher driving speed than an amorphous silicon thin film transistor, a driving circuit for driving a pixel together with the thin film transistor in the pixel region can be formed on the substrate together with the thin film transistor. have.

However, polysilicon thin film transistors require a low concentration doped region to prevent punch through, and in order to form such a low concentration doped region, a doping mask is formed to form a low concentration doped region by forming a spacer or the like on the sidewall of the gate electrode. Since it is necessary to use a photo-etching process to form a low concentration doped region, there is a problem that the manufacturing process is complicated.

The present invention provides a thin film transistor array panel and a method of manufacturing the same, which can minimize the doping process of forming a low concentration doped region.

A thin film transistor array panel according to the present invention for achieving the above object is formed on an insulating substrate, an insulating substrate, a channel region, a source region and a channel region and a drain located between the source region and the drain region, the source region and the drain region Has a lightly doped region located between the region and the channel region, and at least a portion of the source region and the drain region has a thickness thinner than the other portions, a semiconductor layer formed on the semiconductor layer, a gate insulating layer formed on the semiconductor layer, and a channel region A gate line having a gate electrode overlapping the gate line, a data line having a source electrode insulated from and crossing the gate line and connected to the source region, and a pixel electrode insulated from the gate line and electrically connected to the drain region.

Here, the first interlayer insulating film formed on the drain region, the first interlayer insulating film formed on the first interlayer insulating film and the drain electrode connected to the drain region through the contact hole formed in the first interlayer insulating film, the second interlayer insulating film formed on the drain electrode The display device may further include a pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode through a contact hole formed in the second interlayer insulating layer.

In addition, the data line is formed of the same material on the same layer as the gate line, and is formed on the data metal piece formed between the gate line at a predetermined distance from the gate line, on the interlayer insulating film covering the gate line, and across the source region and the gate line. It may further include a data connection for electrically connecting.

In this case, the gate insulating film has a first thickness portion, a second thickness portion formed thinner than the first thickness portion, the first thickness portion corresponds to the channel region and the lightly doped region, and the second thickness portion covers the semiconductor layer. It is desirable to have.

In addition, it is preferable that the gate insulating film is composed of the first and second gate insulating films, and the first and second gate insulating films have the same planar pattern.

Further, it is preferable that the first thickness portion includes the first and second gate insulating films, and the second thickness portion includes the first gate insulating film.

The first gate insulating film is preferably made of silicon oxide, and the second gate insulating film is preferably made of silicon nitride.

The first gate insulating film is preferably made of silicon oxide, and the second gate insulating film is preferably made of silicon nitride.

In addition, it is preferable that portions of the source region and the drain region contacting the source electrode and the drain electrode are formed thinner than other portions.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, including forming a semiconductor layer on an insulating substrate, laminating an insulating film and a conductive film on the semiconductor layer, and patterning the conductive film to form a gate line. Forming a gate insulating film having first and second thickness portions by removing the upper portion of the insulating film by a predetermined thickness, and doping the conductive layer with a high concentration of conductive impurity ions into the semiconductor layer using the gate insulating film as a mask. / Forming the drain region together, removing predetermined regions of the gate insulating film corresponding to the source / drain regions and upper portions of the source / drain regions by a predetermined thickness, and forming a first interlayer insulating film to cover the gate lines and the semiconductor layer. And forming a data line having a source electrode connected to the source region on the first interlayer insulating layer. Forming a pixel electrode electrically connected with the drain region on the first interlayer insulating film, wherein the first thickness portion is formed thicker than the second thickness portion, and the gate line overlaps the second thickness portion. The width of the overlapping gate line is smaller than the width of the second thickness portion.

The forming of the pixel electrode may include forming a drain electrode connected to the drain region through the first contact hole on the first interlayer insulating layer and a second interlayer having a second contact hole exposing the drain electrode on the drain electrode. And forming an insulating layer, wherein the pixel electrode is connected to the drain electrode through the second contact hole.

The forming of the data line may include forming a data metal piece between the gate line by a predetermined distance on the same layer as the gate line, and connecting the source electrode and electrically connecting the data metal piece across the gate line. Forming a connection.

In the gate insulating layer, the first thickness portion may correspond to the channel region and the lightly doped region, and the second thickness portion may be formed to cover the semiconductor layer.

In addition, the insulating film may include forming a first insulating film and forming a second insulating film over the first insulating film.

In the forming of the gate insulating film, the first and second thickness portions may be formed by removing the second insulating film.

The first gate insulating film is preferably formed of silicon oxide, and the second gate insulating film is preferably formed of silicon nitride.

Further, the source region and the drain region are preferably formed thinner than other portions in contact with the source electrode and the drain electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.                     

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

1 is a layout view schematically illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 and 2, a blocking film 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and a high concentration of N-type or P-type conductive impurity ions is formed on the blocking film 111. The semiconductor layer 150 including the source region 153 and the drain region 155 and the channel region 154 positioned therebetween is formed.

A low concentration doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 in which the conductive impurity ions are lightly doped.                     

The source region 153 and the drain region 155 of the semiconductor layer 150 are formed thinner than the thickness of the channel region 154 and the lightly doped region 152.

First and second gate insulating layers 141 and 142 are formed on the semiconductor layer 150. The first gate insulating layer 141 is made of silicon oxide, and the second gate insulating layer 142 is made of silicon nitride. The first and second gate insulating layers 141 and 142 have a width corresponding to the channel region 154 and the lightly doped region 152 of the semiconductor layer 150.

A gate line 121 extending in one direction is formed on the substrate 110, and a portion of the gate line 121 extends to overlap the second gate insulating layer 142 corresponding to the channel region 154. A portion of the overlapping gate line 121 is used as the gate electrode 124 of the thin film transistor. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157.

The gate line 121 and the storage electrode line 131 include a conductive film made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy. In addition to the conductive film, other materials, particularly indium tin oxide (ITO) or indium (IZO), may be used. chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and their alloys (eg, molybdenum-tungsten (MoW) alloys) with good physical, chemical and electrical contact properties with zinc oxide). It may have a multilayer film structure including another conductive film. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

Sides of the gate line 121 and the storage electrode line 131 are formed to be tapered, and the tapered shape is formed so that the layers formed thereon can be in close contact with each other.

A first interlayer insulating film 601 made of silicon oxide, silicon nitride, or the like is formed on the gate line 121, the gate electrode 124, the storage electrode 133, and the storage electrode line 131. The first interlayer insulating layer 601 has first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155.

A data line 171 is formed on the interlayer insulating layer 601 to cross the gate line 121 and define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode of the thin film transistor. Used as One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown).

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

The drain electrode 175 and the data line 171 may also be formed of a conductive film such as aluminum (Al) or an aluminum alloy, such as a gate line. In addition to the conductive film, other materials, especially indium tin oxide (ITO), may be used. Or chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and alloys thereof having good physical, chemical and electrical contact properties with indium zinc oxide (IZO). ] It may have a multilayer film structure including another conductive film made of such. An example of such a structure is a chromium / aluminum-neodymium (AlNd) alloy. In the case of the double film, the aluminum-based conductive film is preferably positioned below the other conductive film, and in the case of the triple film, the aluminum-based conductive film is preferably positioned as the intermediate layer.

The second interlayer insulating layer 602 is entirely formed on the first interlayer insulating layer 601 on which the first drain electrode 175 and the data line 171 are formed. The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.

3A, 4A, 5A, 7A, and 8A are layout views at an intermediate stage in the method of manufacturing the TFT panel according to the present invention, and FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 3A, 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A, FIG. 5B is a cross-sectional view taken along the line V-V' of FIG. 5A, FIG. 6 is a cross-sectional view at the next step of FIG. 5B, and FIG. 7B is 7A is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7B, and FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb' of FIG. 8A.

First, as shown in FIGS. 3A and 3B, the blocking film 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. . Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film not doped with impurities is formed to a thickness of 500 kPa or more by a method such as chemical vapor deposition. Preferably it is formed to a thickness of 500 ~ 1,200Å. Then, the amorphous silicon film is crystallized by ELA method, furnace heat treatment method, SLS method, MIC method or the like to form a polycrystalline silicon film.

Thereafter, a semiconductor layer 150 made of polycrystalline silicon is formed by patterning the photolithography process using a photomask.

Next, as shown in FIGS. 4A and 4B, the first and second insulating films 401 and 402 and the conductive film are stacked to cover the semiconductor layer 150. Then, the conductive layer is etched using the photoresist pattern PR as a mask to form the gate line 121 having the gate electrode 124 and the storage electrode line 131 having the storage electrode 133.

The conductive layer and the second insulating layer 402 are formed of a material having a difference in etching selectivity, and the conductive layer is formed of a material that is etched faster than the second insulating layer 402. Thus, the conductive layer is overetched under the photoresist pattern PR during etching, resulting in undercut. do.

Next, as shown in FIGS. 5A and 5B, the second insulating film 402 is continuously removed using the photoresist pattern PR as a mask to form the second gate insulating film 142. After removing the photoresist pattern PR, a source / drain defining the channel region 154 is formed by implanting conductive impurity ions into the semiconductor layer 150 using the gate line 121 and the second gate insulating layer 142 as a mask. Regions 153 and 155 and lightly doped region 152 are formed simultaneously.

The implantation of ions is set to a certain concentration at a certain depth, and then doping is performed. The distribution of ions around a target point shows a normal distribution curve. Therefore, in the embodiment of the present invention, the edge of the normal distribution curve is set to be located in the low concentration doping region 152, and then ion concentration is implanted at high concentration to form the low concentration doping region 152 and the source / drain regions 153 and 155 simultaneously. do. As such, since the lightly doped lightly doped region 152 and the lightly doped source / drain regions 153 and 155 can be simultaneously formed with only one doping, the ion doping process is simplified.

Next, as shown in FIG. 6, the semiconductor layer 150 in which the first gate insulating layer 141 and the lower source / drain regions 153 and 155, which expose the second gate insulating layer 142 as a mask, is positioned. Remove as much as a certain thickness.

This is because the edge of the normal distribution curve is set in the low concentration doping region 152 in the steps of FIGS. 5A and 5B, and the ion is implanted at a high concentration, so in the low concentration doping region 152, the center of the normal distribution curve (high concentration portion) Are positioned on the gate insulating layers 141 and 142. However, in the source / drain regions 153 and 155, the center portion of the normal distribution curve may be formed toward the substrate so that the upper portion of the source / drain regions 153 and 155 of the semiconductor layer is removed by a predetermined thickness.

This is to ensure that the conductive layer formed later is located close to the center of the normal distribution curve in the semiconductor layer, and the thickness to be removed from the source / drain region of the semiconductor layer may be determined according to the position of the center.

Of course, during the heat treatment process for activating the doped impurity ions doped impurity ions are diffused in the source / drain region to have a uniform doping concentration, but the upper part of the source / drain region is removed by a certain thickness.

If the upper conductive layer is in contact with a portion away from the heavily doped semiconductor layer, there is a problem in that the contact resistance is increased and the characteristics of the thin film transistor are deteriorated.

Then, the dopant ions doped in the semiconductor layer 150 are activated by heat treatment. As such, the heat treatment may be performed separately or may be omitted by heat used in subsequent processes.

Next, as shown in FIGS. 7A and 7B, an insulating material is stacked on the entire surface of the substrate 110 including the gate electrode 124 to form a first interlayer insulating layer 601. In this case, the first interlayer insulating layer 601 may be formed of silicon oxide, silicon nitride, or the like.

Subsequently, first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155 are formed in the first interlayer insulating layer 601 by photolithography.

Next, a data conductive layer is formed on the first interlayer insulating layer 601 including the first and second contact holes 161 and 162, and then the data line 171 and the drain having the source electrode 173 by a photolithography process. An electrode 175 is formed.

The data line 171 is connected to the source region 153 through the first contact hole 161, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 162.                     

Next, as shown in FIGS. 8A and 8B, after forming the second interlayer insulating layer 602 on the source electrode 173 and the drain electrode 175, the third contact hole 163 may be etched by a photolithography process. Form.

The second interlayer insulating film 602 has excellent planarization characteristics and is formed of an organic material having photosensitivity, a-Si: C: O, a-Si: formed by plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials such as O: F or silicon nitride, which is an inorganic material.

1 and 2, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the inside of the third contact hole 163. Afterwards, the contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line is patterned. The pixel electrode 190 is connected to the drain electrode 175a of the pixel area through the third contact hole 163.

When the second interlayer insulating layer 602 is formed of a low dielectric constant material of 4.0 or less, the pixel electrode 190 may overlap the data line 171 to improve the aperture ratio of the pixel.

Second Embodiment

FIG. 9 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view taken along the line X-X 'of FIG. 9.

As shown in Figs. 9 and 10, the second embodiment has almost the same interlayer structure as the first embodiment. That is, a semiconductor layer having a blocking layer 111 formed on the transparent insulating substrate 110 and having source / drain regions 153 and 155, a lightly doped region 152, and a channel region 154 formed on the blocking layer 111. 150) is formed.

First and second gate insulating layers 141 and 142 corresponding to the channel region 154 and the lightly doped region 152 of the semiconductor layer 150 are formed, and the first and second gate insulating layers 141 and 142 are formed. The gate line 121 partially overlaps the channel region 154. A first interlayer insulating layer 601 having contact holes 161 and 162 exposing the source / drain regions 153 and 155, respectively, is formed on the gate line 121, and a source is formed on the first interlayer insulating layer 602. The data line 171 and the drain electrode 175 are formed to be connected to the / drain regions 153 and 155, respectively.

A second interlayer insulating layer 602 is formed on the data line 171 and the drain electrode 175, and a pixel connected to the drain electrode 175 through the contact hole 163 is formed on the second interlayer insulating layer 602. An electrode 190 is formed.

However, in the second embodiment, only portions of the upper portions of the source / drain regions 153 and 155 corresponding to the contact holes 161 and 163 are removed. Therefore, the first gate insulating layer 601 is formed to cover the semiconductor layer 150, and only portions corresponding to the contact holes 161 and 163 are removed.

This will be described in detail together with the manufacturing method with reference to FIGS. 11A and 12B and FIGS. 3A to 5B and 10.

FIG. 11A is a layout view of an intermediate stage in a method of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 11A, and FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb ′ of FIG. 12A.

First, as shown in FIGS. 3A to 5B, the blocking film 111 is formed on the transparent insulating substrate 110, and the polycrystalline silicon is formed on the blocking film 111. The source / drain regions 153 and 155 have a low concentration. The semiconductor layer 150 having the doped region 152 and the channel region 154 is formed.

Then, the first and second gate insulating layers 141 and 142 are formed on the semiconductor layer 150, and the gate line 121 having the gate electrode 124 is formed on the second gate insulating layer 142.

The conductive layer and the second insulating layer 402 are formed of a material having a difference in etching selectivity, and the conductive layer is formed of a material that is etched faster than the second insulating layer 402. Thus, the conductive layer is overetched under the photoresist pattern PR during etching, resulting in undercut. do.

Next, as shown in FIGS. 11A and 11B, a first interlayer insulating film 601 covering the gate line 121 is formed. In this case, the first interlayer insulating layer 601 may be formed of silicon oxide, silicon nitride, or the like.

Afterwards, the first interlayer insulating layer 601, the first gate insulating layer 142, and the semiconductor layer 150 are partially removed by the photolithography process to form the contact holes 161 and 162.

Therefore, unlike the first embodiment, in the second embodiment, the first gate insulating layer 142 covers the semiconductor layer 150.                     

Next, as shown in FIGS. 12A and 12B, a data conductive layer is formed on the first interlayer insulating layer 601 including the first and second contact holes 161 and 162, and then the source electrode 173 is formed by a photolithography process. And a data line 171 and a drain electrode 175 are formed.

The data line 171 is connected to the source region 153 through the first contact hole 161, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 162. After forming the second interlayer insulating layer 602 on the source electrode 173 and the drain electrode 175, the third contact hole 163 is formed by etching by a photolithography process.

Next, as shown in FIGS. 9 and 10, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the third contact hole 163. Afterwards, the contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line is patterned. The pixel electrode 190 is connected to the drain electrode 175a of the pixel area through the third contact hole 163.

When the second interlayer insulating layer 602 is formed of a low dielectric constant material of 4.0 or less, the pixel electrode 190 may overlap the data line 171 to improve the aperture ratio of the pixel.

Third Embodiment

FIG. 13 is a layout view of a TFT panel for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 14 is a cross-sectional view taken along the line XIV-XIV′-XIV ″ of FIG. 13.

In Embodiment 3, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are formed at the same time, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 13 and 14, the blocking layer 111 is formed on the transparent insulating substrate 110. A semiconductor layer including a source region 153, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor between the conductive layer and the dopant having a high concentration of conductive impurities on the blocking layer 111. 150 is formed. The conductive dopant is less doped than the source and drain regions 153 and 155 between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 of the semiconductor layer 150. It is.

First and second gate insulating layers 141 and 142 are formed on the semiconductor layer 150. The first and second gate insulating layers 141 and 142 correspond to the lightly doped region 152 and the channel region 154.

A gate line 121 extending in one direction is formed on the blocking layer 111, and a portion of the gate line 121 extends to partially overlap the gate insulating layer 142 corresponding to the channel region 154 so that the gate electrode ( 124). One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157.

The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. In addition, the data metal piece 171a may enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).

The gate line 121 and the data metal piece 171a include a conductive film made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, and in addition to the conductive film, other materials, particularly indium tin oxide (ITO) or indium (IZO) chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and their alloys (eg, molybdenum-tungsten (MoW) alloys) with good physical, chemical and electrical contact properties with zinc oxide). It may have a multilayer film structure including another conductive film. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

An interlayer insulating layer 160 is formed to cover the gate line 121 and the storage electrode line 131. The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 made of ITO or IZO, which is a transparent conductive material, are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 and the storage electrode line 131 in the vertical direction.                     

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121 and the storage electrode line 131. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate line 121 and the data metal piece 171a, respectively.

The contact auxiliary member 82 is not essential to serve to protect adhesion between the end of the data line 171a and the external device and to protect them, and application thereof is optional.

A method of manufacturing the thin film transistor array panel according to the third embodiment of the present invention described above will be described in detail with reference to FIGS. 11 and 12 described above with reference to FIGS. 15A to 18B.

15A, 16A, 17A, and 18A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along the line XVb-XVb ′ of FIG. 15A. 16B is a cross-sectional view taken along the line XVIb-XVIb'-XVIb "in FIG. 16A, FIG. 17B is a cross-sectional view taken along the line XVIIb-XVIIb'-XVIIb" in FIG. 17A, and FIG. 18B is an XVIIIb-XVIIIb in FIG. 18A. Sectional view taken along the line '-XVIIIb'.                     

First, as shown in FIGS. 15A and 15B, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. . Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film not doped with impurities is formed to a thickness of 500 kPa or more by a method such as chemical vapor deposition. Preferably it is formed to a thickness of 500 ~ 1,200Å. Then, the amorphous silicon film is crystallized by an excimer laser anneal (ELA) method, a furnace heat treatment method, a sequential lateral solidification (SLS) method, a metal induced crystallization (MIC) method to form a polycrystalline silicon film.

Thereafter, the polycrystalline silicon film is photo-etched using a photomask to form a semiconductor layer 150 made of polycrystalline silicon.

First, as shown in FIGS. 16A and 16B, the first and second insulating films 401 and 402 and the conductive film are stacked to cover the semiconductor layer 150. Then, the conductive film is etched using the photoresist pattern PR as a mask to form the gate line 121 having the gate electrode 124, the storage electrode line 131 having the storage electrode 133, and the data metal piece 171a.

Sides of the gate line 121, the storage electrode line 131, and the data metal piece 171a are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.                     

Next, as shown in FIGS. 17A and 17B, the second gate insulating layer 142 is formed by successively removing the second insulating layer 402 using the photoresist pattern PR as a mask. After removing the photoresist pattern PR, a source / drain defining the channel region 154 is formed by injecting conductive impurity ions into the semiconductor layer 150 using the gate line 121 and the second gate insulating layer 142 as a mask. Regions 153 and 155 and lightly doped region 152 are formed simultaneously.

Next, upper portions of the source / drain regions 153 and 155 of the semiconductor layer are removed by a predetermined thickness. Then, heat treatment activates the impurity ions doped in the semiconductor layer. As such, the heat treatment may be performed separately or may be omitted by heat used in subsequent processes.

Next, as shown in FIGS. 18A and 18B, an interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.                     

As shown in FIGS. 13 and 14, a conductive film is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. The pixel electrode 190 and the contact auxiliary member 82 are formed.

The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line 121 and the data metal piece 171b to improve the aperture ratio of the pixel region.

Although not described as a separate embodiment, the structure shown in the third embodiment may remove the source region and the drain region at the time of forming the contact hole as in the second embodiment.

[Example 4, Example 5]

In the above-described embodiment, the gate insulating film is formed in double, but the gate insulating film may be formed in a single layer. When the gate insulating film is formed in a single layer, the insulating film forming process time can be saved more than when forming a double layer.

19 is a layout view of a thin film transistor array panel according to a fourth exemplary embodiment of the present invention, and FIG. 20 is a cross-sectional view taken along the line XX-XX ′ of FIG. 19.

As shown in Figs. 19 and 20, most of the interlayer structures are the same as in the first embodiment. However, in the fourth embodiment, the gate insulating layer 140 is formed of a single layer.

That is, a semiconductor layer having a blocking layer 111 formed on the transparent insulating substrate 110 and having source / drain regions 153 and 155, a lightly doped region 152, and a channel region 154 formed on the blocking layer 111. 150) is formed.

The gate insulating layer 140 corresponding to the channel region 154 and the lightly doped region 152 of the semiconductor layer 150 is formed on the semiconductor layer 150, and the channel region 154 and the channel insulating layer 140 are formed on the gate insulating layer 140. Partly overlapping gate lines 121 are formed. A first interlayer insulating layer 601 having contact holes 161 and 162 exposing source / drain regions 153 and 155, respectively, is formed on the gate line 121, and a source / drain layer is formed on the first interlayer insulating layer 601. The data line 171 and the drain electrode 175 are formed to be connected to the drain regions 153 and 155, respectively.

A second interlayer insulating layer 602 is formed on the data line 171 and the drain electrode 175, and a pixel connected to the drain electrode 175 through the contact hole 163 is formed on the second interlayer insulating layer 602. An electrode 190 is formed.

This will be described in detail together with the manufacturing method with reference to FIGS. 21A to 23B and FIGS. 3A to 5B, 19 and 20.

21A, 22A, and 23A are layout views at an intermediate stage in the method of manufacturing the TFT panel according to the present invention, and FIG. 21B is a cross-sectional view taken along the line XXIb-XXIb ′ of FIG. 21A, and FIG. 22B is a view of FIG. 22A. FIG. 23B is a cross-sectional view taken along the line XXIIb-XXIIb 'of FIG. 23B.

First, as shown in FIGS. 3A and 3B, the blocking film 111 and the semiconductor layer 150 are formed on the transparent insulating substrate 110.

Next, as shown in FIGS. 21A and 21B, the gate insulating layer 140 and the conductive layer are stacked to cover the semiconductor layer 150. Then, the conductive layer is etched using the photoresist pattern PR as a mask to form the gate line 121 having the gate electrode 124 and the storage electrode line 131 having the storage electrode 133.

The conductive layer and the gate insulating layer 140 are formed of a material having a difference in etching selectivity, and the conductive layer is formed of a material that is etched faster than the gate insulating layer 140. The conductive layer is over-etched under the photoresist pattern PR during etching, thereby causing undercut.

Subsequently, the upper portion of the gate insulating layer 140 exposed by removing the conductive layer is removed by a predetermined thickness. In this case, only a part of the upper portion of the gate insulating layer 140 may be removed by adjusting the etching time.

Thereafter, after removing the photoresist pattern PR, the N-type conductive impurity ions are implanted at a high concentration to simultaneously form the channel region 154, the source / drain regions 153 and 155, and the lightly doped region 152.

Next, as shown in FIGS. 22A and 22B, after the gate insulating layer 140 formed on the source / drain regions 153 and 155 is removed, the lower source / drain regions 153 and 155 are also removed by a predetermined thickness. . This is to prevent the heavily doped portion from being formed toward the substrate, so that the conductive layer contacting the source / drain regions 153 and 155 and the heavily doped portion do not directly contact and thus increase the contact resistance.

Then, the dopant ions doped in the semiconductor layer 150 are activated by heat treatment. As such, the heat treatment may be performed separately or may be omitted by heat used in subsequent processes.

Thereafter, as shown in FIGS. 23A to 23B, the interlayer insulating layers 601 and 602, the source and drain electrodes 173 and 175 are formed, and a second interlayer insulating layer 602 is formed thereon.

19 and 20, the pixel electrode 190 is formed on the second interlayer insulating film 602.

In addition, as in the second embodiment, the source / drain regions 153 and 155 may be partially removed together with the contact hole (the fifth embodiment). This will be described taking the structure shown in the third embodiment as an example. Naturally, the structure shown in the first embodiment is also possible.

24 is a layout view of a thin film transistor array panel according to a fifth exemplary embodiment of the present invention, and FIG. 25 is a cross-sectional view taken along the line XXV-XXV'-XV 'of FIG. 24.

As shown in Figs. 24 and 25, most of the interlayer structures are the same as in the third embodiment. That is, the semiconductor layer having the blocking layer 111 formed on the transparent insulating substrate 100 and having the channel region 154, the source / drain regions 153 and 155, and the lightly doped region 154 formed on the blocking layer 111 ( 150) is formed. The gate insulating layer 140 is formed on the semiconductor layer 150. A gate line 121, a storage electrode line 131, and a data metal piece 171a are formed on the gate insulating layer 140, and an interlayer insulating layer 160 is formed on these 121, 131, and 171a, and on the interlayer insulating layer. The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed.

However, in the fifth embodiment, the gate insulating layer 140 has first and second thickness portions, and the first thickness portion is formed thicker than the second thickness portion. The first thickness portion corresponds to the channel region 154 and the lightly doped region 152, except for those 154 and 152 being the second thickness portion.

In addition, only portions where the upper portions of the source / drain regions 153 and 155 correspond to the contact holes 161 and 163 are removed. Therefore, the gate insulating layer 140 is formed to cover the semiconductor layer 150, and only portions corresponding to the contact holes 161 and 163 are removed.

A method of manufacturing the thin film transistor array panel according to the fifth embodiment of the present invention described above will be described in detail with reference to FIGS. 15A through 16B, and FIGS. 24 and 25 previously described with reference to FIGS. 26A through 27B.

26A and 27A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a fifth exemplary embodiment of the present invention, and FIG. 26B is a cross-sectional view taken along the line XXVIb-XXVIb'-XXVIb "of FIG. 26A, and FIG. 27B. Is a cross-sectional view taken along the line XXVIIb-XXVIIb'-XXVIIb "in FIG. 27A.

First, as shown in FIGS. 15A to 16B, the blocking film 111 is formed on the transparent insulating substrate 110, and the semiconductor layer 150 is formed on the blocking film 111. Then, the gate insulating layer 140 and the conductive layer covering the semiconductor layer 150 are stacked. Then, the conductive film is etched using the photoresist pattern PR as a mask to form a gate line 121 having the gate electrode 124, a storage electrode line 131 having the storage electrode 133, and a data metal piece 171a.

The conductive layer and the gate insulating layer 140 are formed of a material having a difference in etching selectivity, and the conductive layer is formed of a material that is etched faster than the gate insulating layer 140. The conductive layer is over-etched under the photoresist pattern PR during etching, thereby causing undercut.

Next, as shown in FIGS. 26A and 26B, the upper portion of the lower gate insulating layer 140 is removed by a predetermined thickness using a photoresist pattern PR as a mask to be stepped. In this case, only a part of the upper portion of the gate insulating layer 140 may be removed by adjusting the etching time.

Thereafter, the N-type conductive impurity ions are implanted at a high concentration to simultaneously form the channel region 154, the source / drain regions 153 and 155, and the lightly doped region 152.

Thereafter, as shown in FIGS. 27A and 27B, an interlayer insulating layer 160 is formed of an insulating material to cover the gate line 121, the storage electrode line 131 having the storage electrode 133, and the data metal piece 171a. .

The first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160 by a photolithography process. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

In this case, the first and second contact holes 161 and 162 exposing the source and drain regions 153 and 155 may have a portion of the interlayer insulating layer 160, the gate insulating layer 140, and the source / drain regions 153 and 155. Removed to form.

24 and 25, a conductive film is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b and The pixel electrode 190 and the contact auxiliary member 82 are formed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, doped regions having different concentrations may be formed using a double gate insulating layer in a single doping process. Therefore, the doping process may be minimized in the manufacturing process of the thin film transistor array panel, thereby improving productivity and minimizing the manufacturing cost.

Claims (17)

Insulation board, A source region and a drain region, a channel region located between the source region and a drain region, a source region and a channel region, and a low concentration doping region positioned between the drain region and the channel region, At least a portion of the source region and the drain region is a semiconductor layer having a thickness thinner than other portions, A gate insulating film formed on the semiconductor layer, A gate line formed on the gate insulating layer and having a gate electrode overlapping the channel region; A data line insulated from and intersecting the gate line and having a source electrode connected to the source region; And a pixel electrode insulated from the gate line and electrically connected to the drain region. In claim 1, A first interlayer insulating film formed over the drain region, A drain electrode formed on the first interlayer insulating layer and connected to the drain region through a contact hole formed in the first interlayer insulating layer; A second interlayer insulating film formed on the drain electrode, And a pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode through a contact hole formed in the second interlayer insulating layer. In claim 1, The data line is formed of the same material on the same layer as the gate line and is formed between the gate line and a distance from the gate line; And a data connection part formed on the interlayer insulating layer covering the gate line and electrically connecting the data metal piece across the source region and the gate line. The method according to any one of claims 1 to 3, The gate insulating film has a first thickness portion, a second thickness portion formed thinner than the first thickness portion, And the first thickness portion corresponds to the channel region and the lightly doped region, and the second thickness portion covers the semiconductor layer. The method according to any one of claims 1 to 3, The gate insulating film is made of a first and second gate insulating film, The thin film transistor array panel of which the first and second gate insulating layers have the same planar pattern. In claim 4, The first thickness portion includes first and second insulating films, The second thickness portion may include a first insulating layer. In claim 5, The first insulating film is made of silicon oxide, The second insulating film is a thin film transistor array panel made of silicon nitride. In claim 6, The first insulating film is made of silicon oxide, The second insulating film is a thin film transistor array panel made of silicon nitride. In claim 1, The thin film transistor array panel of which the source region and the drain region are formed to be thinner than other portions in contact with the source electrode and the drain electrode. Forming a semiconductor layer on the insulating substrate, Stacking an insulating film and a conductive film on the semiconductor layer; Patterning the conductive layer to form a gate line; Removing an upper portion of the insulating layer by a predetermined thickness to form a gate insulating layer having first and second thickness portions; Doping the semiconductor layer with a high concentration of conductive impurity ions using the gate insulating layer as a mask to form a low concentration doped region and a source / drain region together; Removing a predetermined region of the gate insulating layer corresponding to the source / drain region and an upper portion of the source / drain region by a predetermined thickness, Forming a first interlayer insulating film to cover the gate line and the semiconductor layer; Forming a data line having a source electrode connected to the source region on the first interlayer insulating layer; Forming a pixel electrode on the first interlayer insulating layer, the pixel electrode being electrically connected to the drain region; The first thickness portion may be formed thicker than the second thickness portion, and the gate line may overlap the second thickness portion, and the width of the overlapping gate line may be smaller than the width of the second thickness portion. Manufacturing method. In claim 10, Forming the pixel electrode, Forming a drain electrode on the first interlayer insulating layer, the drain electrode being connected to the drain region through a first contact hole; Forming a second interlayer insulating film having a second contact hole exposing the drain electrode over the drain electrode, The pixel electrode is formed to be connected to the drain electrode through the second contact hole. In claim 10, Forming the data line, Forming a data metal piece between the gate line and the gate line by the same material on the same layer as the gate line, And forming a data connection part connected to the source electrode and electrically connecting the data metal piece across the gate line. The method according to any one of claims 11 to 13, And forming the first thickness portion in the gate insulating layer so as to correspond to the channel region and the lightly doped region, and wherein the second thickness portion covers the semiconductor layer. In claim 10, The insulating film forming a first insulating film, And forming a second insulating film on the first insulating film. The method of claim 14, The first and second thickness portions are formed by removing the second insulating layer in the forming of the gate insulating layer. The method of claim 14, The first insulating film is formed of silicon oxide, And the second insulating film is formed of silicon nitride. In claim 10, The source region and the drain region may have a portion in contact with the source electrode and the drain electrode thinner than other portions.

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