KR20050054241A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on an insulating substrate, a semiconductor layer having a source region, a channel region and a drain region, a gate insulating layer formed on the semiconductor layer, and formed on the gate insulating layer and overlapping the channel region. A gate line having a gate electrode, a first interlayer insulating film formed on the gate line, a data line having a source electrode formed on the first interlayer insulating film and electrically connected to the source region, and formed on the first interlayer insulating film and electrically connected to the drain region. A second interlayer insulating film formed on the drain electrode, the data line, and the drain electrode connected to the second electrode; a pixel electrode formed on the second interlayer insulating film and connected to the drain electrode; and the semiconductor layer includes a polycrystal containing germanium of a predetermined concentration. It is formed of silicon.

Description

Thin film transistor array panel and manufacturing method thereof

The present invention relates to a thin film transistor array panel, and more particularly, to a polysilicon thin film transistor array panel and a method of manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor array panel includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transferring an image signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like. It is included.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode connected to the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode with respect to the semiconductor layer. The thin film transistor is a switching element that controls an image signal transmitted to a pixel electrode through a data line according to a scan signal transmitted through a gate line. In this case, the thin film transistor formed on the thin film transistor array panel may be formed using polycrystalline silicon or amorphous silicon.

The thin film transistor using polycrystalline silicon has high electron mobility compared to the thin film transistor using amorphous silicon, and thus can be driven at high speed. In addition, the driving circuit for driving the thin film transistor array panel may be formed on the same substrate as the thin film transistor without attaching a separate circuit.

As such, recently, a glass substrate includes a driving circuit for driving a cell array circuit and a thin film transistor liquid crystal display on a polysilicon thin film transistor array panel, and various peripheral circuit elements for generating an image signal and a scan signal input to the driving circuit. It implements a system on glass (SOG) that integrates all of the above.

However, SOG type polysilicon thin film transistor array panels require high uniformity and high electron mobility, that is, high characteristic thin film transistors. Accordingly, in recent years, the width and length of crystals of polycrystalline silicon have been improved by one of several methods for increasing electron mobility of thin film transistors.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a polycrystalline silicon thin film transistor array panel having a thin film transistor having high uniformity and fast electron mobility.

In order to achieve the above object, the present invention provides a thin film transistor array panel and a method of manufacturing the same.

More specifically, an insulating substrate, a semiconductor layer formed on the insulating substrate and having a source region, a channel region and a drain region, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film and overlapping the channel region. A gate line, a data line having a source electrode formed on the first interlayer insulating film and a first interlayer insulating film formed on the gate line, and a drain formed on the first interlayer insulating film and electrically connected to the drain region. A second interlayer insulating film formed on the electrode, the data line, and the drain electrode; a pixel electrode formed on the second interlayer insulating film and connected to the drain electrode; and the semiconductor layer is formed of polycrystalline silicon containing germanium at a predetermined concentration. A thin film transistor array panel is provided.

Here, it is preferable to further include a lightly doped region formed between the drain region and the channel region between the source region and the channel region and doped with a low concentration of the conductive impurities.

In addition, it is preferable to further include a blocking film formed on the entire surface of the insulating substrate and located below the semiconductor layer.

In addition, the semiconductor layer preferably contains 40% or less germanium.

Alternatively, the insulating substrate, the gate electrode formed on the insulating substrate, the gate insulating film formed on the gate electrode, the semiconductor layer formed on the gate insulating film, the source and drain portion ohmic contact formed on the semiconductor layer, the gate insulating film A data line having a source electrode partially overlapping the source resistive contact region, the gate insulating layer being formed on the drain electrode, the data line and the drain electrode facing the source electrode and partially overlapping the drain resistive contact region; And a protective film, wherein the semiconductor layer is provided with a thin film transistor array panel made of polycrystalline silicon containing germanium at a predetermined concentration.

Alternatively, forming a germanium-silicon film on an insulating substrate, heat-treating the germanium-silicon film, and then patterning to form a semiconductor layer, sequentially forming a gate insulating film and a gate conductive film on the semiconductor layer, and a photoresist pattern on the gate conductive film Forming a gate line having a gate electrode on the gate insulating layer by photo-etching the gate conductive layer using the photoresist pattern as a mask, and doping conductive type impurities to a predetermined region of the semiconductor layer so that source, drain and Forming a undoped channel region, forming a first interlayer insulating film covering the gate line and having first and second contact holes, a source connected to the source region through the first contact hole on the first interlayer insulating film Before the drain connected to the drain region through the data line having the electrode and the second contact Forming a pole; forming a second interlayer insulating film covering the data line and the drain electrode and having a third contact hole; forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating film; A method of manufacturing a thin film transistor array panel including the steps is provided.

In addition, the germanium-silicon film on the insulating substrate is preferably formed by depositing a germanium-silicon mixture in which germanium and silicon are mixed by chemical vapor deposition.

In addition, forming the germanium-silicon film on the insulating substrate preferably includes forming a silicon layer on the insulating substrate and doping germanium ions into the silicon layer.

Further, the germanium-silicon film preferably contains 40% or less of germanium in the total composition ratio.

Alternatively, in a thin film transistor array panel divided into a display region and a driving region, a first thin film transistor including a semiconductor layer made of a polycrystalline silicon film is formed in the display region, and the driving region contains germanium having a predetermined concentration. A thin film transistor array panel on which a second thin film transistor including a semiconductor layer made of a polycrystalline silicon film is formed is provided.

The first thin film transistor may include an insulating substrate, a semiconductor layer formed on the insulating substrate, a gate insulating film formed on the semiconductor layer, a gate line formed on the gate insulating film, a first interlayer insulating film formed on the gate line, and a first interlayer. A data line formed on the insulating layer and connected to the semiconductor layer, a second interlayer insulating layer formed on the drain electrode, the data line and the drain electrode formed on the first interlayer insulating layer and connected to the semiconductor layer, and a drain electrode formed on the second interlayer insulating layer. It is preferable to include a pixel electrode connected to the.

The second thin film transistor includes an insulating substrate, a semiconductor layer formed on the insulating substrate, a gate insulating film formed on the semiconductor layer, a gate line formed on the gate insulating film, a first interlayer insulating film formed on the gate line, and a first interlayer. A data line formed on the insulating layer and connected to the semiconductor layer, a second interlayer insulating layer formed on the drain electrode, the data line and the drain electrode formed on the first interlayer insulating layer and connected to the semiconductor layer, and a drain electrode formed on the second interlayer insulating layer. It is preferable to include a pixel electrode connected to the.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic layout view of a thin film transistor array panel.

As shown in FIG. 1, the thin film transistor array panel includes driving circuit units 410 and 510 for controlling the display area A together with the display area A, and an image signal and a scan signal input to the driving circuit. Various peripheral circuit elements (not shown) are formed together.

In the display area A, a display thin film transistor, a gate line connected to the display thin film transistor, a data line, a pixel electrode, and the like are formed. In the driving circuit unit, an N-type, a P-type thin film transistor, a complementary thin film transistor connected to the display area, or a mixture thereof is formed.

Next, the display area A according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. The display thin film transistor of the display area A is described using an N-type thin film transistor as an example.

FIG. 2 is a layout view illustrating one pixel area of a display area of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 3 is a view illustrating a pixel area of the thin film transistor array panel illustrated in FIG. 2 along a line II-II ′. It is sectional drawing cut out.

2 and 3, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and an N-type source region 153a and a drain region are formed on the blocking layer 111. The semiconductor layer 150a including the 155a and the channel region 154a is formed.

The semiconductor layer 150a is mainly made of silicon and contains germanium at a predetermined concentration.

Next, the crystallization of the germanium-containing semiconductor layer 150a will be described in detail with reference to FIGS. 20A to 20C.

20A to 20C are diagrams illustrating a crystal state of a semiconductor layer according to a germanium concentration in a thin film transistor array panel according to an exemplary embodiment of the present invention.

Germanium has high electron mobility due to its characteristics. Accordingly, when germanium is further added to the semiconductor layer 150a made of silicon and the crystallization process is performed, crystals having a wider width and a longer length are formed as shown in FIGS. 18A and 18B as compared with the case where only silicon is crystallized. Form. However, as shown in FIG. 18C, when the content of germanium in the semiconductor layer 150a made of silicon exceeds 40% of the total composition ratio, problems such as a phenomenon in which crystals are broken during the crystallization process may occur. You do not get the decision you want.

Therefore, it is preferable that germanium contains 40% or less of germanium in the total composition ratio of the material constituting the semiconductor layer 150a, as shown in FIGS. 20A and 20B.

The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150a. The gate line 121 is formed to extend in one direction on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154a of the semiconductor layer 150a. A portion of the line 121 is used as the gate electrode 124a of the thin film transistor.

A lightly doped region 152 is formed between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154a.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150a becomes the storage electrode 133, and the semiconductor layer 150a overlapping the storage electrode 133 becomes the storage electrode region 157. In addition, one end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 on which the gate line 121 and the storage electrode line 131 are formed. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153a through the first contact hole 161, and the portion 173a connected to the source region 153a is a source electrode of the thin film transistor. Used. One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown).

The drain electrode 175a is formed on the same layer as the data line 171 and is separated from the source electrode 173a and connected to the drain region 155a through the second contact hole 162.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 165 exposing the drain electrode 173.

The pixel electrode 190 connected to the drain electrode 175a is formed on the second interlayer insulating layer 602 through the third contact hole 165.

Next, the driving units 410 and 510 according to an exemplary embodiment of the present invention will be described using P-type thin film transistors as an example.

4 is a layout view of a driving unit of a thin film transistor array panel according to an exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view of the driving unit of the thin film transistor array panel illustrated in FIG. 4 taken along the line IV-IV ′.

As shown in FIGS. 4 and 5, a blocking layer 111 is formed on the transparent insulating substrate 110, and a semiconductor layer including a source region 153b, a drain region 155b, and a channel region 154b thereon. 150b is formed. At this time, the semiconductor layer 150b is mainly made of silicon, and contains less than 40% of germanium in the total composition ratio constituting the semiconductor layer 150b.

The gate insulating layer 140 is formed on the semiconductor layer 150b, and the gate electrode 124b is formed on the gate insulating layer 140. The gate electrode 124b is connected to a gate line (not shown) for applying a voltage.

A first interlayer insulating layer 601 is formed to cover the gate electrode 124b and have fourth and fifth contact holes 163 and 164 exposing the source region 154b and the drain region 155b.

A source electrode 173b and a drain electrode 175b connected to the source region 154b, the drain region 155b, respectively, are formed on the first interlayer insulating layer 601. The source electrode 173b and the drain electrode 175b are also connected to data lines (not shown) for applying a voltage to them.

A second interlayer insulating layer 602 is formed on the source electrode 173b and the drain electrode 175b to insulate the source electrode 173b and the drain electrode 175b according to the structure of the thin film transistor formed in the pixel region. The second interlayer insulating layer 602 is a layer formed according to the structure of the thin film transistor formed in the pixel region and may be omitted in some cases.

As described above, each semiconductor layer constituting the display thin film transistor of the pixel region and the driving thin film transistor of the driving unit is formed using a silicon film containing 40% or less germanium. Then, in the crystallization process such as ELA, furnace heat treatment, and SLS that crystallize the semiconductor layer, crystals having large width and length of crystals are obtained in terms of crystallography. As a result, the electron mobility of the display thin film transistor and the driving thin film transistor of the driver is increased.

On the other hand, when the mobility of electrons is large, in the case of the display thin film transistor, an off current increases, and thus the image quality of the liquid crystal display device is deteriorated. Therefore, when there is a problem that the reliability of the display thin film transistor is reduced due to the off current, the semiconductor layer constituting the display thin film transistor in the display area is formed of polycrystalline silicon that does not contain germanium, and the thin film of the driving unit Only the semiconductor layer constituting the transistor may contain germanium.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to the accompanying drawings. Hereinafter, one pixel area in the display area A and one P-type thin film transistor in the driving units 410 and 510 will be described as an example. Their connection is not shown.

6A and 6B, 8A and 8B, 10A and 10B, 12A and 12B, 14A and 14B, and 16A and 16B respectively illustrate one embodiment of the present invention shown in FIGS. FIG. 7 is a layout view at an intermediate stage of a method of manufacturing a thin film transistor array panel according to an example, and is arranged in order of a process, and FIG. 7 is a line VII-VII 'and VII'-VII ", respectively. 9 is a cross-sectional view of the thin film transistor array panel of FIGS. 8A and 8B taken along lines IX-IX 'and IX'-IX ", and FIG. 11 is a cross-sectional view of FIGS. 10A and 10B. FIG. 13 is a cross-sectional view of the thin film transistor array panel taken along lines XI-XI ′ and XI′-XI ″, and FIG. 13 illustrates the thin film transistor array panels of FIGS. 12A and 12B as XIII-XIII ′ and XIII′-XIII ″ lines. 15 is a cross-sectional view of the thin film transistor array panel of FIGS. 14A and 14B, along with the XV-XV 'line and XV'-XV. 17 is a cross-sectional view of the thin film transistor array panel of FIGS. 16A and 16B taken along the lines XVII-XVII 'and XVII'-XVII.

First, as shown in FIGS. 6A, 6B, and 7, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO 2) or silicon nitride (SiN x).

Then, a germanium-silicon film (not shown) is formed on the blocking layer 111. Here, the germanium-silicon film is formed by forming a germanium-silicon mixture in which germanium and silicon are mixed by chemical vapor deposition, or by first forming a silicon film on the blocking layer 111 and then doping germanium ions in the silicon layer. In addition, germanium is contained in 40% or less of the total composition ratio of the germanium-silicon film.

After that, the germanium-silicon film is crystallized through laser annealing, furnace annealing, or sequential lateral solidification (SLS), and then patterned by photolithography to pattern the semiconductor layer 150a of the pixel region and the semiconductor of the driving region. Each layer 150b is formed.

8A, 8B, and 9, an insulating material such as silicon nitride or silicon oxide is deposited on the semiconductor layers 150a and 150b to form a gate insulating layer 140.

A gate metal layer 120 is formed by depositing a metal material such as molybdenum tungsten on the gate insulating layer 140, and then a first photoresist layer pattern 51 is formed on the gate metal layer 120. In this case, the first photoresist layer pattern 51 is formed on the entire area corresponding to the upper portion of the pixel area to protect the pixel area, and is formed on a portion of the semiconductor layer 150b of the driving part on the upper part of the driving part to form a gate line in the driving part. Define. Subsequently, the gate metal layer 120 is etched using the first photoresist layer pattern 51 as a mask to form the gate electrode 124b of the driving unit.

The P-type conductive dopant is doped with the gate electrode 124b as a mask to form the P-type source region 153b, the drain region 155b, and the channel region 154b. At this time, the P-type channel region 154b is not doped with impurities to the semiconductor layer 150b of the driving unit under the gate electrode 124b and separates the P-type source region 153b and the drain region 155b.

As shown in FIGS. 10A, 10B, and 11, after the first photoresist layer pattern is removed, the second photoresist layer pattern 52 is formed on the substrate 110 including the gate metal layer 120 and the gate electrode 124b of the driver unit. do. In this case, the second photoresist layer pattern 52 is formed on the entire area corresponding to the upper portion of the driving portion to protect the driving portion, and is formed on a portion of the semiconductor layer 150a of the pixel region on the upper portion of the pixel region to form a gate line and The formation region of a sustain electrode line is defined, respectively.

Subsequently, the gate metal layer 120 is isotropically etched using the second photoresist pattern 52 as a mask to form the gate line 121 having the gate electrode 124a in the pixel region and the storage electrode line 131 having the storage electrode 133. Form. When the storage capacitor is sufficient, the storage electrode line 131 may not be formed.

The N-type impurity ions are heavily doped into the semiconductor layer 150a of the pixel region using the second photoresist pattern 52 as an ion implantation mask to form the N-type source region 153a, the drain region 155a, and the channel region 154a. ). In this case, the channel region 154a is a semiconductor layer 150a disposed under the gate electrode 124a of the pixel region and is not doped with impurities, and separates the N-type source region 153a and the drain region 155a. In addition, the semiconductor layer 150p may be exposed outside the storage electrode line 131 due to a difference in length and width of the semiconductor layer 150b and the storage electrode line 131. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155a.

Subsequently, the second photosensitive film pattern 52 of the pixel area is removed while the second photosensitive film pattern 52 of the driving part is removed, and then the semiconductor layer is formed using the gate electrode 124a and the storage electrode 133 of the pixel area as an ion implantation mask. N-type impurity ions are lightly doped into 150a to form a lightly doped region 152. In this case, the N-type channel region 154a overlaps the gate electrode 124a of the pixel region by a predetermined portion of the semiconductor layer 150a protected by the second photoresist pattern 52, that is, the lightly doped region 152. Is reduced to the part.

12A, 12B, and 13, the first interlayer insulating layer 601 is formed by stacking an insulating material on the entire surface of the substrate 110 including the gate electrode 124a of the pixel region and the gate electrode 124b of the driving unit. Form. In this case, the first interlayer insulating layer 601 is formed of a double layer made of SiO ₂ / SiN. If the SiO ₂ formed in the SiO ₂ / SiN-layer rather than a single layer is improved and the reliability of the thin film transistor than when formed in a SiO ₂ single layer.

Next, the first contact hole 161 and the second contact hole 162 and the P-type source region exposing the N-type source region 153a and the drain region 155a by a photolithography method to the first interlayer insulating layer 601. The third contact hole 163 and the fourth contact hole 164 exposing the 153b and the drain region 155b are formed.

As shown in FIGS. 14A, 14B and 15, a first interlayer including the first contact hole 161, the second contact hole 162, the third contact hole 163, and the fourth contact hole 164 is included. The data conductive layer is formed on the insulating layer 601 and then patterned to form a data line 171a having a source electrode 173a, a drain electrode 175a, a source electrode 173b, and a drain electrode 175b of the driving unit. do. The data line 171a of the pixel region is connected to the N-type source region 153a through the first contact hole 161, and the drain electrode 175a is connected to the N-type drain region 155a through the second contact hole 162. ). In addition, the source electrode 173b of the driving unit is connected to the P-type source region 153b through the third contact hole 163, and the drain electrode 175b is the P-type drain region 155b through the fourth contact hole 164. ).

As shown in FIGS. 16A, 16B, and 17, after forming the second interlayer insulating layer 602 on the source electrodes 173a and 173b and the drain electrodes 175a and 175b, the fifth contact hole is etched by a photolithography process. Form 165.

The indium tin oxide (ITO), the indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the fifth contact hole 165, and then patterned to form the pixel electrode 190. And a contact auxiliary member (not shown) connected to one end of the gate line or the data line. The pixel electrode 190 is connected to the drain electrode 175a of the pixel area through the fifth contact hole 165.

A thin film transistor of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 18 and 19.

18 is a layout view of a pixel area of a thin film transistor array panel according to another exemplary embodiment, and FIG. 19 is a cross-sectional view of the display area of the thin film transistor array panel illustrated in FIG. 18 taken along the line XIX-XIX ′.

As shown in FIGS. 18 and 19, a gate line 121 long in one direction is formed on the insulating substrate 110.

The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. An end portion of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal transmitted from a gate driving circuit (not shown). If the storage capacitor is sufficient, it may not be formed. If the storage capacitor is insufficient, a storage electrode line (not shown) formed in parallel with the gate line 121 may be added.

The gate line 121 and the storage electrode line 131 may be formed of a silver-based metal such as silver (Ag) or a silver alloy having low resistivity, an aluminum-based metal such as aluminum (Al) or an aluminum alloy, and a copper-based copper such as copper or a copper alloy. It includes a conductive film made of metal, and in addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) having good physical, chemical and electrical contact properties with other materials, particularly ITO or IZO. And other conductive films made of alloys thereof (eg, molybdenum-tungsten (MoW) alloys). An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

The side of the gate line 121 is inclined, and the inclination angle is in a range of about 30-80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

The semiconductor layer 154 is formed directly on the gate insulating layer 140 corresponding to the gate electrode 124. The semiconductor layer 150a is mainly made of silicon and contains germanium at a predetermined concentration. As described above with reference to FIGS. 20A to 20C, germanium is 40 in the total composition ratio of the material constituting the semiconductor layer 150a. It is preferable to contain germanium in% or less.

A source ohmic contact 163 and a drain ohmic contact 165 are formed on the semiconductor layer 154. The source and drain ohmic contact regions 163 and 165 are formed at a predetermined distance from the predetermined region of the semiconductor layer 154. The predetermined region is a channel region that forms a channel between the source electrode 173 and the drain electrode 175.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the source and drain resistive contact regions 163 and 165 and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 123. The source electrode 173 partially overlaps the source resistive contact region 163, and the drain electrode 175 partially overlaps the drain resistive contact region 165. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

In order to improve the storage capacitance of the pixel region, a storage conductor 177 overlapping the gate line 121 is formed.

The data line 171 and the drain electrode 175 may also include a conductive film made of a silver metal or an aluminum metal. In addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo) may be used. ) And other conductive films made of alloys thereof. Sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

The data line 171, the drain electrode 175, and the exposed portion of the semiconductor layer 154 are disposed on the data line 171, the drain electrode 175, and the conductive capacitor 177 for the storage capacitor and the exposed portion of the semiconductor 151. Above is a low level of a-Si: C: O, a-Si: O: F, etc. formed by plasma enhanced chemical vapor deposition (PECVD), an organic material having excellent planarization characteristics and photosensitivity. A passivation layer 180 made of a dielectric insulating material or an inorganic material silicon nitride is formed.

The passivation layer 180 is formed with a first contact hole 185 exposing a portion of the drain electrode 175 and a second contact hole 187 exposing a portion of the conductive capacitor conductor 177. In this case, the first and second contact holes 185 and 187 have a gentle profile by forming sidewalls of the first and second contact holes 185 and 187 having an inclined surface having a predetermined inclination angle.

A plurality of pixel electrodes 190 made of a transparent conductor or a reflective metal such as IZO or ITO is formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the first contact hole 185, and is physically and electrically connected to the conductor 177 for the storage capacitor through the second contact hole 187. It is connected.

Meanwhile, in another embodiment of the present invention, only the structure of the display thin film transistor is described. However, thin film transistors such as N-type, P-type thin film transistors, and complementary thin film transistors formed in the driving circuit unit may also be formed in such a structure.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, a thin film transistor having a high uniformity and fast electron mobility can be manufactured by increasing the width and length of the crystal of the semiconductor layer. Therefore, the driving characteristics of the SOG type thin film transistor array panel requiring high electron mobility can be improved.

1 is a schematic layout view of a thin film transistor array panel,

2 is a layout view of a pixel area of a thin film transistor array panel according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of the display area of the TFT panel shown in FIG. 2 taken along the line II-II ';

4 is a layout view of a driving unit of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the driving unit of the thin film transistor array panel illustrated in FIG. 4 taken along the line IV-IV ′.

6A and 6B, 8A and 8B, 10A and 10B, 12A and 12B, 14A and 14B, and 16A and 16B respectively illustrate one embodiment of the present invention shown in FIGS. Arrangement diagram in an intermediate step of the method of manufacturing a thin film transistor array panel according to an example, the drawings are arranged in order of the process,

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIGS. 6A and 6B taken along lines VII-VII ′ and VII′-VII ″;

FIG. 9 is a cross-sectional view of the thin film transistor array panel of FIGS. 8A and 8B taken along lines IX-IX 'and IX'-IX ".

FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIGS. 10A and 10B taken along lines XI-XI ′ and XI′-XI ″.

FIG. 13 is a cross-sectional view of the thin film transistor array panel of FIGS. 12A and 12B taken along lines XIII-XIII 'and XIII'-XIII ",

FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIGS. 14A and 14B taken along lines XV-XV 'and XV'-XV',

FIG. 17 is a cross-sectional view of the thin film transistor array panel of FIGS. 16A and 16B taken along lines XVII-XVII ′ and XVII′-XVII ″;

18 is a layout view of a pixel area of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 19 is a cross-sectional view of the display area of the thin film transistor array panel illustrated in FIG. 18 taken along the line XIX-XIX ′,

20A to 20C are diagrams illustrating a crystal state of a semiconductor layer according to a germanium concentration in a thin film transistor array panel according to an exemplary embodiment of the present invention.

Claims (16)

Insulation board, A semiconductor layer formed on the insulating substrate and having a source region, a channel region, and a drain region; A gate insulating film formed on the semiconductor layer, A gate line formed on the gate insulating layer and having a gate electrode overlapping the channel region; A first interlayer insulating film formed over the gate line, A data line formed on the first interlayer insulating layer and having a source electrode electrically connected to the source region; A drain electrode formed on the first interlayer insulating layer and electrically connected to the drain region; A second interlayer insulating film formed on the data line and the drain electrode, A pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode; And the semiconductor layer is formed of polycrystalline silicon containing germanium at a predetermined concentration. In claim 1, And a lightly doped region formed between the source region and the channel region between the drain region and the channel region, wherein the dopant is lightly doped. In claim 1, The thin film transistor array panel of claim 1, further comprising a blocking layer formed on the entire surface of the insulating substrate and positioned under the semiconductor layer. In claim 1, And the semiconductor layer contains 40% or less germanium. Forming a germanium-silicon film on the insulating substrate, Heat-treating the germanium-silicon film and then patterning to form a semiconductor layer, Sequentially forming a gate insulating film and a gate conductive film on the semiconductor layer; Forming a photoresist pattern on the gate conductive layer; Photo-etching the gate conductive layer using the photoresist pattern as a mask to form a gate line having a gate electrode on the gate insulating layer; Doping a predetermined region of the semiconductor layer to form a source region, a drain region, and a channel region not doped with impurities; Forming a first interlayer insulating film covering the gate line and having first and second contact holes; Forming a data line having a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole on the first interlayer insulating layer; Forming a second interlayer insulating film covering the data line and the drain electrode and having a third contact hole; Forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating layer. In claim 5, And forming a low concentration doped region by doping the semiconductor layer with a conductive impurity. In claim 5, The germanium-silicon film is a method of manufacturing a thin film transistor array panel for depositing a germanium-silicon mixture of germanium and silicon by chemical vapor deposition. In claim 5, Forming a germanium-silicon film on the insulating substrate Forming a silicon layer on the insulating substrate, And doping germanium ions in the silicon layer. In claim 5, 7 or 8, And a germanium-silicon film containing 40% or less of germanium in the total composition ratio. Insulation board, A gate electrode formed on the insulating substrate, A gate insulating film formed on the gate electrode, A semiconductor layer formed on the gate insulating film, Source and drain resistive contact regions formed on the semiconductor layer; A data line formed on the gate insulating layer and having a source electrode partially overlapping with the source portion ohmic contact; A drain electrode formed on the gate insulating layer and facing the source electrode and partially overlapping the drain resistive contact region; A protective film formed on the data line and the drain electrode; And the semiconductor layer is formed of polycrystalline silicon containing germanium at a predetermined concentration. In claim 10, And a lightly doped region formed between the source region and the channel region between the drain region and the channel region, wherein the dopant is lightly doped. In claim 10, The thin film transistor array panel of claim 1, further comprising a blocking layer formed on the entire surface of the insulating substrate and positioned under the semiconductor layer. In claim 10, And the semiconductor layer contains 40% or less germanium. In the thin film transistor array panel divided into a display area and a driving area, A first thin film transistor including a semiconductor layer formed of a polycrystalline silicon film is formed in the display area. And a second thin film transistor including a semiconductor layer made of a polycrystalline silicon film containing germanium at a predetermined concentration in the driving region. The method of claim 14, The first thin film transistor includes an insulating substrate, a semiconductor layer formed on the insulating substrate, a gate insulating film formed on the semiconductor layer, a gate line formed on the gate insulating film, and a first interlayer insulating film formed on the gate line. A data line formed on the first interlayer insulating layer and connected to the semiconductor layer, a drain electrode formed on the first interlayer insulating layer and connected to the semiconductor layer, and a second interlayer insulating layer formed on the data line and the drain electrode; And a pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode. The method of claim 14, The second thin film transistor includes an insulating substrate, a semiconductor layer formed on the insulating substrate, a gate insulating film formed on the semiconductor layer, a gate line formed on the gate insulating film, and a first interlayer insulating film formed on the gate line. A data line formed on the first interlayer insulating layer and connected to the semiconductor layer, a drain electrode formed on the first interlayer insulating layer and connected to the semiconductor layer, and a second interlayer insulating layer formed on the data line and the drain electrode; And a pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode.