KR101107683B1 - METHOD OF FABRICATING poly-Si TFT ARRAY SUBSTRATE - Google Patents

Abstract

The present invention relates to a polysilicon thin film transistor array substrate which improves device characteristics by effectively dissipating heat in the channel layer area by further including a SiC film having a high thermal conductivity as an element deterioration prevention film under the channel layer. An element deterioration prevention film formed, an active layer formed on the element deterioration prevention film and comprising a source / drain region and a channel layer, a gate insulating film formed on the entire surface including the active layer, a gate electrode formed on the gate insulating film, And an interlayer insulating film formed on the entire surface including the gate electrode, and a source / drain electrode contacting the source / drain region on the interlayer insulating film.

Channel Layer, Degradation, SiC

Description

Method for manufacturing polysilicon thin film transistor array substrate {METHOD OF FABRICATING poly-Si TFT ARRAY SUBSTRATE}

1 is a cross-sectional view of a polysilicon thin film transistor according to the prior art.

2 is a cross-sectional view of a polysilicon thin film transistor according to the present invention.

3a to 3f are process cross-sectional views of a polysilicon thin film transistor according to the present invention.

Figure 4 is a cross-sectional view of a polysilicon thin film transistor array substrate according to the present invention.

* Explanation of symbols for the main parts of the drawings

110: glass substrate 111: buffer layer

112 SiC film 113 Active layer

113a: source region 113b: drain region

113c: channel layer 114: gate insulating film

115: gate electrode 116: interlayer insulating film

117a: source electrode 117b: drain electrode

118: protective film 119: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing a polysilicon thin film transistor array substrate which is intended to effectively disperse heat in a portion of a channel layer to improve device characteristics.

(PDP), Electro Luminescent Display (ELD), Vacuum Fluorescent (VFD), and the like have been developed in recent years in response to the demand for display devices. Display) have been studied, and some of them have already been used as display devices in various devices.

Among them, active matrix liquid crystal display devices are widely used as flat panel display devices widely used in notebooks, personal digital assistants, TVs, aviation monitors, etc. due to low voltage driving, full color implementation, light weight and small size.

A general liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel has a predetermined space and is bonded to the color filter array substrate and the thin film transistor array substrate. And a liquid crystal layer injected between the two substrates.

In this case, the thin film transistor array substrate includes a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and each of the gate lines and data. A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing lines, and a plurality of thin film transistors (TFTs) that are switched by signals of the gate lines to transfer signals of the data lines to each pixel electrode. Film Transistor) is provided.

The thin film transistor can be classified into using an active layer made of amorphous silicon (amorphous silicon: a-Si) and an active layer made of polysilicon having a crystalline phase, depending on which silicon is used as the active layer. .

The active layer made of polysilicon has a carrier mobility of 10 to 100 times higher than the active layer made of amorphous silicon, so that a driving circuit can be made on a substrate, which is advantageous as a switching element of a high resolution panel. However, the self-heating effect has a great influence on the characteristics of the device, such as a change in threshold voltage and mobility, because of operating at a higher driving current than an amorphous silicon thin film transistor.

Hereinafter, a polysilicon thin film transistor array substrate according to the prior art will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a polysilicon thin film transistor according to the prior art.

First, a SiO ₂ buffer layer 11 is formed on the entire surface of the insulating substrate 10, and then a polysilicon layer is formed by plasma enhanced d chemical vapor deposition (PECVD) and patterned by photolithography. Form layer 13. In this case, forming a polysilicon layer with a thinner thickness has advantages of increasing on-current, decreasing off-current, and reducing leakage current. .

Subsequently, SiO ₂ , which is an inorganic material, is deposited on the entire surface of the active layer 13 to form a gate insulating layer 14, and a low resistance metal layer is deposited and patterned thereon to form the gate electrode 15 and the gate wiring (not shown). ).

Next, the active layer 13 is doped with a high concentration of n-type impurity ions using the gate electrode 15 as a mask to form source / drain regions 13a and 13b. At this time, the active layer between the source region 13a and the drain region 13b where the impurity ions are not doped by the gate electrode 15 becomes the channel layer 13c.

That is, a dopant gas ion is adsorbed on the surface of the active layer 13 by using a plasma made of a dopant gas containing no active layer deposition gas to terminate the dangling bond of the silicon layer. This is because if the dangling bond is large in the silicon layer, the carrier is subsequently caught by the dangling bond and the mobility is greatly reduced.

Subsequently, SiO ₂ , which is an inorganic material, is deposited on the entire surface including the gate electrode 15 to form an interlayer insulating layer 16, and the gate insulating layer 14 and the interlayer insulating layer 16 are etched to form the source / drain regions. A contact hole through which 13a and 13b is exposed is formed.

Thereafter, a low-resistance metal layer is deposited and patterned on the interlayer insulating layer 16 to intersect the source / drain electrodes 17a and 17b and the gate line, which are in contact with the source / drain regions 13a and 13b, respectively. (Not shown).

This completes the polysilicon thin film transistor composed of the active layer 13, the gate electrode 15, and the source / drain electrodes 17a and 17b using polysilicon.

Subsequently, although not shown, a protective film is formed by depositing SiNx, an inorganic material, on the entire surface including the source / drain electrodes 17a and 17b by chemical vapor deposition, and contacting the drain electrode 17b thereon. By forming the polysilicon thin film transistor array substrate may be completed.

However, the polysilicon thin film transistor array substrate according to the prior art has the following problems.

In the case of fabricating a polysilicon thin film transistor on a glass substrate, if stress is applied under high power conditions (a condition of applying high bias to both the gate and the drain), the temperature of the channel layer 13c rises and ionization collision causes Electron-hole pairs are created. In addition, the wider the channel width (the interface length between the source / drain region and the channel layer), the greater the amount of current, thereby causing a serious thermal reliability problem of the polysilicon thin film transistor.

Furthermore, the thermal conductivity of the glass substrate 10 positioned around the channel layer is 0.002 W / mK and the thermal conductivity of the interlayer insulating film 16 (SiOx) is 0.14 W / mK, which is susceptible to heat. Difficulties in dissipating heat exacerbate degradation.

The present invention has been proposed to solve the above problems, and by using a SiC film having a high thermal conductivity as an element deterioration prevention film further under the channel layer, the poly to improve the characteristics of the device by effectively dissipating heat in the channel layer region It is an object of the present invention to provide a method for manufacturing a silicon thin film transistor array substrate.

The polysilicon thin film transistor array substrate of the present invention for achieving the above object is an element deterioration prevention film formed on the substrate, an active layer formed on the element deterioration prevention film and composed of a source / drain region and a channel layer, A gate insulating film formed on the entire surface including the active layer, a gate electrode formed on the gate insulating film, an interlayer insulating film formed on the entire surface including the gate electrode, and a source / drain electrode contacting the source / drain region on the interlayer insulating film; Characterized in that it comprises a.

As described above, the present invention is to improve the reliability by effectively reducing the heat generated in the channel layer by depositing a high thermal conductivity element degradation prevention film under the channel layer. Hereinafter, the SiC film will be described as an example of an element deterioration prevention film having high thermal conductivity.

Hereinafter, a polysilicon thin film transistor array substrate according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a polysilicon thin film transistor according to the present invention, Figures 3a to 3e is a cross-sectional view of the process of the polysilicon thin film transistor according to the present invention, Figure 4 is a cross-sectional view of a polysilicon thin film transistor array substrate according to the present invention.

As shown in FIG. 2, the polysilicon thin film transistor according to the present invention has a buffer layer 111 and a SiC film 112 formed on the entire surface including the glass substrate 110 and a predetermined pattern on the SiC film 112. An active layer 113 patterned to include source / drain regions 113a and 113b and a channel layer 113c, a gate insulating layer 114 formed on the entire surface including the active layer 113, and the channel layer ( 113c) the gate electrode 115 formed on the gate insulating film 114 on the upper portion, the interlayer insulating film 116 formed on the entire surface including the gate electrode 115, and the source intersecting the interlayer insulating film 116. And a source / drain electrode 117a and 117b connected to the drain region, wherein the thermal conductivity is deteriorated by a hot carrier at the junction between the channel layer 113c and the drain region 113b. Heat is dispersed to the high SiC film 112 to prevent deterioration of the device. do.

Specifically, referring to the process, as illustrated in FIG. 3A, silicon oxide (SiO 2) is deposited on the glass substrate 110 by chemical vapor deposition to form a buffer layer 111. The buffer layer 111 prevents mobile charge from penetrating into the active layer 113 from the glass substrate 110 in a subsequent process, and removes the glass substrate 110 from the high temperature in the crystallization process of the amorphous silicon layer. It protects and serves to improve the contact characteristics of the semiconductor layer with respect to the glass substrate 110.

Next, an inorganic insulating film made of SiC is formed on the buffer layer 111 by a PECVD method using SiF ₄ and C ₂ H ₄ as a source gas and Ar as a carrier gas. Since the SiC film 112 has a thermal conductivity of 42 W / Km and is 300 times higher than that of an inorganic insulating material such as SiOx, the SiC film 112 easily dissipates heat generated at the junction between the channel layer 113c and the drain region 113b. Can be. That is, the SiC film 112 according to the present invention serves to prevent the self-heating effect of the device.

Next, as shown in FIG. 3B, the polysilicon layer 113 is formed on the entire surface of the substrate on which the SiC film 112 is formed by chemical vapor deposition.

In this case, the polysilicon layer may be formed by directly depositing polysilicon or by depositing amorphous silicon and then crystallizing it into polycrystal.

Subsequently, the photoresist 120 having a photosensitive characteristic is coated on the polysilicon layer 113, exposed and developed, and the developed photoresist 120 is used as a mask, as shown in FIG. 3C. The polysilicon layer 113 is patterned. Hereinafter, the polysilicon layer 113 is called an active layer.

Thereafter, after the remaining photoresist 120 is completely stripped, as shown in FIG. 3D, an inorganic material SiOx or SiNx is deposited on the entire surface including the active layer 113 to form a gate insulating layer 114. In order to prevent signal delay thereon, a low resistive metal layer having low specific resistance, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), Tantalum (Ta), molybdenum-tungsten (MoW), and the like are deposited and wet-etched with HF, BOE, NH ₄ F, or a mixed solution thereof to form the gate electrode 115.

The gate electrode 115 is formed to overlap a predetermined portion of the semiconductor layer 113, and the active layer overlapping the gate electrode 115 becomes a channel layer.                     

Subsequently, a high concentration of n-type or p-type impurity ions are doped into the active layer 113 using the gate electrode 115 as a mask to form source / drain regions 113a and 113b. As described above, the semiconductor layer between the source region 113a and the drain region 113b where the gate electrode 115a is not doped and the impurity ions are not doped becomes the channel layer 113c.

Next, as shown in FIG. 3E, SiOx or SiNx, which is an inorganic material, is deposited on the entire surface including the gate electrode 115 to form an interlayer insulating layer 116.

The gate insulating layer 114 and the interlayer insulating layer 116 are etched to expose the source / drain regions 113a and 113b to form a contact hole, and a low resistance metal layer is formed thereon, for example, copper (Cu) or aluminum. (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW) and the like, and deposited by HF, BOE, NH ₄ F or their By wet etching with a mixed solution, source / drain electrodes 117a and 117b contacting the source / drain regions 113a and 113b, respectively, are formed.

Thus, the polysilicon is formed of a top-gate polysilicon made of a laminated film of the active layer 113, the gate insulating film 114, the gate electrode 115, the interlayer insulating film 116, and the source / drain electrodes 117a and 117b. The thin film transistor is completed, and deterioration of the device is prevented by the SiC film under the channel layer of the active layer.

Meanwhile, the polysilicon thin film transistor is also applicable to a TFT array substrate of a liquid crystal display device, and further includes a gate line formed simultaneously with the gate electrode and a data line formed simultaneously with the source / drain electrode. In this case, the polysilicon thin film transistors are formed to cross each other at a crossing point of the gate line and the data line defining pixels.

Here, the drain electrode 117b is connected to the pixel electrode 119 as shown in FIG. 4, and the pixel electrode 119 is formed to have a size occupying most of an area of the pixel. The protective layer 118 may be deposited between the thin film transistor and the pixel electrode 119 by depositing an inorganic material, SiNx, SiO _2, by chemical vapor deposition, or by applying an organic material, benzocyclobutene (BCB), or an acrylic resin. To form more.

As described above, a polysilicon thin film transistor array substrate in which device deterioration is prevented by the SiC film located under the channel layer is completed.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

That is, in the detailed description of the present invention, the embodiment has been described with reference to a liquid crystal display device having a polysilicon thin film transistor. However, the present invention is not limited thereto and may be applied to a semiconductor device, a display device, and the like.

The method of manufacturing a polysilicon thin film transistor array substrate according to the present invention as described above has the following effects.

That is, a SiC film having a high thermal conductivity is further provided below the channel layer to disperse heat generated at the junction surface of the channel layer and the drain region to the SiC film, thereby effectively preventing deterioration of the channel layer portion. Therefore, it is possible to manufacture a device including a highly reliable polysilicon thin film transistor.

Claims (6)

Forming an element deterioration prevention film made of SiC material on a substrate by PECVD using SiF ₄ and C ₂ H ₄ as a source gas and Ar as a carrier gas; Forming an active layer including a source / drain region and a channel layer on the device deterioration prevention film; Depositing a gate insulating film of SiOx or SiNx on the entire surface including the active layer; Forming a gate electrode on the gate insulating film; Forming an interlayer insulating film on the entire surface including the gate electrode; Forming a source / drain electrode on the interlayer insulating layer to contact the source / drain region; Forming a buffer layer on an entire surface between the substrate and the device degradation prevention film; Forming a gate wiring simultaneously with the gate electrode; Forming a data line simultaneously with the source / drain electrodes; Forming a protective film on the entire surface including the source / drain electrodes; Forming a pixel electrode penetrating the passivation layer and contacting the drain electrode; The active layer is formed of a polysilicon layer; The polysilicon thin film transistor comprising the active layer, the gate electrode, and the source / drain electrode is formed at an intersection point of the gate line and the data line. delete delete delete delete delete

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