KR101266448B1 - Thin film transistor and display substrate including the same and manufacturing method thereof - Google Patents

Abstract

The present invention provides a low cost polysilicon thin film transistor using a conductive etch stopper without an additional mask and a photolithography process, a display substrate including the same, and a method of manufacturing the same.

To this end, the present invention is a gate electrode, an active layer formed of polysilicon overlapping the gate electrode and the insulating film between, an ohmic contact layer formed of polysilicon doped with an impurity doped exposing a channel region on the active layer, A thin film transistor comprising: a drain electrode and a source electrode formed on the ohmic contact layer, and an etch stopper layer formed between the active layer and the ohmic contact layer in the same manner as the ohmic contact layer. And it provides a preparation method thereof.

Description

A thin film transistor, a display substrate including the same, and a method of manufacturing the same {THIN FILM TRANSISTOR AND DISPLAY SUBSTRATE INCLUDING THE SAME AND MANUFACTURING METHOD THEREOF}

1 is a plan view illustrating a thin film transistor substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a cross section taken along line II ′ of the thin film transistor substrate illustrated in FIG. 1.

3A is a cross-sectional view illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

3B is a cross-sectional view illustrating a second mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

3C are cross-sectional views illustrating a third mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

3D is a cross-sectional view for describing a fourth mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

3E is a cross-sectional view illustrating a fifth mask process in the method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention.

<Brief Description of Drawings>

10: substrate 20: gate electrode

21: gate line 30: gate insulating film

40: active layer 41: ohmic contact layer

50: etch stopper layer 61: source electrode

62: drain electrode 63: data line

70: shield 71: contact hole

80: pixel electrode 100: thin film transistor

141: amorphous silicon layer 142: amorphous carbon layer

143: impurity doped amorphous silicon layer

160: data metal layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor, a display substrate having the same, and a method of manufacturing the same, wherein the etch stopper layer of the polysilicon thin film transistor is formed of conductive carbon to reduce a mask process.

In general, polysilicon thin film transistors are used to independently drive each pixel in a display device such as a liquid crystal display or an organic light emitting diode. A display substrate having such a thin film transistor forms thin film transistors and signal lines through a separate mask process. The polysilicon thin film transistor is mainly formed of a top gate structure for the crystallization process, but a plurality of photolithography processes are added as compared to the amorphous silicon thin film transistor process, and the contact resistance between the source electrode and the drain electrode and the active layer is reduced. To form an ohmic contact layer. In this case, an ion doping process and an activation process are added to form an ohmic contact layer, thereby increasing the process cost.

In order to solve the above problems, the manufacturing process of the amorphous silicon thin film transistor is used as it is, and after depositing the active layer and the ohmic contact layer continuously, the amorphous silicon is crystallized with polysilicon to form a source / drain electrode. In this case, the channel region of the thin film transistor formed between the source / drain electrodes has a problem that the active layer is overetched when the source / drain electrodes are formed.

Accordingly, an aspect of the present invention is to provide a low-cost polysilicon thin film transistor, a display substrate including the same, and a manufacturing method thereof using a conductive etch stopper without an additional mask and photolithography process.

In order to solve the above technical problem, the present invention is formed of a gate electrode, an active layer formed of polysilicon overlapping with the gate electrode and the insulating film therebetween, and formed of impurity doped polysilicon exposing a channel region on the active layer A thin film transistor including an ohmic contact layer, a drain electrode and a source electrode respectively formed on the ohmic contact layer, and an etch stopper layer formed between the active layer and the ohmic contact layer in the same manner as the ohmic contact layer To provide.

In addition, a display substrate including the thin film transistor is provided.

And the etch stopper layer contains carbon.

Here, the etch stopper layer is characterized in that any one selected from methane, ethane, propane, butane, acetylene, propene and n-butane.

In addition, the etch stopper layer further includes doped with nitrogen to increase electrical conductivity.

In order to solve the above technical problem, the present invention is to form a gate pattern including a gate line and a gate electrode on the substrate, a gate insulating film, an amorphous silicon layer, an etch stopper layer on the substrate and the gate pattern And continuously forming and patterning an impurity doped amorphous silicon layer to form an active layer, an ohmic contact layer and an etch stopper layer, crystallizing the active layer, the ohmic contact layer and an etch stopper layer by a solid phase crystallization method, A data pattern including a drain electrode, a source electrode, and a data line is formed on a substrate on which the active layer, the ohmic contact layer, and the etch stopper layer are formed, and the ohmic contact layer and the etch stopper exposed by the drain electrode and the source electrode. Removing the layer, and the drain electrode on the substrate on which the data pattern is formed. It provides an exposure method of manufacturing a display substrate comprising the steps of: forming a pixel electrode connected with the drain electrode through the contact hole and a step on the protective film to form a protective film having a contact hole for.

The forming of the data pattern and removing the ohmic contact layer and the etch stopper layer exposed to the drain electrode and the source electrode may include forming a data metal layer on the substrate on which the active layer, the etch stopper layer, and the ohmic contact layer are formed. Forming a photoresist pattern on the data metal layer, etching the data metal layer using the mask pattern to form the data pattern, and an ohmic contact layer exposed by the drain electrode and the source electrode. Etching and removing the etch stopper layer exposed by the etched ohmic contact layer.

At this time, the etch stopper layer contains carbon.

And the carbon is formed of any one selected from methane, ethane, propane, butane, acetylene, propene and n-butane.

In addition, the carbon layer is characterized in that the doped with nitrogen.

Other technical problems and features of the present invention in addition to the above technical problem will become apparent through the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3E.

1 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along a line II ′ of the thin film transistor substrate illustrated in FIG. 1.

1 and 2, the illustrated thin film transistor substrate includes a thin film transistor connected to a gate line 21 and a data line 63 formed to cross each other, and a gate line 21 and a data line 63, respectively. 100 and a pixel electrode 80 connected to the thin film transistor 100.

In detail, the thin film transistor 100 keeps the pixel signal supplied to the data line 63 charged in the pixel electrode 80 in response to the scan signal supplied to the gate line 21. To this end, the thin film transistor 100 faces the pixel electrode 80 while facing the gate electrode 20 connected to the gate line 21, the source electrode 61 connected to the data line 63, and the source electrode 61. An active layer 40 formed of polysilicon by forming a channel between the source electrode 61 and the drain electrode 62 by overlapping the gate electrode 20 with the drain electrode 62 and the gate insulating layer 30 interposed therebetween. ) Ohmic contact layer 41 and ohmic contact layer 41 formed on the active layer 40 except for the channel region and made of impurity doped polysilicon for ohmic contact with the source electrode 61 and the drain electrode 62. An etch stopper layer 50 formed between the contact layers 41 and patterned in the same manner as the ohmic contact layer 41 is provided.

As shown in FIG. 1, the gate line 21 supplies a gate on / off voltage from the gate driving circuit to the gate electrode 20 connected to the gate line 21. The gate line 21 may be directly connected to an output terminal of a gate driving circuit integrated with a thin film transistor substrate, or may be connected to metal pads connected with a driving chip mounted with an integrated gate driving circuit.

The gate electrode 20 protrudes from the gate line 21 and turns on and off the thin film transistor through a gate on / off voltage supplied from the gate line 21.

In this case, a storage line (not shown) for supplying a storage voltage in parallel with the gate line 21 may be further formed. The storage line is formed of the same metal as the gate line 21, and overlaps the pixel electrode 80 to form a storage capacitor.

As the gate pattern including the gate line 21 and the gate electrode 20, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or the like is used. The gate pattern is formed of a single layer or a double layer or more in consideration of properties such as signal attenuation due to the internal resistance of the above-described metals or bonding characteristics with other metals.

An insulating material such as SiNx or SiOx is formed on the substrate 10 and the gate pattern to insulate the gate pattern including the gate line 21 and the gate electrode 20.

An active layer 40 is formed on the gate insulating layer 30 to form a channel of the thin film transistor, and an ohmic contact layer to reduce the contact resistance between the source electrode 61 and the drain electrode 62 on the active layer 40. 41 is formed. At this time, the etch stopper layer 50 is formed to prevent the active layer 40 from being overetched in the data pattern process.

The active layer 40 is crystallized to polysilicon by solid phase crystallization (hereinafter referred to as "SPC") method by depositing and patterning amorphous silicon. In addition, the ohmic contact layer 41 is deposited and patterned using amorphous silicon doped with either n-type impurities or p-type impurities, and then simultaneously crystallized with polysilicon during the amorphous silicon crystallization process of the active layer 40. do. Accordingly, the active layer 40 and the ohmic contact layer 41 may improve electron mobility in the inside, thereby further improving the characteristics of the thin film transistor 100.

The etch stopper layer 50 is formed between the active layer 40 and the ohmic contact layer 41 and is formed in the same pattern as the ohmic contact layer 41. When the etch stopper layer 50 is used as a material such as a metal, metal deposition is performed by a sputtering method, thereby lifting the metal thin film using a break break between the active layer 40 and the ohmic contact layer 41. In addition to being a source of contamination or surface contamination, a separate etching process for patterning the etch stopper layer 50 is required, so that the non-metal material is used to simultaneously form the active layer 40 and the ohmic contact layer 41. For this purpose, the etch stopper layer 50 preferably uses carbon. In particular, the etch stopper layer 50 uses any one selected from methane, ethane, propane, butane, acetylene, propene, and n-butane having electrical conductivity. In addition, the etch stopper layer 50 may use impurity doped carbon, for example, nitrogen doped carbon, to increase electrical conductivity during deposition. When the amorphous carbon is used as the etch stopper layer 50, the active layer 40, the etch stopper layer 50, and the ohmic contact layer 41 may be patterned in one mask process, thereby reducing the mask process time and the process time. You can save money.

Here, the active layer 40, the etch stopper layer 50, and the ohmic contact layer 41 may be polysilicon, polycarbon, and impurity doped amorphous silicon, amorphous carbon, and impurity doped amorphous silicon using the SPC method. Crystallize in polysilicon.

The source electrode 61 and the drain electrode 62 are formed to face each other on the ohmic contact layer 41.

The data line 63 is formed to intersect the gate line 21 with the gate insulating layer 30 interposed therebetween, and supplies a data signal to the source electrode 61 from the data driving circuit.

The passivation layer 70 is formed on the gate insulating layer 30 on which the data pattern and the data pattern including the source electrode 61, the drain electrode 62, and the data line 63 are formed. An inorganic insulating material or an organic insulating material is used as the passivation layer 70, and may be formed of a dual structure of an inorganic insulating material and an organic insulating material. In the passivation layer 70, a portion of the passivation layer 70 is removed to connect the pixel electrode 80 and the drain electrode 62 to form a contact hole 71 exposing the drain electrode 62.

The pixel electrode 80 is connected to the drain electrode 62 exposed through the contact hole 71. The pixel electrode 80 charges a pixel signal supplied from the thin film transistor 100 to generate a potential difference with a common electrode formed on a color filter substrate (not shown). Due to the potential difference, the liquid crystals positioned on the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy, and the amount of light incident through the pixel electrode 80 from the light source (not shown) is controlled to be transmitted to the color filter substrate. The pixel electrode 80 is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, for each mask process.

3A is a cross-sectional view illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, at least one metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or the like may be sputtered onto a substrate 10 such as glass or plastic. The gate metal layer including the furnace gate line 21 and the gate electrode 20 is deposited in a single layer or multiple layers. The gate metal layer is patterned through a photolithography process using a first mask to form a gate pattern. In this case, the gate metal layer is preferably formed of a double layer or a triple layer or more in order to improve signal transmission characteristics. Next, when the gate metal layer is formed, a photoresist (“PR”) is applied to the entire surface of the gate metal layer, and a gate pattern is formed through a photolithography process using a first mask. The gate pattern is etched through an etchant after exposing and patterning PR using a mask on a substrate on which PR is applied.

3B is a cross-sectional view illustrating a second mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 3B, a gate insulating film 30 such as an organic insulating material or an inorganic insulating material, such as plasma enhanced chemical vapor deposition (PECVD), or the like is formed on the substrate 10 having the gate pattern formed thereon. A layer 141, an amorphous carbon layer 142, and an impurity doped amorphous silicon layer 143 are successively deposited. Here, the amorphous carbon layer 142 is deposited using at least one of methane, ethane, propane, butane, acetylene, propene and n-butane. In this case, the amorphous carbon layer 142 may be doped with nitrogen to increase the electrical conductivity during deposition. Then, a channel pattern is formed by patterning the amorphous silicon layer 141, the amorphous carbon layer 142, and the impurity doped amorphous silicon layer 143 through a photolithography process using a second mask. At this time, the amorphous carbon 142 is ashed by an oxygen plasma method.

Next, the amorphous silicon layer 141 and the impurity doped amorphous silicon layer 143 are crystallized through an SPC method. That is, the amorphous silicon layer 141 and the impurity doped amorphous silicon layer 143 are crystallized into polysilicon through an annealing process in which the amorphous silicon layer 143 is heated to a temperature of 600 to 700 ° C. or lower and then cooled. At the same time, the amorphous carbon layer 142 is also crystallized from polycarbon.

3C is a cross-sectional view illustrating a third mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 3C, metal, such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or the like may be sputtered on the ohmic contact layer 41 and the gate insulating layer 30. At least one of the data metal layers 160 is deposited in a single layer or multiple layers. The data metal layer 160 is patterned through a photolithography process using a third mask to form a data pattern including the source electrode 61, the drain electrode, and the data line 63. In this case, the data metal layer 160 may be formed in two or more layers in order to improve signal transmission characteristics.

Specifically, when the data metal layer 160 is formed, PR is applied to the entire surface of the data metal layer 160 and a data pattern is formed through a photolithography process using a third mask. In other words, the data pattern is formed by exposing and patterning the PR using the third mask on the substrate 10 to which the PR is applied, and then etching the data metal layer 160 through the etching solution. Here, the ohmic contact layer 41 is etched after the source electrode 61 and the drain electrode 62 are etched. This prevents over-etching of the active layer 40 during etching of the ohmic contact layer 41 and also prevents damage due to exposure to plasma. Next, after the ohmic contact layer 41 is etched, the etch stopper layer 50 on the active layer 40 is removed together using an oxygen plasma method in an ashing process of removing PR.

3D is a cross-sectional view illustrating a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 3D, a protective film 70, such as an inorganic insulating material or an organic insulating material, is deposited on the substrate 10 on which the data pattern is formed by using a method such as PECVD. Next, the contact hole 71 is formed through a photolithography process using a fourth mask to expose the drain electrode 62. As the protective film 70, an inorganic insulating material such as the gate insulating film 30 formed by a method such as CVD or PECVD is used. Alternatively, an organic insulating material such as an acryl-based organic compound, BCB, or PFCB, which is formed by a method such as spin coating or spinless coating, may be used. Or it may be formed by the dual structure of an inorganic insulating material and an organic insulating material.

Referring to FIG. 3E, a transparent conductive metal layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the substrate 10 on which the passivation layer 70 is formed by using a method such as sputtering, and the fifth mask is formed. The pixel electrode 80 is formed by patterning the transparent conductive metal layer through the photolithography process. The pixel electrode 80 is connected to the drain electrode 62 via the contact hole 71 formed in the passivation layer 70.

Meanwhile, although the thin film transistor, the display substrate, and the manufacturing method thereof according to the embodiment of the present invention have been described with reference to a liquid crystal display device, for example, the scope of rights thereof is not limited to the liquid crystal display device. The same applies to all display devices having transistors.

According to the present invention, the thin film transistor, the display substrate including the same, and a method of manufacturing the same may improve the characteristics of the polysilicon thin film transistor by preventing the active layer from being overetched using a conductive etch stopper.

Here, since the conductive etch stopper manufactures the thin film transistor without using an additional mask process using carbon, it is possible to form a low cost polysilicon thin film transistor.

In the detailed description of the present invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the spirit and scope of the art.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A gate electrode; An active layer formed of polysilicon by overlapping the gate electrode with an insulating layer therebetween; An ohmic contact layer formed of impurity doped polysilicon exposing a channel region on the active layer; A drain electrode and a source electrode respectively formed on the ohmic contact layer; And an etch stopper layer formed between the active layer and the ohmic contact layer in the same pattern as the ohmic contact layer. The method of claim 1, And the etch stopper layer comprises carbon. The method of claim 2, The etch stopper layer is any one selected from methane, ethane, propane, butane, acetylene, propene and n-butane. The method of claim 3, wherein The carbon is a thin film transistor, characterized in that further comprises nitrogen doped. A substrate; A gate electrode formed on the substrate; An active layer formed of polysilicon by overlapping the gate electrode with an insulating layer therebetween; An ohmic contact layer formed of impurity doped polysilicon exposing a channel region on the active layer; A drain electrode and a source electrode respectively formed on the ohmic contact layer; A thin film transistor including an etch stopper layer formed between the active layer and the ohmic contact layer in the same manner as the ohmic contact layer; A gate line connected to the gate electrode; A data line crossing the gate line with the gate insulating layer interposed therebetween and connected to the source electrode; And a pixel electrode connected to the drain electrode via a contact hole exposing the drain electrode with a passivation layer interposed therebetween. 6. The method of claim 5, And the etch stopper layer comprises carbon. The method of claim 6, The carbon is a display substrate, characterized in that any one selected from methane, ethane, propane, butane, acetylene, propene and n-butane. The method of claim 7, wherein The carbon may further include doped with nitrogen. Forming a gate pattern comprising a gate line and a gate electrode on the substrate; Continuously forming and patterning a gate insulating layer, an amorphous silicon layer, an etch stopper layer, and an impurity doped amorphous silicon layer on the substrate and the gate pattern to form an active layer, an ohmic contact layer, and an etch stopper layer; Crystallizing the active layer, the ohmic contact layer and the etch stopper layer by a solid phase crystallization method; A data pattern including a drain electrode, a source electrode, and a data line is formed on a substrate on which the active layer, the ohmic contact layer, and the etch stopper layer are formed, and the ohmic contact layer and the etch stopper layer exposed by the drain electrode and the source electrode. Removing the; Forming a protective film having a contact hole exposing the drain electrode on the substrate on which the data pattern is formed; And And forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer. The method of claim 9, Forming the data pattern and removing the ohmic contact layer and the etch stopper layer exposed to the drain electrode and the source electrode may include Forming a data metal layer on the substrate on which the active layer, the etch stopper layer and the ohmic contact layer are formed; Forming a photoresist pattern on the data metal layer; Etching the data metal layer using a mask pattern to form the data pattern; Etching the ohmic contact layer exposed by the drain electrode and the source electrode; And removing the etch stopper layer exposed by the etched ohmic contact layer. The method of claim 9, And said etch stopper layer comprises carbon. The method of claim 11, Wherein the carbon is any one selected from methane, ethane, propane, butane, acetylene, propene and n-butane. 13. The method of claim 12, The carbon is a method of manufacturing a display substrate, characterized in that doped with nitrogen.

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