KR20020074701A - Liquid crystal display device and fabricating method thereof - Google Patents
Liquid crystal display device and fabricating method thereof Download PDFInfo
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- KR20020074701A KR20020074701A KR1020010014650A KR20010014650A KR20020074701A KR 20020074701 A KR20020074701 A KR 20020074701A KR 1020010014650 A KR1020010014650 A KR 1020010014650A KR 20010014650 A KR20010014650 A KR 20010014650A KR 20020074701 A KR20020074701 A KR 20020074701A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
Description
본 발명은 액정표시장치 및 그 제조방법에 관한 것으로, 특히, 3층 구조의 버스라인에서 최하층금속의 과식각을 방지하는 액정표시장치 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device and a method for manufacturing the same that prevent over-etching of the lowest metal in a three-layer bus line.
액티브 매트릭스 구동방식의 액정표시장치는 스위칭소자로서 박막트랜지스터를 이용하여 자연스로운 동화상을 표시하고 있다. 이러한 액정표시장치는 브라운관에 비하여 소형화가 가능하며, 퍼스널 컴퓨터와 노트북 컴퓨터는 물론, 복사기 등의 사무자동화기기, 휴대전화기나 호출기 등의 휴대기기까지 광범위하게 이용되고 있다.A liquid crystal display device of an active matrix driving method displays a natural moving image using a thin film transistor as a switching element. Such liquid crystal displays can be miniaturized compared to CRTs, and are widely used not only for personal computers and notebook computers, but also for office automation equipment such as copying machines, portable devices such as cell phones and pagers.
액정표시장치는 박막트랜지스터(Thin Film Transistor : 이하 "TFT"라 함)로 이루어진 스위칭소자와 기판 사이에 주입되어 입사되는 빛을 투과하거나 반사하는 액정을 제어하는 화소(Pixel)전극을 기본단위로 하는 화소가 종횡으로 배열된 구조를 가진다.The liquid crystal display device is based on a pixel electrode that controls a liquid crystal that transmits or reflects light incident and injected between a switching element formed of a thin film transistor (hereinafter referred to as a TFT) and a substrate. The pixel has a structure arranged vertically and horizontally.
액정표시장치에서 스위칭소자인 TFT와 이에 연결된 화소전극으로 구성된 N×M(여기서, N 및 M은 자연수)개의 단위 화소가 하부기판 상에 매트릭스(Matric) 상태로 배열되고, 이 TFT 게이트전극들과 소스전극들에 신호를 전달하는 N개의 게이트라인과 M개의 데이터라인이 교차되어 형성된다.In a liquid crystal display device, N × M unit pixels composed of a TFT, which is a switching element, and a pixel electrode connected thereto are arranged in a matrix state on a lower substrate. N gate lines and M data lines that transmit signals to the source electrodes are formed to cross each other.
도 1은 액정표시장치의 TFT 기판에 대한 평면도이다.1 is a plan view of a TFT substrate of a liquid crystal display device.
도 2는 도 1에 도시된 액정표시장치를 선 "A-A'"를 따라 절단한 단면도이다.FIG. 2 is a cross-sectional view of the liquid crystal display shown in FIG. 1 taken along line "A-A '".
도 1 및 도 2를 참조하면, 액정표시장치는 게이트라인(11)과 데이터라인(14)의 교차부에 형성되어진 TFT(T)와, TFT에 접속된 화소전극을 포함하는 하판과, 도시되지 않은 칼라필터 등이 형성된 도시되지 않은 상판과, 상하판 사이에 주입된 도시되지 않은 액정으로 구성된다.1 and 2, the liquid crystal display device is not shown, and a lower plate including a TFT (T) formed at the intersection of the gate line 11 and the data line 14, and a pixel electrode connected to the TFT; And an unshown liquid crystal injected between the top and bottom plates, on which an uncolored filter and the like are formed.
TFT(T)는 게이트라인(11)에서 연장된 게이트전극(3)과, 데이터라인(11)에서 연장된 소스전극(5)과, 화소전극(23)과 접촉홀(19b)에 의해 접속된 드레인전극(7)과, 소스전극(5)과 드레인전극(7)에 접속된 반도체층(15,17)을 구성으로 한다. 게이트라인(11)과 데이터라인(13) 각각의 일측단에는 구동 IC(Integrated Circuit)와 접속되는 게이트패드부(GP)와 데이터패드부(DP) 각각이 형성된다.The TFT T is connected by the gate electrode 3 extending from the gate line 11, the source electrode 5 extending from the data line 11, the pixel electrode 23, and the contact hole 19b. The drain electrode 7 and the semiconductor layers 15 and 17 connected to the source electrode 5 and the drain electrode 7 are constituted. At one end of each of the gate line 11 and the data line 13, a gate pad part GP and a data pad part DP connected to a driving IC are formed.
게이트라인(11) 및 게이트전극(3)과 게이트패드(25)는 동일한 금속재질이 사용되며, 통상 알루미늄(Al)과 몰리브덴(Mo)이 순차적으로 적층된 구조를 가지고 있다. 데이터라인(13)은 신호전달 특성이 양호하도록 저항값을 줄이기 위하여 몰리브덴(Mo) 금속으로 이루어진다.The gate line 11, the gate electrode 3, and the gate pad 25 are made of the same metal material, and generally have a structure in which aluminum (Al) and molybdenum (Mo) are sequentially stacked. The data line 13 is made of molybdenum (Mo) metal in order to reduce the resistance value so that the signal transmission characteristic is good.
도 3a 내지 도 3e는 도 1에 도시된 액정표시장치의 제조방법을 선 "A-A'"을따라 절단하여 단계적으로 나타내는 단면도이다.3A through 3E are cross-sectional views illustrating a method of manufacturing the liquid crystal display shown in FIG. 1 by cutting along a line "A-A '".
도 3a를 참조하면, 기판(1) 상에 스퍼터링(sputtering)등의 방법으로 알루미늄(Al) 또는 구리(Cu)/몰리브덴(Mo) 등을 순차적으로 증착하여 금속박막을 형성한다. 그리고, 금속박막을 습식방법을 포함하는 포토리쏘그래피방법으로 패터닝하여 기판(1)상에 게이트전극(3), 게이트라인(11) 및 게이트패드(25)를 형성한다.Referring to FIG. 3A, aluminum (Al) or copper (Cu) / molybdenum (Mo) or the like is sequentially deposited on the substrate 1 by a method such as sputtering to form a metal thin film. The metal thin film is patterned by a photolithography method including a wet method to form a gate electrode 3, a gate line 11, and a gate pad 25 on the substrate 1.
도 3b를 참조하면, 기판(1) 상에 게이트패드(25) 및 게이트전극(3)을 덮도록 게이트절연막(9), 활성층(15) 및 오믹접촉층(17)이 PECVD(Plasma Enhanced Chemical Vapor Deposition)로 순차적으로 형성된다.Referring to FIG. 3B, the gate insulating layer 9, the active layer 15, and the ohmic contact layer 17 are covered with PECVD (Plasma Enhanced Chemical Vapor) to cover the gate pad 25 and the gate electrode 3 on the substrate 1. Deposition) is formed sequentially.
게이트절연막(9)은 질화실리콘(SiNx) 또는 산화실리콘(SiOx)으로 절연물질을 증착하여 형성된다. 활성층(15)은 불순물이 도핑되지 않은 비정질실리콘으로 형성된다. 또한, 오믹접촉층(17)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘으로 형성된다.The gate insulating film 9 is formed by depositing an insulating material with silicon nitride (SiNx) or silicon oxide (SiOx). The active layer 15 is formed of amorphous silicon which is not doped with impurities. In addition, the ohmic contact layer 17 is formed of amorphous silicon doped with N-type or P-type impurities at a high concentration.
오믹접촉층(17) 및 활성층(15)을 식각을 포함하는 포토리쏘그래피방법으로 게이트절연막(9)이 노출되도록 패터닝한다.The ohmic contact layer 17 and the active layer 15 are patterned to expose the gate insulating layer 9 by a photolithography method including etching.
도 3c를 참조하면, 게이트절연막(9) 상에 크롬(Cr), 몰리브덴(Mo)등의 금속층이 오믹접촉층(17)을 덮도록 CVD방법 또는 스퍼터링(sputtering)방법으로 증착된다. 증착된 금속(Cr, Mo)은 오믹접촉층(17)과 오믹접촉을 이룬다.Referring to FIG. 3C, a metal layer such as chromium (Cr) or molybdenum (Mo) is deposited on the gate insulating film 9 by a CVD method or a sputtering method to cover the ohmic contact layer 17. The deposited metals Cr and Mo make ohmic contact with the ohmic contact layer 17.
그리고, 금속층(Cr, Mo)을 게이트절연막(9)이 노출되도록 포토리쏘그래피방법으로 패터닝하여 데이터라인(13), 데이터패드(27), 소스 및 드레인전극(5,7)이 형성된다.Then, the metal layers Cr and Mo are patterned by a photolithography method so that the gate insulating film 9 is exposed to form the data lines 13, the data pads 27, the source and drain electrodes 5 and 7.
소스 및 드레인전극(5,7) 패터닝시 사이의 게이트전극(3)과 대응하는 부분의 오믹접촉층(17)도 패터닝되도록 하여 활성층(15)을 노출시킨다. 활성층(15)의 소스 및 드레인전극(5,7)사이의 게이트전극(3)과 대응하는 부분은 채널이 된다.The ohmic contact layer 17 of the portion corresponding to the gate electrode 3 between the source and drain electrodes 5 and 7 is also patterned to expose the active layer 15. The portion of the active layer 15 corresponding to the gate electrode 3 between the source and drain electrodes 5, 7 becomes a channel.
도 3d를 참조하면, 게이트절연층(9) 상에 게이트패드(25), 데이터패드(27), 소스 및 드레인전극(5,7)을 덮도록 질화실리콘 또는 산화실리콘 등의 무기절연물질 또는 아크릴계(acryl)유기화합물, 테프론(Teflon), BCB(benzocyclobutene), 사이토프 (cytop)또는 PFCB(perfluorocyclobutane)등의 유전상수가 작은 유기절연물을 증착하여 보호층(21)이 형성된다.Referring to FIG. 3D, an inorganic insulating material such as silicon nitride or silicon oxide or an acrylic type is formed to cover the gate pad 25, the data pad 27, the source and drain electrodes 5 and 7 on the gate insulating layer 9. The protective layer 21 is formed by depositing an organic insulator having a low dielectric constant such as an (acryl) organic compound, Teflon, benzocyclobutene (BCB), cytotope (cytop), or perfluorocyclobutane (PFCB).
보호층(21)을 포토리쏘그래피방법으로 패터닝하여 드레인전극(7), 게이트패드(25) 및 데이터패드(27)를 노출시키는 제 1 내지 제 3접촉홀(19a 내지 19c)이 형성된다.The protective layer 21 is patterned by photolithography to form first to third contact holes 19a to 19c exposing the drain electrode 7, the gate pad 25, and the data pad 27.
도 3e를 참조하면, 보호층(21) 상에 투명전도성물질인 인듐-틴-옥사이드(Indium-Tin-Oxide : 이하 "ITO"라 함), 인듐-징크-옥사이드(Indium-Zinc-Oxide) 또는 인듐-틴-징크-옥사이드(Indium-Tin-Zinc-Oxide) 을 증착한 후 패터닝하여 보호층(21)상의 TFT와 대응되는 부분을 제외한 부분에 화소전극(23) 및 보호전극(29)이 형성된다.Referring to FIG. 3E, indium-tin-oxide (hereinafter referred to as “ITO”), indium-zinc-oxide, or transparent conductive material on the protective layer 21 or Indium-Tin-Zinc-Oxide is deposited and patterned to form the pixel electrode 23 and the protective electrode 29 at portions other than those corresponding to the TFTs on the protective layer 21. do.
화소전극(23)은 제2 접촉홀(19b)을 통해 드레인전극(7)과 접촉되며, 보호전극(29)은 제1 접촉홀(19a)을 통해 게이트패드(25)와 접촉되며, 제3 접촉홀(19c)을 통해 데이터패드(27)와 전기적으로 접촉된다.The pixel electrode 23 contacts the drain electrode 7 through the second contact hole 19b, and the protective electrode 29 contacts the gate pad 25 through the first contact hole 19a. Electrical contact with the data pad 27 is made through the contact hole 19c.
이와 같이, 종래에 소스/드레인전극으로 Cr, MO등의 단층막을 주로 사용하였다. 그러나, 액정표시장치가 고정세로 되어갈수록 TFT의 소스/드레인전극은 제1 금속층(6a)/제2 금속층(6b)/제3층 금속(6c)층의 3층 구조로 형성된다. 제1 및 제3 금속층(6a,6c)은 주로 몰리브덴(Mo)으로 형성되며, 제2 금속층(6b)은 알루미늄(Al) 또는 알루미늄 합금으로 형성된다.As described above, conventional single layer films such as Cr and MO are mainly used as source / drain electrodes. However, as the liquid crystal display device becomes more high definition, the source / drain electrodes of the TFT are formed in a three-layer structure of the first metal layer 6a / second metal layer 6b / third layer metal 6c layer. The first and third metal layers 6a and 6c are mainly formed of molybdenum (Mo), and the second metal layer 6b is formed of aluminum (Al) or an aluminum alloy.
그러나, 도 4에 도시된 바와 같이 3층 구조의 금속층 패터닝시 습식식각방식을 사용하면 에천트내에서 제1 및 제3 금속층(6a,6c)과 제2 금속층(6b)의 전극준위차이(electrode potential)로 제1 및 제3 금속층(6a,6c)이 제2 금속층(6b)보다 이온화하는 경향이 크므로 제1 및 제3 금속층(6a,6c)은 제2 금속층(6b)에 의해 산화되고, 제2 금속층(6b)은 제1 및 제3 금속층(6a,6c)에 의해 환원된다.However, as shown in FIG. 4, when wet etching is used for patterning a metal layer having a three-layer structure, an electrode potential difference between the first and third metal layers 6a and 6c and the second metal layer 6b in the etchant is used. ), Since the first and third metal layers 6a and 6c have a greater tendency to ionize than the second metal layer 6b, the first and third metal layers 6a and 6c are oxidized by the second metal layer 6b, The second metal layer 6b is reduced by the first and third metal layers 6a and 6c.
이로 인해 제1 내지 제3 금속층(6a 내지 6c)은 제2 금속층보다 언더컷(undercut)이 되어 그 다음에 보호층을 증착하면 반도체층과 반응성이 좋은 제2 금속층(6b)이 내려앉아 접촉이 발생하므로 누설전류의 상승 등 TFT특성저하 및 불량이 발생하는 단점이 있다.As a result, the first to third metal layers 6a to 6c are undercut than the second metal layer, and when the protective layer is deposited, the second metal layer 6b, which is highly reactive with the semiconductor layer, is settled to generate contact. Therefore, there is a disadvantage that TFT characteristics decrease and defects occur such as an increase in leakage current.
따라서, 본 발명의 목적은 3층 구조의 버스라인에서 최하층의 금속의 과식각을 방지할 수 있는 액정표시장치 및 그 제조방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same that can prevent overetching of the metal of the lowest layer in a bus line having a three-layer structure.
도 1은 종래의 액정표시장치를 나타내는 평면도.1 is a plan view showing a conventional liquid crystal display device.
도 2는 도 1에 도시된 액정표시장치를 선 "A-A'"를 따라 절취한 액정표시장치를 나타내는 단면도.FIG. 2 is a cross-sectional view of a liquid crystal display device taken along the line "A-A '" of the liquid crystal display device shown in FIG.
도 3a 내지 도 3e는 도 2에 도시된 액정표시장치의 제조방법을 단계적으로 나타내는 단면도.3A to 3E are cross-sectional views illustrating a method of manufacturing the liquid crystal display shown in FIG. 2 in stages.
도 4는 종래의 3층 구조의 버스라인의 과식각을 나타내는 단면도.4 is a cross-sectional view showing the overetching of a conventional three-layer bus line.
도 5는 본 발명의 실시 예에 따른 액정표시장치를 나타내는 단면도.5 is a cross-sectional view of an LCD device according to an exemplary embodiment of the present invention.
도 6a 내지 도 6e는 도 5에 도시된 액정표시장치의 제조방법을 단계적으로 설명하는 단면도.6A to 6E are cross-sectional views illustrating a method of manufacturing the liquid crystal display shown in FIG. 5 in stages.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1,31 : 기판3,33: 게이트전극1,31 substrate 3,33 gate electrode
5,35 : 소스전극7,37: 드레인전극5,35 source electrode 7,37 drain electrode
9,39 : 게이트절연막11,41 : 게이트라인9,39 gate insulating film 11,41 gate line
13,43 : 데이터라인15,45 : 활성층13,43 data line 15,45 active layer
17,47 : 오믹접촉층19, 49 : 접촉홀17,47: ohmic contact layer 19, 49: contact hole
21,51 : 보호층23,53 : 화소전극21,51: protective layer 23,53: pixel electrode
25,55 : 게이트패드27,57 : 데이터패드25, 55: gate pad 27, 57: data pad
상기 목적들을 달성하기 위하여, 본 발명에 따른 액정표시장치는 액정셀들이매트릭스형태로 배열된 액정표시장치에 있어서, 데이터신호가 공급되는 데이터라인과, 스캔신호가 공급되는 게이트라인과, 액정셀을 구동하기 위한 화소전극과, 상기 스캔신호에 응답하여 상기 데이터신호를 상기 화소전극으로 절환하기 위한 박막트랜지스터와, 상기 박막트랜지스터의 반도체층상에 동일패턴으로 형성되는 제1 배리어금속층을 구비하고, 상기 데이터라인, 소스 및 드레인전극은 주금속층과 제2 배리어금속층으로 구성되는 것을 특징으로 한다.In order to achieve the above object, the liquid crystal display device according to the present invention is a liquid crystal display device in which the liquid crystal cells are arranged in a matrix form, comprising: a data line supplied with a data signal, a gate line supplied with a scan signal, and a liquid crystal cell; A pixel electrode for driving, a thin film transistor for switching the data signal to the pixel electrode in response to the scan signal, and a first barrier metal layer formed in the same pattern on the semiconductor layer of the thin film transistor; The line, source, and drain electrodes are composed of a main metal layer and a second barrier metal layer.
상기 목적을 달성하기 위하여, 본 발명에 따른 액정표시장치의 제조방법은 기판 상에 게이트라인, 박막트랜지스터의 게이트전극을 형성하는 단계와, 상기 기판 상에 게이트절연막을 전면 도포하는 단계와, 상기 게이트절연막 상에 반도체층 및 제1 배리어금속층을 동일 패턴으로 형성하는 단계와, 상기 게이트절연막 상에 주금속층 및 제2 배리어금속층의 2층 구조로 이루어진 데이터라인, 소스 및 드레인전극을 형성하는 단계와, 상기 게이트전극과 소스전극 및 드레인전극을 가지는 박막트랜지스터를 덮도록 상기 게이트절연막 상에 보호층을 전면 형성하는 단계와, 상기 드레인전극에 접속되도록 전극물질을 상기 보호층상에 전면 증착한 후에 이를 패터닝하여 화소전극을 형성하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a liquid crystal display device according to the present invention includes the steps of forming a gate line, a gate electrode of a thin film transistor on a substrate, applying a gate insulating film on the substrate, and the gate Forming a semiconductor layer and a first barrier metal layer on the insulating film in the same pattern, forming a data line, a source and a drain electrode having a two-layer structure of a main metal layer and a second barrier metal layer on the gate insulating film; Forming a protective layer over the gate insulating layer to cover the thin film transistor having the gate electrode, the source electrode and the drain electrode, depositing an electrode material on the protective layer to be connected to the drain electrode, and then patterning the protective layer. Forming a pixel electrode.
상기 목적 외에 본 발명의 다른 목적 및 특징들은 첨부한 설명 예들에 대한 설명을 통하여 명백하게 드러나게 될 것이다.Other objects and features of the present invention in addition to the above object will become apparent from the description of the accompanying examples.
이하, 도 5 내지 도 6e를 참조하여 본 발명의 바람직한 실시 예에 대하여 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 6E.
도 5는 본 발명의 실시 예에 따른 액정표시장치의 TFT의 기판에 대한 단면도이다.5 is a cross-sectional view of a substrate of a TFT of a liquid crystal display according to an exemplary embodiment of the present invention.
도 5를 참조하면, TFT(T)는 게이트라인(41)에서 연장된 게이트전극(33)과, 데이터라인(41)에서 연장된 소스전극(35)과, 화소전극(53)과 접촉홀(49b)에 의해 접속된 드레인전극(37)과, 소스전극(35)과 드레인전극(37)에 접속된 반도체층(45,47)을 구성으로 한다. 게이트라인(41)과 데이터라인(43) 각각의 일측단에는 구동 IC(Integrated Circuit)와 접속되는 게이트패드부(GP)와 데이터패드부(DP) 각각이 형성된다.Referring to FIG. 5, the TFT T includes a gate electrode 33 extending from the gate line 41, a source electrode 35 extending from the data line 41, a pixel electrode 53, and a contact hole ( The drain electrode 37 connected by 49b) and the semiconductor layers 45 and 47 connected to the source electrode 35 and the drain electrode 37 are comprised. At one end of each of the gate line 41 and the data line 43, a gate pad portion GP and a data pad portion DP connected to a driving IC are formed.
게이트라인(41) 및 게이트전극(33)과 게이트패드(55)는 동일한 금속재질이 사용되며, 통상 알루미늄(Al)과 몰리브덴(Mo)이 순차적으로 적층된 구조를 가지고 있다. 데이터패드(57), 데이터라인(44), 소스 및 드레인전극(35,37)은 알루미늄(Al), 알루미늄 합금/몰리브덴(Mo), 크롬(Cr), 텅스텐(W), 티탄(Ti) 등의 2층의 구조로 형성된다.The gate line 41, the gate electrode 33, and the gate pad 55 are made of the same metal material, and generally have a structure in which aluminum (Al) and molybdenum (Mo) are sequentially stacked. The data pad 57, the data line 44, and the source and drain electrodes 35 and 37 may be formed of aluminum (Al), aluminum alloy / molybdenum (Mo), chromium (Cr), tungsten (W), titanium (Ti), or the like. It is formed into a two-layer structure.
도 6a 내지 도 6e는 도 5에 도시된 액정표시장치의 제조방법을 나타내는 단면도이다.6A through 6E are cross-sectional views illustrating a method of manufacturing the LCD shown in FIG. 5.
도 6a를 참조하면, 기판(31) 상에 스퍼터링(sputtering)등의 방법으로 알루미늄(Al) 또는 구리(Cu)/몰리브덴(Mo) 등을 순차적으로 증착하여 2층 구조의 금속박막을 형성한다. 그리고, 금속박막을 습식방법을 포함하는 포토리쏘그래피방법으로 패터닝하여 기판(31)상에 게이트라인(41), 게이트전극(33)과 게이트패드(55)가 형성된다.Referring to FIG. 6A, aluminum (Al), copper (Cu), molybdenum (Mo), or the like is sequentially deposited on the substrate 31 by a method such as sputtering to form a metal thin film having a two-layer structure. The metal thin film is patterned by a photolithography method including a wet method to form a gate line 41, a gate electrode 33, and a gate pad 55 on the substrate 31.
도 6b를 참조하면, 게이트절연막(39), 활성층(45), 오믹접촉층(47) 및 제1배리어금속층(59a)이 순차적으로 적층된다. 게이트절연막(39), 활성층(45), 오믹접촉층(47) 및 제1 배리어금속층(59a)은 PECVD방법을 이용해 적층되거나 또는, 게이트절연막(39), 활성층(45), 오믹접촉층(47)은 PECVD방법을 증착되고, 제1 배리어금속층(59a)은 스퍼터링방법으로 증착된다.Referring to FIG. 6B, the gate insulating layer 39, the active layer 45, the ohmic contact layer 47, and the first barrier metal layer 59a are sequentially stacked. The gate insulating film 39, the active layer 45, the ohmic contact layer 47, and the first barrier metal layer 59a are laminated using a PECVD method, or the gate insulating film 39, the active layer 45, and the ohmic contact layer 47 are formed. ) Is deposited by the PECVD method, and the first barrier metal layer 59a is deposited by the sputtering method.
게이트절연막(39)은 질화실리콘 또는 산화실리콘 등의 절연물질을 게이트전극을 덮도록 전면 증착하여 형성된다. 활성층(45)은 불순물이 도핑되지 않은 비정질실리콘 또는 다결정실리콘으로 형성된다. 오믹접촉층(47)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘 또는 다결정실리콘으로 형성된다. 제1 배리어금속층(59a)은 몰리브덴(Mo), 크롬(Cr), 텅스텐(W), 티탄(Ti)등으로 형성된다.The gate insulating film 39 is formed by entirely depositing an insulating material such as silicon nitride or silicon oxide to cover the gate electrode. The active layer 45 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. The ohmic contact layer 47 is formed of amorphous silicon or polycrystalline silicon doped with N-type or P-type impurities at a high concentration. The first barrier metal layer 59a is formed of molybdenum (Mo), chromium (Cr), tungsten (W), titanium (Ti), or the like.
채널부의 제1 배리어금속층(59a)을 습식식각 후 활성층(45)/오믹접촉층(47)을 건식식각하거나, 활성층(45)/오믹접촉층(47)/제1 배리어금속층(59a)의 3층이 모두 건식식각되거나, 3층이 모두 습식식각으로 형성하여 게이트절연막(39)이 노출되도록 패터닝한다.After wet etching the first barrier metal layer 59a of the channel portion, the active layer 45 / ohmic contact layer 47 is dry-etched, or 3 of the active layer 45 / ohmic contact layer 47 / first barrier metal layer 59a. All the layers are dry etched or all three layers are wet etched to pattern the gate insulating layer 39.
도 6c를 참조하면, 게이트절연막(39) 상에 주금속층(59c)과 제2 배리어금속층(59b)이 제1배리어금속층(59a)을 덮도록 CVD방법 또는 스퍼터링(sputtering)방법으로 연속적으로 증착된다.Referring to FIG. 6C, the main metal layer 59c and the second barrier metal layer 59b are continuously deposited on the gate insulating film 39 by the CVD method or the sputtering method so as to cover the first barrier metal layer 59a. .
그리고, 주금속층(59c)과 제2 배리어금속층(59b)을 제1 배리어금속층(59a)이 노출되도록 포토리쏘그래피방법으로 패터닝하여 게이트라인(41)과 수직되는 데이터패드(57)와, 소스 및 드레인전극(35,37)이 형성된다. 여기서, 주금속층은 알루미늄(Al) 또는 알루미늄 합금으로 형성되며, 제2 배리어금속층(59b)은 몰리브덴(Mo),크롬(Cr), 텅스텐(W), 티탄(Ti)등으로 형성된다. 제2 배리어금속층(59b)은 제1 배리어금속층(59a)과 동일한 금속으로 형성될 수도 있다.The main metal layer 59c and the second barrier metal layer 59b are patterned by a photolithography method so that the first barrier metal layer 59a is exposed, the data pad 57 perpendicular to the gate line 41, a source and Drain electrodes 35 and 37 are formed. Here, the main metal layer is formed of aluminum (Al) or aluminum alloy, the second barrier metal layer 59b is formed of molybdenum (Mo), chromium (Cr), tungsten (W), titanium (Ti) and the like. The second barrier metal layer 59b may be formed of the same metal as the first barrier metal layer 59a.
소스 및 드레인전극(35,37) 패터닝한 후 소스 및 드레인전극(35,37) 사이로 제1 배리어금속층(59a)과 오믹접촉층(47)을 건식식각으로 패터닝하여 활성층(45)이 노출된다. 활성층(45)의 소스 및 드레인전극(35,37)사이의 게이트전극(33)과 대응하는 부분은 채널이 된다.After patterning the source and drain electrodes 35 and 37, the active layer 45 is exposed by dry etching the first barrier metal layer 59a and the ohmic contact layer 47 between the source and drain electrodes 35 and 37. The portion corresponding to the gate electrode 33 between the source and drain electrodes 35 and 37 of the active layer 45 becomes a channel.
도 6d를 참조하면, 게이트절연층(39) 상에 데이터패드(57), 소스 및 드레인전극(35,37)과, 기판(31)상에 게이트패드(55)를 덮도록 질화실리콘 또는 산화실리콘 등의 무기절연물질 또는 아크릴계(acryl)유기화합물, 테프론(Teflon), BCB(benzocyclobutene), 사이토프(cytop) 또는 PFCB(perfluorocyclobutane)등의 유전상수가 작은 유기절연물을 증착하여 보호층(51)이 형성된다.Referring to FIG. 6D, silicon nitride or silicon oxide is disposed on the gate insulating layer 39 to cover the data pads 57, the source and drain electrodes 35 and 37, and the gate pads 55 on the substrate 31. The protective layer 51 may be formed by depositing an inorganic insulating material such as an inorganic insulating material such as an acryl organic compound, Teflon, BCB (benzocyclobutene), cytotope (cytop) or PFCB (perfluorocyclobutane). Is formed.
보호층(51)을 포토리쏘그래피방법으로 패터닝하여 드레인전극(37), 게이트패드(55) 및 데이터패드(57)를 노출시키는 제 1 내지 제 3접촉홀(49a,49b,49c)이 형성된다.The protective layer 51 is patterned by photolithography to form first to third contact holes 49a, 49b, and 49c exposing the drain electrode 37, the gate pad 55, and the data pad 57. .
도 6e를 참고하면, 보호층(51) 상에 투명한 전도성물질인 ITO, IZO, ITZO을 증착한 후 패터닝하여 보호층(51) 상의 TFT와 대응되는 부분을 제외한 부분에 화소전극(53) 및 보호전극(58)이 형성된다.Referring to FIG. 6E, the transparent conductive materials ITO, IZO, and ITZO are deposited on the protective layer 51 and patterned, and then, the pixel electrode 53 and the protective portion are disposed at portions other than the portions corresponding to the TFTs on the protective layer 51. An electrode 58 is formed.
보호전극(58)은 제1 접촉홀(49a)을 통해 게이트패드(55)와 접촉되며, 제3 접촉홀(49c)을 통해 데이터패드전극(57)과 접촉된다. 화소전극(53)은 제2 접촉홀(49b)을 통해 드레인전극(37)과 접촉된다.The protective electrode 58 is in contact with the gate pad 55 through the first contact hole 49a and the data pad electrode 57 through the third contact hole 49c. The pixel electrode 53 is in contact with the drain electrode 37 through the second contact hole 49b.
상술한 바와 같이, 본 발명에 따른 액정표시장치 및 그 제조방법은 반도체층과 제1 배리어금속층을 같이 패터닝함하고 그 위에 주금속층/제2 배리어금속층을 포함하는 소스 및 드레인전극을 형성함으로써 제1 배리어금속층의 식각을 방지할 수 있게 된다. 이에 따라, 제1 배리어금속층의 과도식각에 의한 주금속층과 반도체층과의 접촉을 방지하여 박막트랜지스터 특성의 저하를 방지할 수 있다. 이 결과, 고정세 액정표시장치의 품질을 향상과 수율을 향상시킬 수 있다.As described above, the liquid crystal display and the method of manufacturing the same according to the present invention are formed by patterning a semiconductor layer and a first barrier metal layer together, and forming a source and a drain electrode including a main metal layer and a second barrier metal layer thereon. Etching of the barrier metal layer can be prevented. Accordingly, contact between the main metal layer and the semiconductor layer due to the excessive etching of the first barrier metal layer can be prevented, thereby preventing the degradation of the thin film transistor characteristics. As a result, the quality and the yield of the high-definition liquid crystal display device can be improved.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
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KR100938885B1 (en) * | 2003-06-30 | 2010-01-27 | 엘지디스플레이 주식회사 | Liquid Crystal Display and method for fabricating of the same |
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KR100938885B1 (en) * | 2003-06-30 | 2010-01-27 | 엘지디스플레이 주식회사 | Liquid Crystal Display and method for fabricating of the same |
KR100937173B1 (en) * | 2006-12-26 | 2010-01-15 | 엘지디스플레이 주식회사 | An Array Substrate of Thin Film Transistor Liquid Crystal Display Device and the method for fabricating thereof |
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US9978777B2 (en) | 2016-01-11 | 2018-05-22 | Samsung Display Co., Ltd. | Display device including thin film transistor array panel and manufacturing method thereof |
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