KR101899930B1 - Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate for an FFE-type liquid crystal display device and a method of manufacturing the same. A data line crossing the gate line and defining a pixel region; A thin film transistor formed at a point of intersection of the gate line and the data line; A pixel electrode formed in a pixel region of the substrate and connected to the thin film transistor, the pixel electrode including a plurality of metallization regions; A passivation film formed on an entire surface of the substrate including the pixel electrode and the thin film transistor, the passivation film exposing a metallization region of the pixel electrode; And a plurality of common electrodes formed on the passivation film and overlapped with the pixel electrodes.

Description

TECHNICAL FIELD [0001] The present invention relates to an array substrate for an FFE-type liquid crystal display device and a method of manufacturing the array substrate.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an FFS (FFS) type liquid crystal display device and a manufacturing method thereof.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (hereinafter abbreviated as AM-LCD) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has received the most attention because of its excellent resolution and video realization ability.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field in which the common electrode and the pixel electrode are arranged in an up-down direction, and the characteristics such as transmittance and aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent.

Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

A conventional FFS type liquid crystal display device having such advantages has a large area pixel electrode (not shown) disposed on the entire surface of the pixel region, and an insulating film (not shown) And a plurality of common electrodes (not shown) are disposed.

Although not shown in the drawing, a conventional FFS type liquid crystal display device configured in this manner is configured such that, when a data signal is supplied to a large-area pixel electrode (not shown) through a thin film transistor (not shown) A fringe field is formed between a plurality of common electrodes (not shown) and a pixel electrode (not shown).

In the conventional FFS type liquid crystal display device having the above-described structure, transparent ITO (Indium Tin Oxide) is used as a pixel electrode material, and since the transmissive portion and the capacitor Cst region are used together, So that the FFE-type liquid crystal display device can not be used for a small-sized or higher-order model. That is, the large-area pixel electrode disposed on the entire surface of the pixel region shares the transmissive portion and the capacitor (Cst) region and does not require a separate storage capacitance space.

However, in the case of a conventional FFS type liquid crystal display device, a structure in which a common electrode is disposed at the top of a substrate and a part of the common electrode overlaps the data line is applied. At this time, Since the capacitance of the wiring increases, it is necessary to reduce the RC load by applying the low resistance wiring.

Therefore, since the conventional FFS type liquid crystal display device is very disadvantageous for pixel charging at the time of a large-sized product or a high-speed driving, the FFS type liquid crystal display device structure has been applied only to a small model so far .

As described above, in the conventional FEF LCD type liquid crystal display device, since the pixel electrode of a large area is configured to share the transmission region and the capacitor region of the pixel region, the self-charging area is wide, Do not.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems occurring in the prior art, and it is an object of the present invention to provide a liquid crystal display device capable of reducing the storage capacitance Cst by changing the material of a pixel electrode, And an array substrate for an F-type liquid crystal display device and a method of manufacturing the same.

According to an aspect of the present invention, there is provided an array substrate for an FPC-type liquid crystal display, including: a gate wiring and a data wiring crossing each other on a substrate to define a pixel region; A passivation film formed on the entire surface of the substrate including the pixel electrode and the thin film transistor, the passivation film exposing a part of the pixel electrode, and a passivation film formed on the entire surface of the substrate including the pixel electrode and the thin film transistor, And a plurality of common electrodes formed on the passivation film and overlapping the pixel electrodes, wherein the exposed pixel electrodes can constitute a metallization region.

According to an aspect of the present invention, there is provided a method of fabricating an array substrate for an FFS type liquid crystal display device, the method including forming a gate wiring on a substrate, forming a gate insulating film on the entire surface of the substrate including the gate wiring, Forming an active layer made of an oxide semiconductor and a pixel electrode over the gate insulating film; forming source and drain electrodes spaced apart from each other along with the data line on the active layer; Forming a passivation film and a transparent conductive layer on the entire surface of the substrate including the electrode and the drain electrode; patterning the transparent conductive layer and the passivation layer to form a plurality of common electrodes overlapping the pixel electrode, An opening for exposing a part of the pixel electrode is formed And performing a plasma treatment process through the opening to metallize the exposed part of the pixel electrode.

According to the array substrate for an F-FFS type liquid crystal display and the method of manufacturing the same according to the present invention, the following effects can be obtained.

In manufacturing an array substrate for an FFE type liquid crystal display according to the present invention, an oxide semiconductor such as IGZO (In-Ga-Zinc_Oxide) may be used instead of ITO (Indium Tin Oxide) ) Is used as a pixel electrode and a part of the oxide semiconductor constituting the pixel electrode is metallized so that a storage capacitance is not applied to the metallized region of the oxide semiconductor, It becomes possible to reduce the capacitance Cst region.

Therefore, in the array substrate for an FFC-type liquid crystal display according to the present invention, storage capacitance is not applied to the metallized region of the oxide semiconductor, so that the FFC-type liquid crystal display The device structure can be applied to a large-sized model such as a TV, and there is no problem in pixel charging at high-speed driving.

Further, since the FFS type liquid crystal display device structure can be applied to a large model such as a TV, the array substrate for an FFE type liquid crystal display device according to the present invention can be applied to an organic light emitting device (OLED) Diode device) can be expected to be low cost and high performance.

1 is a schematic plan view of an array substrate for an FFS type liquid crystal display according to the present invention.
FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and is a schematic cross-sectional view of an array substrate for an F-FFS type liquid crystal display according to the present invention.
3A to 3T are cross-sectional views illustrating an array substrate for an F-FFS type liquid crystal display according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an array substrate for an F-FFS type liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic plan view of an array substrate for an FFS type liquid crystal display according to the present invention.

FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and is a schematic cross-sectional view of an array substrate for an F-FFS type liquid crystal display according to the present invention.

As shown in FIGS. 1 and 2, the array substrate for an F-FFS type liquid crystal display according to the present invention includes a gate wiring 103a formed on one surface of a transparent substrate 101 in one direction; A data line 117a crossing the gate line 103a and defining a pixel region; A thin film transistor T formed at the intersection of the gate wiring 103a and the data wiring 117a; A pixel electrode 109b formed in the pixel region of the substrate 101 and having a large area directly connected to the thin film transistor T; A plurality of pixel electrodes 109b formed on the entire surface of the substrate including the pixel electrode 109b and the thin film transistor T and formed on the entire surface of the substrate including the thin film transistor T and the pixel electrode 109b, A passivation film 121 having pixel electrode openings 131 of the pixel electrodes 131; And a plurality of common electrodes 127a formed on the passivation film 121 and overlapped with the pixel electrodes 109b and the data lines 117a.

A transparent pixel electrode 109b having a large area is disposed on the entire surface of the pixel region of the substrate 101 with a space separated from the gate line 103a and the data line 117a. And a plurality of bar-shaped transparent common electrodes 127a spaced apart from each other by a predetermined distance are disposed on the upper side of the passivation film 121.

At this time, the common electrode 127a overlaps with the large-area pixel electrode 109b disposed in the pixel region, and a part of the common electrode 127a overlaps with the data line 117a.

The thin film transistor T includes a gate electrode 103b extending in a vertical direction from a gate wiring 103a formed on a transparent substrate 101, a gate insulating film 107 formed on the gate electrode 103b, A etch stop layer pattern 109a formed on the active layer 109a and an etch stop layer pattern 113b formed on the channel region of the active layer 109a, And a source electrode 117b and a drain electrode 117c spaced apart from each other by a channel region of the active layer 109a. In this case, the active layer (109a) is IGZO (In-Ga-Zinc- Oxide) of a material, ZnO, ZnO _2, CdO, SrO, SrO _2, CaO, CaO _2, MgO, MgO _2, InO, In ₂ O ₂ , a _{GaO, Ga 2 O, Ga 2} O 3, SnO, SnO 2, GeO, GeO 2, PbO, Pb 2 O 3, Pb 3 O 4, TiO, TiO 2, Ti 2 O 3, and Ti ₃ O ₅ Any one of the oxide semiconductors is used. That is, one of the combinations of the elements in the group D and the group P in the element periodic table is selected and used.

Here, the case where IGZO (In-Ga-Zinc-Oxide) which is an oxide semiconductor is used as the active layer 109a will be described as an example.

In addition, the pixel electrode (109b) is the active layer (109a) and the same oxide semiconductor, for example, IGZO (In-Ga-Zinc- Oxide), ZnO, ZnO 2, CdO, SrO, SrO 2, CaO, CaO 2 _{, MgO, MgO 2, InO,} In 2 O 2, GaO, Ga 2 O, Ga 2 O 3, SnO, SnO 2, GeO, GeO 2, PbO, Pb 2 O 3, Pb 3 O 4, TiO, TiO 2 , Ti ₂ O ₃ , and Ti ₃ O ₅ . That is, one of the combinations of the elements in the group D and the group P in the element periodic table is selected and used. Here, a case in which an oxide semiconductor IGZO (In-Ga-Zinc-Oxide) is used as the pixel electrode 109b will be described as an example.

At this time, a part of the pixel electrode 109b, that is, the region A exposed through the pixel electrode opening 131 is metallized by plasma treatment.

Further, although not shown in the figure, a lower alignment film (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 127a.

On the other hand, a black matrix (BM) 143 for blocking light from being transmitted to the region excluding the pixel region is formed on the color filter substrate 141, which is adhered to the substrate 101, that is, Is formed.

In addition, color filter layers 145 of red, green, and blue colors are formed in the pixel region of the color filter substrate 141. At this time, the black matrix 143 is formed on the color filter substrate 141 between the color filter layers 145 of red, green, and blue colors.

When the color filter substrate 141 and the substrate 101 as a thin film transistor substrate are attached together, the black matrix 143 is formed in a region excluding the pixel region of the insulating substrate 101, for example, a thin film transistor T ), The gate wiring 103a, and the data wiring 117a. At this time, the line width of the black matrix 117b overlapping the data line 117a may be the same as or narrower than the data line 117a.

Although not shown in the figure, an upper alignment film (not shown) is formed on the color filter layer 145 to align the liquid crystal in a predetermined direction.

When a data signal is supplied to the pixel electrode 109b through the thin film transistor T, a fringe field is formed between the common electrode 127a and the pixel electrode 109b to which a common voltage is supplied , The liquid crystal molecules arranged in the horizontal direction between the substrate 101 and the color filter substrate 141 are rotated by dielectric anisotropy so that the light transmittance of the liquid crystal molecules transmitted through the pixel region varies depending on the degree of rotation, .

According to the present invention, an oxide semiconductor, for example, IGZO (In-Ga-Zinc-Oxide) is used as a pixel electrode in place of ITO (Indium Tin Oxide) It is possible to reduce the capacitance Cst region by itself because the metallized region does not have storage capacitance.

Therefore, in the array substrate for an FFC-type liquid crystal display according to the present invention, storage capacitance is not applied to the metallized region of the oxide semiconductor, so that the FFC-type liquid crystal display The device structure can be applied to a large-sized model such as a TV, and there is no problem in pixel charging at high speed driving.

Further, since the FFS type liquid crystal display device structure can be applied to a large model such as a TV, the array substrate for an FFE type liquid crystal display device according to the present invention can be applied to an organic light emitting device (OLED) A low cost and a high performance can be expected than a diode device.

A method of fabricating an array substrate for a FFS type liquid crystal display according to the present invention will be described with reference to FIGS. 3A to 3T.

3A to 3T are cross-sectional views illustrating an array substrate for an F-FFS type liquid crystal display according to the present invention.

3A, a plurality of pixel regions including a switching region are defined on a transparent substrate 101, and a first conductive metal layer 103 is sequentially deposited on the substrate 101 by a sputtering method . As the material of the first conductive metal layer 103, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten A single film consisting of at least one selected from the group of conductive metals including titanium (MoTi) and copper / moly titanium (Cu / MoTi), a double film consisting of two films or a triple film consisting of three films. Here, a laminated structure of a double-layer structure, for example, molybdenum (Mo) / neodymium (Nd) is taken as an example. At this time, the molybdenum (Mo) is deposited to a thickness of 150 to 300 Å, and the neodymium (Nd) is deposited to a thickness of 1000 to 3000 Å.

Then, a photo-resist having high transmittance is applied on the first conductive metal layer 103 to form a first photoresist layer 105.

Next, as shown in FIG. 3B, the first photoresist layer 105 is selectively removed by performing a photolithography process using a first mask (not shown) to expose and develop the photoresist layer 105, The first photoresist pattern 105a corresponding to the gate pad formation region is formed.

3C, the first conductive metal layer 103 is selectively etched using the first photoresist pattern 105a as an etching mask to form a gate wiring (not shown in FIG. 2, 103a) A gate electrode 103b and a gate pad 103c extending from the gate wiring 103a are formed at the same time.

Then, the, after removing the photoresist pattern (105a), a gate insulating film 107 made of silicon nitride (SiNx) or silicon oxide (SiO ₂₎ over the entire surface of the substrate including the gate electrode (103c) as shown in Figure 3d And the oxide semiconductor layer 109 is deposited on the gate insulating film 107 and annealed. The gate insulating film 107 is formed by depositing the oxide semiconductor layer 109 on the gate insulating film 107 by a CVD (Chemical Vapor Deposition) method. In this case, in the oxide semiconductor layer 109, the material is IGZO (In-Ga- Zinc-Oxide), ZnO, ZnO _2, CdO, SrO, SrO _2, CaO, CaO _2, MgO, MgO _2, InO, In ₂ O _{2, GaO, Ga 2 O,} Ga 2 O 3, SnO, SnO 2, GeO, GeO 2, PbO, Pb 2 O 3, Pb 3 O 4, TiO, TiO 2, Ti 2 O 3, and Ti ₃ O ₅ Is used as the oxide semiconductor. That is, one of the combinations of the elements in the D and P groups is selected and used in the periodic table of the elements. Here, IGZO (In-Ga-Zinc-Oxide) is used as the material of the oxide semiconductor layer 109. At this time, the oxide semiconductor layer 109 is deposited to a thickness of 400 to 1000 ANGSTROM.

Then, a photo-resist having a high transmittance is coated on the oxide semiconductor layer 109 to form a second photoresist layer 111.

Then, as shown in FIG. 3E, the second photoresist pattern 111 is selectively patterned by performing an exposure and a development process by a photolithography process technique using a second mask (not shown) to form a second photoresist pattern 111a ).

3F, the oxide semiconductor layer 109 is selectively etched using the second photoresist pattern 111a as an etching mask to simultaneously form the active layer 109a and the pixel electrode 109b do. At this time, the pixel electrode 109b has a large area and is formed on the entire surface of the pixel region of the substrate. The active layer 109a and the pixel electrode 109b are spaced apart from each other by a predetermined distance.

Then, too, the second photoresist after removing the pattern (111a), a silicon nitride (SiNx) or silicon oxide film on the substrate surface including the active layer (109a) and the pixel electrode (109b), as illustrated in 3g (SiO ₂ A second photoresist 115 is formed on the etch stop layer 113 by applying a photoresist having a high transmittance to the top of the etch stop layer 113.

Next, as shown in FIG. 3H, the second photoresist pattern 115 is selectively patterned by performing an exposure and a development process by a photolithography process technique using a third mask (not shown) to form a second photoresist pattern 115a.

Next, as shown in FIG. 3I, the etch stop layer 113 is selectively etched using the third photoresist pattern 115a as an etch mask to form an etch stop layer pattern 113a. At this time, the etch stop film pattern 113a is formed on the channel region of the active layer 109a.

Next, as shown in FIG. 3J, after the third photoresist pattern 115a is removed, a second conductive metal layer 117 is deposited on the entire surface of the substrate including the etch stop film pattern 113a by a sputtering method. The second conductive metal layer 117 may be formed of a material selected from the group consisting of Al, tungsten, copper, molybdenum, chromium, titanium, molybdenum, A single film consisting of at least one selected from the group consisting of molybdenum (MoTi) and a conductive metal group comprising copper / moly titanium (Cu / MoTi), a double film consisting of two films or a triple film consisting of three films. Here, the case where a laminated structure of a triple film structure, for example, first molybdenum (Mo) / neodymium (Nd) / second molybdenum (Mo) is applied will be described as an example. At this time, the first molybdenum (Mo) is deposited to a thickness of 150 to 300 Å, the neodymium (Nd) is deposited to a thickness of 1000 to 3000 Å, and the second molybdenum (Mo) is deposited to a thickness of 50 to 150 Å.

Then, a photo-resist having a high transmittance is applied on the second conductive metal layer 117 to form a fourth photoresist layer 119.

Next, as shown in FIG. 3K, the fourth photoresist pattern 119 is selectively patterned by performing an exposure and a development process by a photolithography process technique using a fourth mask (not shown) to form a fourth photoresist pattern 119a.

Then, as shown in FIG. 31, the second conductive metal layer 117 is selectively etched using the fourth photoresist pattern 119a as an etch mask to form a data line (for example, A source electrode 117b and a drain electrode 117c spaced apart from each other with reference to the etch stop film pattern 113a are simultaneously formed on the active layer 109a. At this time, the drain electrode 117c is in direct contact with the pixel electrode 109b and is electrically connected. In addition, a data pad (not shown in FIG. 2, 117d) is formed at one end of the data line 117a.

 After the fourth photoresist pattern 119a is removed, an inorganic insulating material or an organic insulating material is deposited on the entire surface of the substrate including the source electrode 117b and the drain electrode 117c to form a passivation layer 121 And then a photo-resist having a high transmittance is applied on the passivation film 121 to form a fifth photoresist film 123. The passivation film 121 may have a thickness of 4000 to 7000 angstroms Lt; / RTI >

Next, as shown in FIG. 3M, the fifth photoresist pattern 123 is removed by performing the exposure and development processes by a photolithography process technique using a fifth mask (not shown) to form the fifth photoresist pattern 123a .

3N, the passivation film 121 and the gate insulating film 107 thereunder are selectively etched using the fifth photoresist pattern 123a as an etching mask to expose the gate pad 103c A gate pad contact hole 125b for exposing the data pad 117d and a data pad contact hole 125c for exposing the data pad 117d are formed at the same time.

3O, the fifth photoresist pattern 123a is removed and a transparent conductive material is deposited on the passivation film 121 including the gate pad contact hole 125b and the data pad contact hole 125c, Layer 127 is deposited by DC magnetron sputtering. At this time, the transparent conductive material layer 127 may be any one selected from the group of transparent materials including ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

Then, a photo-resist having a high transmittance is applied on the transparent conductive material layer 127 to form a sixth photoresist layer 129.

Next, as shown in FIG. 3P, the sixth photoresist pattern 129 is removed by performing a photolithography process technique using a sixth mask (not shown) to expose the sixth photoresist pattern 129a .

Then, as shown in FIG. 3Q, the transparent conductive material layer 129 is selectively etched through a wet etching process using the sixth photoresist pattern 129a as a mask to form a plurality of spaced apart A gate pad connection pattern 127b connected to the gate pad 103c and the data pad 117d through the gate pad contact hole 125a and the data pad contact hole 125b together with the common electrode 127a, Thereby forming a data pad connecting pattern 127c.

The passivation film 121 is selectively etched through a dry etching process using the sixth photoresist pattern 129a as an etching mask so that a part of the pixel electrode 109b is exposed A plurality of pixel electrode openings 131 are formed.

3 r, the plasma processing process is performed after removing the sixth photoresist pattern 129a, and then heat treatment is performed to expose the exposed portion of the pixel electrode 109b under the pixel electrode opening 131, To form the metallization region A. The metallization region A is formed by a metallization process. At this time, the plasma process is performed using at least one of He, SF ₆ , CF ₄ , and Ar gas. Here, the plasma treatment process using SF ₆ and He gas is described as an example.

Further, the pixel electrode aperture 131. metallization of the exposed pixel electrode (109b) (metallization), i.e. oxide metallization (metallization) of the IGZO semiconductor, the following is achieved by the interaction of SF ₆ and He.

Therefore, when the plasma process using SF ₆ and He is performed in this manner, the resistance of the pixel electrode 109b decreases according to the plasma processing time, and the uniformity is improved. For example, as the SF ₆ plasma processing time is increased from 30 seconds (sec) to 90 seconds, the resistance of the metallization region A of the pixel electrode 109b is reduced and the uniformity is improved. That is, when the plasma processing time is 30 seconds, the resistance value of the metallization area A is about 7941 kΩ. However, when the plasma processing time is 60 seconds, a resistance value of about 89 kΩ is obtained. When the plasma processing time is 90 seconds, About 44 kΩ is obtained. In particular, when the resistance value is about 100 to 200 or less, it can be considered to have metallization properties.

Therefore, in the case of the present invention, the metallization region A of the pixel electrode 109b has a metallization characteristic when the plasma processing time is at least 30 seconds or more.

Next, a bottom orientation film (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 127a, thereby completing the fabrication process of the array substrate for the FFS type liquid crystal display according to the present invention.

Then, as shown in FIG. 3 (t), on the color filter substrate 141 separated from the thin film transistor substrate, that is, the substrate 101, to prevent light from being transmitted to regions other than the pixel region, A black matrix (BM) 143 is formed.

Next, a color filter layer 145 of red, green, and blue colors is formed in the pixel region of the color filter substrate 141. At this time, the black matrix 143 is located on the color filter substrate 141 between the red, green, and blue color filter layers 145.

At this time, the black matrix 143 is formed in a region excluding the pixel region of the substrate 101, for example, a thin film transistor T ), The gate wiring 103a, and the data wiring 117a.

Although not shown in the drawings, a process of manufacturing a color filter array substrate is completed by forming an upper alignment layer (not shown) on the color filter layer 145 so as to align liquid crystals in a predetermined direction.

Then, a liquid crystal layer 151 is formed between the substrate 101 and the color filter substrate 141 to produce an FFS liquid crystal display device according to the present invention.

In the fabrication of the array substrate for an FFE type liquid crystal display device according to the present invention, an oxide semiconductor such as IGZO (In-Ga-Zinc) is used instead of ITO (Indium Tin Oxide) -Oxide is used as a pixel electrode and a part of the oxide semiconductor is metallized so that a part of the pixel electrode made of the oxide semiconductor is metallized and the resistance value is reduced. Since this storage capacitance is not applied, it becomes possible to reduce the capacitance (Cst) area by itself.

Therefore, in the array substrate for an FFC-type liquid crystal display according to the present invention, storage capacitance is not applied to the metallized region of the oxide semiconductor, so that the FFC-type liquid crystal display The device structure can be applied to a large-sized model such as a TV, and there is no problem in pixel charging at high speed driving.

Further, since the FFS type liquid crystal display device structure can be applied to a large model such as a TV, the array substrate for an FFE type liquid crystal display device according to the present invention can be applied to an organic light emitting device (OLED) Diode device) can be expected to be low cost and high performance.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

101: substrate 103a: gate wiring
103b: gate electrode 103c: gate pad
107: gate insulating film 109a: active layer
109b: pixel electrode 113a: etch stop film pattern
117a: data line 117b: source electrode
117c: drain electrode 117d: data pad
121: Passivation film 125a: Gate pad contact hole
125b: Data pad contact hole 127a: Common electrode
127b: gate pad connection pattern 127c: data pad connection pattern
131: pixel electrode opening 141: color filter substrate
143: black matrix 145: color filter layer
151: liquid crystal layer A: metallization region

Claims (12)

A gate wiring and a data wiring crossing each other on the substrate to define a pixel region;
A thin film transistor formed at an intersection of the gate line and the data line;
A pixel electrode made of the same oxide semiconductor as the active layer of the thin film transistor in the pixel region;
A passivation film formed on the entire surface of the substrate including the pixel electrode and the thin film transistor, the passivation film exposing a part of the pixel electrode; And
And a plurality of common electrodes formed on the passivation film and overlapping the pixel electrodes, wherein the exposed pixel electrodes constitute a metallization region. The thin film transistor according to claim 1,
A gate electrode extending from the gate wiring;
A gate insulating film formed on the gate electrode;
The active layer formed on the gate insulating film,
An etch stop layer pattern formed on the active layer; And
And a source electrode and a drain electrode spaced apart above the active layer with reference to the etch stop film pattern. The array substrate according to claim 2, wherein the drain electrode is directly connected to the pixel electrode on the pixel electrode. The array substrate according to claim 2, wherein the plurality of common electrodes overlap the pixel electrodes and the data lines and are spaced apart from each other. The method of claim 1, wherein the oxide semiconductor is IGZO (In-Ga-Zinc- Oxide), ZnO, ZnO 2, CdO, SrO, SrO 2, CaO, CaO 2, MgO, MgO 2, InO, In 2 O 2, among _{GaO, Ga 2 O, Ga 2} O 3, SnO, SnO 2, GeO, GeO 2, PbO, Pb 2 O 3, Pb 3 O 4, TiO, TiO 2, Ti 2 O 3, and Ti ₃ O ₅ which And an array substrate for a liquid crystal display device. The array substrate according to claim 1, wherein the common electrode overlaps with the pixel electrode in a region other than the metallization region of the pixel electrode. Forming a gate wiring on the substrate;
Forming a gate insulating film on the entire surface of the substrate including the gate wiring;
Forming an active layer made of an oxide semiconductor and a pixel electrode on the gate insulating layer;
Forming a source electrode and a drain electrode spaced apart from each other along with the data line on the active layer;
Forming a passivation film and a transparent conductive layer on the entire surface of the substrate including the data electrode, the source electrode, and the drain electrode;
Forming an opening for exposing a part of the pixel electrode between the plurality of common electrodes with a plurality of common electrodes overlapping the pixel electrode by patterning the transparent conductive layer and the passivation film; And
And performing a plasma treatment process through the opening to metallize an exposed partial area of the pixel electrode. 8. The method of claim 7, wherein the plurality of common electrodes overlap the pixel electrodes and the data lines and are spaced apart from each other. The method of claim 8, wherein the oxide semiconductor is IGZO (In-Ga-Zinc- Oxide), ZnO, ZnO 2, CdO, SrO, SrO 2, CaO, CaO 2, MgO, MgO 2, InO, In 2 O 2, among _{GaO, Ga 2 O, Ga 2} O 3, SnO, SnO 2, GeO, GeO 2, PbO, Pb 2 O 3, Pb 3 O 4, TiO, TiO 2, Ti 2 O 3, and Ti ₃ O ₅ which Wherein the first and second substrates are formed as a single substrate. The method of claim 7, wherein the plasma treatment is performed using at least one gas plasma selected from He, SF ₆ , CF ₄ , and Ar gases. The method of manufacturing an array substrate for a liquid crystal display according to claim 7, wherein the plasma process is performed for 30 seconds or more. 8. The method of claim 7, wherein the common electrode overlaps with the pixel electrode in the remaining region excluding the exposed partial area of the pixel electrode.

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