CN111679517A

CN111679517A - Display panel, manufacturing method thereof and display device

Info

Publication number: CN111679517A
Application number: CN202010592330.XA
Authority: CN
Inventors: 黄建龙
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2020-09-18

Abstract

The application discloses a display panel and a manufacturing method thereof, and a display device, wherein the display panel comprises an array substrate and a color film substrate which are oppositely arranged, and a liquid crystal layer positioned between the array substrate and the color film substrate; the array substrate comprises a plurality of thin film transistors arranged in an array, an insulating layer, a common electrode and a pixel electrode, wherein the insulating layer, the common electrode and the pixel electrode are positioned above the thin film transistors, the common electrode and the pixel electrode are arranged on the insulating layer at the same layer and are distributed at intervals in the horizontal direction, and the pixel electrode is electrically connected with the thin film transistors. The display panel of the application arranges the pixel electrode and the public electrode on the same layer at a horizontal interval, and a lateral storage capacitor and a transverse electric field are formed between the pixel electrode and the public electrode to drive the liquid crystal to rotate. According to the method, the common electrode and the pixel electrode are prepared by using the same photomask, so that the using number of the photomasks is reduced, and the manufacturing cost of the display panel is reduced.

Description

Display panel, manufacturing method thereof and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device.

Background

The lateral electric Field display mode includes an In-Plane Switching (IPS) mode and a Fringe Field Switching (FFS) mode. The lateral electric field display mode has wide and ideal applications in the field of liquid crystal display panels due to its excellent viewing angle characteristics, dynamic definition, and color reduction effects.

However, the lcd panel in the transverse electric field display mode often needs to be completed with different masks when forming different circuit patterns. Therefore, the number of photomasks required for the manufacturing process of the liquid crystal display panel is large, and the cost is high.

Disclosure of Invention

In order to solve the above problems, an object of the present invention is to provide a display panel and a method for manufacturing the same, and a display device, which can reduce the number of masks used and the manufacturing cost of the display panel.

The application provides a display panel, comprising

The liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the array substrate and the color film substrate are oppositely arranged, and the liquid crystal layer is positioned between the array substrate and the color film substrate;

the array substrate comprises a plurality of thin film transistors arranged in an array, an insulating layer, a common electrode and a pixel electrode, wherein the insulating layer, the common electrode and the pixel electrode are positioned above the thin film transistors, the common electrode and the pixel electrode are arranged on the insulating layer at the same layer and are distributed at intervals in the horizontal direction, and the pixel electrode is electrically connected with the thin film transistors.

In some embodiments, a first groove and a second groove are formed in the insulating layer at an interval on a surface facing the color filter substrate, the pixel electrode is located in the first groove, and the common electrode is located in the second groove.

In some embodiments, the insulating layer is further provided with a first via hole, the first via hole penetrates through the insulating layer, and the pixel electrode is electrically connected to the thin film transistor through the first via hole.

In some embodiments, the array substrate further includes an auxiliary electrode electrically connected to the common electrode, and the auxiliary electrode is connected to a common voltage signal line.

In some embodiments, the auxiliary electrode and the source and drain electrodes of the thin film transistor are disposed on the same layer, a second via hole is formed in the insulating layer, and the common electrode is filled in the second via hole and electrically connected to the auxiliary electrode.

In some embodiments, the insulating layer is an organic insulating material.

In some embodiments, the insulating layer serves as a planarization layer and a passivation layer of the array substrate.

The application provides a display device comprising the display panel.

The application provides a manufacturing method of a display panel, which comprises the following steps:

preparing an array substrate, wherein the array substrate comprises a plurality of thin film transistors which are arranged in an array;

forming an insulating layer on the thin film transistor;

preparing a common electrode and a pixel electrode on one side of the insulating layer, which is far away from the array substrate, wherein the common electrode and the pixel electrode are horizontally arranged on the insulating layer at intervals and electrically connected to the thin film transistor;

providing a color film substrate, and arranging the color film substrate and the array substrate in a box-to-box manner; and injecting liquid crystal between the array substrate and the color film substrate to form a liquid crystal layer.

In some embodiments, a first groove and a second groove are formed on the insulating layer at an interval on one surface facing the color film substrate, the pixel electrode is disposed in the first groove, and the common electrode is disposed in the second groove; and arranging a first via hole on the insulating layer, wherein the first via hole penetrates through the insulating layer, and the pixel electrode is filled into the first via hole and is in contact with the thin film transistor.

The application has the following advantages and technical effects:

compared with the prior art that the pixel electrode and the common electrode are arranged on different layers, the display panel of the application has the advantages that the pixel electrode and the common electrode are horizontally arranged on the same layer at intervals, and a lateral storage capacitor and a transverse electric field are formed between the pixel electrode and the common electrode to drive the liquid crystal to rotate. According to the method, the common electrode and the pixel electrode are prepared by using the same photomask, so that the using number of the photomasks is reduced, and the manufacturing cost of the display panel is reduced.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Fig. 2 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being directly adjacent or may comprise the first and second features being not in direct contact but in contact with each other by means of further features between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

The application provides a display panel, a manufacturing method thereof and a display device. The details will be described below separately.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The embodiment of the application provides a display panel 1000 in an IPS display mode, which includes an array substrate 100 and a color filter substrate 200 that are disposed opposite to each other, and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200. The array substrate 100 includes a plurality of thin film transistors 110 arranged in an array, an insulating layer 120 located above the thin film transistors 110, and a common electrode 130 and a pixel electrode 140. The common electrode 130 and the pixel electrode 140 are disposed on the insulating layer 120 at the same layer and are distributed at intervals in the horizontal direction, and the pixel electrode 140 is electrically connected to the thin film transistor 110.

In an embodiment, the thin film transistor 110 may be a top gate thin film transistor, but the embodiments of the present application are not limited thereto, and the thin film transistor 110 may also be a bottom gate thin film transistor, which may refer to the prior art specifically and will not be illustrated. In the present embodiment, the thin film transistor 110 includes a substrate 111, a light-shielding layer 112 disposed on the substrate 111, a buffer layer 113 disposed on the substrate 111 and covering the light-shielding layer 112, an active layer 114, a gate insulating layer 115, and a gate electrode 116 stacked in this order from bottom to top, and an interlayer dielectric layer 117 located above the buffer layer 113 and covering the active layer 114, the gate insulating layer 115, and the gate electrode 116. The active layer 114 includes a channel region 1141 and source and

drain regions

1142 and 1143 located at both sides of the channel region 1141. The thin film transistor 110 further includes a source electrode 118 and a drain electrode 119 on the interlayer dielectric layer 117, wherein the source electrode 118 and the drain electrode 119 are electrically connected to the source region 1142 and the drain region 1143, respectively. An insulating layer 120 is disposed over the interlayer dielectric layer 117 and covers the source 118 and the drain 119. The insulating layer 120 is provided with a first via hole 121, the first via hole 121 penetrates through the insulating layer 120, and the pixel electrode 140 contacts the drain electrode 119 of the thin film transistor 110 through the first via hole 121.

A first groove 151 and a second groove 152 which are arranged at intervals are formed on one surface of the insulating layer 120 facing the color filter substrate 200, the pixel electrode 140 is filled in the first groove 151, and the common electrode 130 is filled in the second groove 152.

Specifically, the common electrode 130 and the pixel electrode 140 are horizontally spaced on the insulating layer 120, and when a voltage is applied, a side storage capacitor is formed at the space, and a lateral electric field E is formed in the liquid crystal layer, including the horizontal electric field E between the common electrode 130 and the pixel electrode 140_xAnd a vertical electric field E_zThe liquid crystal molecules 310 are rotated in a designated direction by the transverse electric field E, thereby controlling the amount of light transmitted.

The array substrate 100 further includes an auxiliary electrode 131 electrically connected to the common electrode 130, and the auxiliary electrode 131 is connected to a common voltage signal line (not shown). In one embodiment, the auxiliary electrode 131 is disposed at the same layer as the source electrode 118 and the drain electrode 119 of the thin film transistor 110, but is disposed to be insulated from the source electrode 118 and the drain electrode 119. A second via hole 122 is opened in the insulating layer 120, and the common electrode 130 is electrically connected to the auxiliary electrode 131 through the second via hole 122. Specifically, a second via hole 122 is disposed in the insulating layer 120, and the common electrode 130 is filled in the second via hole 122 and contacts the auxiliary electrode 131. The auxiliary electrode 131, the source electrode 118 and the drain electrode 119 are disposed on the same layer, and the auxiliary electrode 131, the source electrode 118 and the drain electrode 119 can be prepared by using the same photomask, so that the number of photomasks used is reduced, and the cost is reduced.

The insulating layer 120 is made of an organic insulating material, and can perform a planarization function of a planarization layer and a protection function of a passivation layer. The display panel is only provided with one insulating layer, the common electrode and the pixel electrode are horizontally arranged in the insulating layer at intervals, and under the isolation of the insulating layer, the common electrode and the pixel electrode generate a side storage capacitor and a transverse electric field, so that the use number of light shades is effectively reduced, and the manufacturing cost of the liquid crystal display panel is reduced.

Of course, the display panel 1000 further includes components such as an alignment film, a polarizer, and a backlight, and the details thereof are not described herein, please refer to the prior art.

Referring to fig. 2, fig. 2 is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure. Referring to fig. 1, the manufacturing method includes the following steps:

step 101, preparing an array substrate 100, wherein the array substrate comprises a plurality of thin film transistors arranged in an array.

Specifically, a substrate 111 is provided, and the substrate 111 may be a glass substrate. On the substrate 111, a light-shielding layer 112 is formed. A buffer layer 113 is formed on the substrate 111 by Chemical Vapor Deposition (CVD) and covers the light-shielding layer 112. An amorphous indium gallium zinc oxide (a-IGZO) thin film is deposited on the buffer layer 113, and then the a-IGZO thin film is etched by a photolithography process to form the active layer 114. The active layer 114 includes a channel region 1141 and a source region 1142 and a drain region 1143 disposed on both sides of the channel region 1141. The deposition canIn a manner using Physical Vapor Deposition (PVD). Forming SiO on the buffer layer 113 by CVD_xA thin film, and covers the active layer 114.

Adopting PVD method to prepare SiO on silicon oxide_xForming a gate metal layer on the film, coating photoresist with the same pattern as the gate metal layer, and etching the gate metal layer and silicon oxide SiO unprotected by the photoresist by etching process_xA thin film, a gate insulating layer 115 and a gate electrode 116 are formed on the channel region 1141.

An interlayer dielectric layer 117 is formed on the buffer layer 113 and covers the active layer 114, the gate insulating layer 115 and the gate electrode 116, and the interlayer dielectric layer 117 may be silicon oxide (SiO)_x) Silicon nitride (SiN)_x) At least one of (1). Contact holes are formed in the interlayer dielectric layer 117 by photolithography corresponding to the source region 1142 and the drain region 1143. A source/drain metal layer is deposited on the interlayer dielectric layer 117 by PVD, and the source electrode 118 and the drain electrode 119, and the auxiliary electrode 131 are prepared by photolithography using the same photomask. The source and drain

electrodes

118 and 119 are in contact with the source and

drain regions

1142 and 1143, respectively, through contact holes.

In step 102, an insulating layer 120 is formed over the thin film transistor 110.

Specifically, a layer of insulating layer 120 is formed on the interlayer dielectric layer 117, the insulating layer 120 is made of an organic insulating material, and a semi-permeable mask (halftone) is used on one side of the insulating layer 120 away from the thin film transistor to prepare a first groove 151 and a second groove 152, and a first via hole 121 and a second via hole 122. The first and

second vias

121 and 122 penetrate the insulating layer 120.

In step 103, the common electrode 130 and the pixel electrode 140 are formed.

The pixel electrode 140 is disposed in the first groove 151. The common electrode 130 is disposed in the second groove 152. Specifically, a transparent ITO thin film is formed in the first and

second grooves

151 and 152 by PVD, and patterned by a photolithography process to form the pixel electrode 140 and the common electrode 130. The pixel electrode 140 is filled in the first via hole 121 and contacts the drain electrode 119 of the thin film transistor 110. The common electrode 130 is filled into the second via hole 122 and contacts the auxiliary electrode 131, and the auxiliary electrode 131 is connected to a common voltage signal line (not shown). In the embodiment of the present application, the common electrode 130 and the pixel electrode 140 are ITO (indium tin oxide) electrodes that are transparent at the same layer and are prepared by using the same mask. The transparent ITO electrode effectively improves the pixel aperture opening ratio.

Step 104, providing a color film substrate 200, and arranging the color film substrate and the array substrate 100 in a box-to-box manner; and injecting liquid crystal between the array substrate 100 and the color film substrate 200 to form a liquid crystal layer 300.

According to the manufacturing method of the display panel, the common electrode and the pixel electrode are prepared by the same photomask, the use of the photomask is saved, and the manufacturing cost of the display panel is reduced.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above detailed description is provided for one of the embodiments, and the technical solution of the present application is explained by applying a specific example, and the description of the above embodiment is only used to help understanding the technical solution of the present application and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel, comprising

2. The display panel according to claim 1, wherein a first groove and a second groove are formed in the insulating layer at an interval on a surface facing the color filter substrate, the pixel electrode is located in the first groove, and the common electrode is located in the second groove.

3. The display panel according to claim 1, wherein a first via hole is further formed in the insulating layer, the first via hole penetrates through the insulating layer, and the pixel electrode is electrically connected to the thin film transistor through the first via hole.

4. The display panel of claim 1, wherein the array substrate further comprises an auxiliary electrode electrically connected to the common electrode, and the auxiliary electrode is connected to a common voltage signal line.

5. The display panel according to claim 4, wherein the auxiliary electrode and the source and drain electrodes of the thin film transistor are disposed on the same layer, a second via hole is formed in the insulating layer, and the common electrode is filled in the second via hole and electrically connected to the auxiliary electrode.

6. The display panel according to claim 1, wherein the insulating layer is an organic insulating material.

7. The display panel according to claim 1, wherein the insulating layer serves as a planarization layer and a passivation layer of the array substrate.

8. A display device comprising the display panel according to any one of claims 1 to 7.

9. A method for manufacturing a display panel, comprising:

forming an insulating layer on the thin film transistor;

10. The manufacturing method according to claim 9, wherein a first groove and a second groove are provided at an interval on one surface of the insulating layer facing a color filter substrate, the pixel electrode is provided in the first groove, and the common electrode is provided in the second groove; and arranging a first via hole on the insulating layer, wherein the first via hole penetrates through the insulating layer, and the pixel electrode is filled into the first via hole and is in contact with the thin film transistor.