KR20070109612A - Method for fabricating poly-silicon thin film transistors array substrate - Google Patents

Abstract

A fabrication method of a polysilicon TFT(thin film transistor) array substrate is provided to perform storage doping on a capacitor lower electrode directly after masking a polysilicon semiconductor layer with a metal mask to reduce a process cost and an area occupied by equipment and simplify a process. A polysilicon layer is formed on a substrate. The polysilicon layer is patterned to form a semiconductor layer and a capacitor lower electrode(S4). The capacitor lower electrode is opened with a metal mask to perform storage doping. A gate insulating layer is formed on an entire surface including the semiconductor layer and the capacitor lower electrode(S5). A gate electrode and a capacitor upper electrode are formed on the gate insulating layer disposed on the semiconductor layer and the capacitor lower electrode. Impurities are injected to the semiconductor layer using the gate electrode as a mask to form source/drain areas. Source/drain electrodes contacting the source/drain areas of the semiconductor layer are formed. A pixel electrode contacting the drain electrode is formed.

Description

Method for manufacturing polysilicon TFT array substrate {Method For Fabricating Poly-Silicon Thin Film Transistors Array Substrate}

1A to 1C are process cross-sectional views for explaining storage doping according to the prior art.

2 is a plan view of a polysilicon TFT array substrate for explaining the present invention.

3A to 3E are process cross-sectional views of a polysilicon TFT array substrate for explaining the present invention.

4 is a process flowchart for explaining an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

11 Insulation substrate 12 Buffer layer

13 semiconductor layer 13a source region

13b: channel region 13c: drain region

14 gate insulating film 15 gate wiring

15a: gate electrode 16: interlayer insulating film

17: data wiring 17a: source electrode

17b: drain electrode 18: protective film

19; Pixel electrode 70: metal mask

71, 72, 73: 1st, 2nd, 3rd contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a method of manufacturing a polysilicon TFT array substrate intended to facilitate storage doping.

Active matrix liquid crystal display (AM-LCD) as a flat panel display device widely used in notebooks, personal digital assistants, TVs, aviation monitors, etc. due to low voltage driving, full color implementation, light weight and small size, etc. Thin Film Transistor (TFT) is mainly used. The thin film transistor is composed of a polycrystalline silicon having a crystalline phase and a semiconductor film made of amorphous silicon (amorphous silicon: a-Si) depending on which silicon is used as the semiconductor layer. It can be classified into using a semiconductor film. As polycrystalline silicon, polysilicon (poly-Si) or microcrystalline silicon (μc-Si) is mainly known.

A semiconductor made of polycrystalline silicon has a feature that carrier mobility is about 10 to 100 times larger than a semiconductor made of amorphous silicon, and has excellent characteristics as a constituent material of a switching element.

In addition, since a thin film transistor using polycrystalline silicon as an active layer is capable of high speed operation, in recent years, various logic circuits such as CMOS-TFT (Complementary Metal Oxide Semiconductor TFT), EPROM (Erasable and Programmable Read Only Memory), and EEPROM (Electrically) Erasable and Programmable Read Only Memory (RAM), RAM (Random Access Memory) or applied to a switching element constituting a driving circuit such as a liquid crystal display device, an electroluminescent display device.

The liquid crystal display device includes a TFT having a thin film transistor (TFT) for selectively applying a signal to a pixel electrode, and a storage device for maintaining a state of charge until a unit pixel area is next addressed. It consists of an array substrate, a color filter layer array substrate having a color filter layer for realizing color, a liquid crystal layer enclosed between the two substrates, and a driving circuit for driving the TFT array substrate to display an image by various external signals. Display.

In this case, the thin film transistor is a polysilicon thin film transistor, comprising: a polysilicon semiconductor layer including a source / drain region doped with impurities and a channel layer not doped with impurities, a gate electrode formed on the channel layer, and the semiconductor The source / drain electrodes are respectively contacted with the source / drain regions of the layer, and the pixel electrode is contacted with the drain electrode.

The storage capacitor includes a capacitor lower electrode doped with an impurity and a capacitor upper electrode overlapping the capacitor lower electrode with an insulating layer therebetween.

In this case, the capacitor lower electrode is provided on the same layer as the polysilicon semiconductor layer, and the capacitor upper electrode is provided on the same layer as the gate electrode.

In this case, when the storage doping is performed on the capacitor lower electrode, the mask is performed after masking the polysilicon semiconductor layer.

Hereinafter, the storage doping will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a process of storage doping according to the prior art.

First, as shown in FIG. 1A, polysilicon is deposited on the entire surface of the insulating substrate 111 by a plasma enhanced chemical vapor deposition (PECVD) method and patterned by photolithography to form a semiconductor layer 113. And a capacitor lower electrode 132.

Thereafter, the photoresist 160 is coated on the entire surface including the semiconductor layer 113 to a predetermined thickness and cured, and then a predetermined portion of the photoresist is exposed and developed. As shown in FIG. 1B, the capacitor lower electrode 132 is opened and the semiconductor layer 113 is patterned to be masked.

Next, storage doping is performed on the entire surface of the substrate 111. At this time, since the semiconductor layer is masked by the photoresist, impurities are doped only in the capacitor lower electrode.

Subsequently, as shown in FIG. 1C, the photoresist 160 is stripped, and silicon nitride is deposited on the entire surface of the substrate 111 to form a gate insulating layer 113.

Next, a low-resistance metal layer thereon, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW) and the like are deposited and patterned by photolithography to form the gate electrode 112 and the capacitor upper electrode 135.

However, the method of manufacturing a polysilicon TFT array substrate according to the prior art as described above has the following problems.

Conventionally, when performing storage doping to the capacitor lower electrode, a photoetch process using a photoresist was performed to mask the polysilicon semiconductor layer.

However, the photoetch process uses the principle that a certain photoresist undergoes a chemical reaction when the light is received to change its properties. The photoresist is applied to a substrate, and the photoresist is selectively exposed using ultraviolet wavelengths. (exposure), developing the exposed photoresist, performing storage doping using the developed photoresist as a mask, and stripping the photoresist Is done.

Therefore, there is a disadvantage that the process for performing storage doping is complicated and cumbersome.

In addition, in order to perform the photo-etching process, it is necessary to have a variety of equipment, so that the area occupied by the equipment is increased, and the process time and the process cost are also consumed. In the case of exposure equipment, since it is an expensive equipment, researches to omit the process of using the exposure equipment have been continued in recent years.

The present invention has been made to solve the above problems, polysilicon TFT to simplify the process and reduce the process cost by masking the polysilicon semiconductor layer with a metal mask, and directly performing storage doping to the capacitor lower electrode It is an object of the present invention to provide a method for manufacturing an array substrate.

The method of manufacturing a polysilicon TFT array substrate of the present invention for achieving the above object comprises the steps of forming a polysilicon layer on the substrate, patterning the polysilicon layer to form a semiconductor layer and a capacitor lower electrode; Opening the capacitor lower electrode with a metal mask and performing storage doping, forming a gate insulating layer on the entire surface including the semiconductor layer and the capacitor lower electrode, and forming a gate insulating layer on the semiconductor layer and the capacitor lower electrode. Forming a gate electrode and a capacitor upper electrode on the substrate, implanting impurities into the semiconductor layer using the gate electrode as a mask to form a source / drain region, and a source contacting the source / drain region of the semiconductor layer / Forming a drain electrode, and the pixel electrode in contact with the drain electrode It characterized by comprising the step of forming.

In this case, the forming of the polysilicon layer may be performed by directly depositing polysilicon already crystallized on the substrate or by depositing amorphous silicon and then crystallizing.

Meanwhile, a method of manufacturing a polysilicon TFT array substrate for achieving another object of the present invention includes forming an amorphous silicon layer on a substrate, opening a predetermined portion of the amorphous silicon layer with a metal mask, and then performing storage doping. And crystallizing the amorphous silicon layer into a polysilicon layer; patterning the polysilicon layer to form a semiconductor layer and a capacitor lower electrode; and a gate insulating film on the entire surface including the semiconductor layer and the capacitor lower electrode. Forming a gate electrode and a capacitor upper electrode on the gate insulating layer on the semiconductor layer and the capacitor lower electrode, and implanting impurities into the semiconductor layer using the gate electrode as a mask to form a source / drain region; Forming and contacting the source / drain regions of the semiconductor layer. / Forming the drain electrode, including the step of forming a pixel electrode which contacts with the drain electrode is characterized in that formed.

In this case, the metal mask is disposed so that a predetermined portion of the amorphous silicon layer in which the capacitor lower electrode is formed is opened, and there is no other pattern in the lower portion thereof, so the alignment process may be omitted.

After the storage doping, a crystallization process is performed, so that the metal mask may be in contact with the amorphous silicon layer. When the metal mask is in contact with the amorphous silicon layer rather than without contact, the doping may be performed in a desired area more precisely.

Meanwhile, the method may further include dehydrogenating the amorphous silicon layer before or after performing a storage doping after opening a predetermined portion of the amorphous silicon layer with a metal mask.

As described above, the present invention only aligns the metal mask without applying the photo etching process during storage doping, thereby simplifying the process and reducing the process cost.

Particularly, in the case of the polysilicon TFT liquid crystal display device, the size of the sub-pixel is about 72 ㅧ 222 μm. In the case of a recently manufactured metal mask, an opening having a width of 40 μm can be formed as much as possible, so that the metal mask is sufficiently stored. The capacitor part can be opened and the other parts, the channel part and the circuit part can be masked.

Therefore, storage doping may be performed using only a metal mask.

The present invention may be applied to a structure in which the semiconductor layer and the capacitor lower electrode are integrally formed, and may be applied to a structure in which the semiconductor layer and the capacitor lower electrode are integrally formed.

Hereinafter, a method of manufacturing a polysilicon TFT array substrate according to the present invention with reference to the accompanying drawings in detail as follows.

FIG. 2 is a plan view of a polysilicon TFT array substrate for explaining the present invention, and FIGS. 3A to 3E are process cross-sectional views of a polysilicon TFT array substrate for explaining the present invention, and FIG. 4 illustrates an embodiment of the present invention. It is process flowchart to make it.

In the polysilicon TFT array substrate according to the present invention, as shown in FIG. 2, the unit pixels are formed by the gate wirings 15 arranged in a row and the data wirings 17 perpendicularly arranged to the gate wirings 15. In the unit pixel, a TFT for controlling turn-on or turn-off of a voltage, a pixel electrode 19 for applying a signal voltage to a liquid crystal layer to a region through which light passes, and the gate wiring 15 A storage capacitor parallel to the capacitor is further provided to reduce the level-shift voltage and maintain the charge charged in the liquid crystal during the turn-off period of the thin film transistor (non-selection period). .

In this case, the TFT includes a semiconductor layer 13 including a source / drain region doped with an impurity and a channel layer not doped with an impurity, and a gate insulating film (not shown) formed on the entire surface including the semiconductor layer 13. A gate electrode 15a overlapping an upper portion of the channel layer of the semiconductor layer 13 on the gate insulating film, an interlayer insulating film (not shown) formed on the entire surface including the gate electrode 15a, and on the interlayer insulating film. Source / drain electrodes 17a and 17b contacted to the source / drain regions of the semiconductor layer 13 through the first and second contact holes 71 and 72, respectively. The pixel electrode 19 is connected through the third contact hole 73 to transfer a voltage.

The storage capacitor includes a capacitor lower electrode 32 doped with an impurity, a capacitor upper electrode 35 parallel to the gate wiring 15 and overlapping an upper capacitor lower electrode, and a gate insulating layer interposed therebetween. It consists of.

In this case, the upper and lower electrodes of the capacitor are extended to the outside of the active area to receive a voltage from the outside of the active area. For reference, FIG. 2 illustrates a structure in which the semiconductor layer and the capacitor lower electrode are separated from each other.

Hereinafter, the manufacturing method of the polysilicon TFT array substrate by this invention is demonstrated concretely.

First, as shown in FIG. 3A, a buffer layer 12 made of silicon oxide (SiO 2) is formed on the entire surface of the insulating substrate 11 by chemical vapor deposition or the like.

The buffer layer 12 prevents foreign matter from penetrating into the semiconductor layer in a subsequent process, protects the insulating substrate 11 from high temperature during the crystallization process of the amorphous silicon layer, and contacts the semiconductor layer to the insulating substrate 11. Improves properties.

Thereafter, a polysilicon layer is formed on the entire surface including the buffer layer 12 and patterned by photolithography to form the semiconductor layer 13 and the capacitor lower electrode 32. In this case, the semiconductor layer and the capacitor lower electrode may be formed integrally, or may be formed separately, as shown in FIG.

The polysilicon layer may be formed by directly depositing polysilicon or by depositing amorphous silicon and crystallizing polycrystalline.

The former method is LPCVD (Low Pressure Chemical Vapor Deposition) to be deposited at a high temperature of 550 ° C. or higher, and plasma deposited using SiF ₄ / SiH ₄ / H ₂ mixed gas at 400 ° C. or lower. PECVD (Plasma Enhanced Chemical Vapor Deposition), etc.

As a method of depositing and crystallizing the latter amorphous silicon layer, a solid phase crystallization method (SPC method: Solid Phase Crystallization) which is crystallized by heat treatment at high temperature for a long time, and an excimer laser annealing method (ELA method) which crystallizes by applying an excimer laser while heating to about 250 ° C : Eximer Lazer Annealing), and metal induced crystallization, which induces crystallization by depositing a metal on an amorphous silicon layer.

In the latter method, since there are a lot of dangling bonds on the surface of the amorphous silicon layer, interfacial bonding between SiO ₂ , which is a buffer layer, and the amorphous silicon layer may not be easily performed. Therefore, if necessary, before the crystallization of amorphous silicon, A dehydrogenation process may be performed to remove hydrogen.

Thereafter, as illustrated in FIG. 3B, the metal mask is aligned so that the open portion of the metal mask 70 is disposed on the capacitor lower electrode 32, and impurities are injected through the open portion of the metal mask to perform storage doping. Perform.

Subsequently, as shown in FIG. 3C, an inorganic material SiO ₂ , SiN x, or the like is deposited on the entire surface including the semiconductor layer 13 to form the gate insulating layer 14. do.

For example, a low resistance metal layer having a low specific resistance to prevent signal delay on the gate insulating layer 14 may include copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), Titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW), etc. are deposited and wet etched with HF, BOE, NH ₄ F or a mixed solution thereof to form a gate wiring (15 in FIG. 2) and a gate electrode 15a. And a capacitor upper electrode 35.

The gate electrode 15a is formed to overlap a predetermined portion of the semiconductor layer 13, and the capacitor upper electrode is formed to overlap the storage doped capacitor lower electrode.

Next, as shown in FIG. 3D, source / drain regions 13a and 13b are formed by doping a high concentration of n-type impurity ions into the semiconductor layer 13 using the gate electrode 15a as a mask. At this time, the semiconductor layer between the source region 13a and the drain region 13b where the impurity ions are not doped by the gate electrode 15a becomes the channel layer 13b. Of course, the n-type TFT may be formed by doping the n-type impurity ion, but the p-type TFT may be formed by doping the p-type impurity ion.

That is, a dopant gas ion is adsorbed on the surface of the semiconductor layer 13 by using a plasma made of a dopant gas containing no semiconductor film forming gas to terminate the dangling bond of the silicon layer. This is because if the dangling bond is large in the silicon layer, the carrier is subsequently caught by the dangling bond and the mobility is greatly reduced.

In this case, in the case of the n-type TFT, a gas obtained by diluting a phosphine (PH ₃ ) gas containing phosphorus (P) ions with hydrogen (H ₂ ) may be used as the dopant gas. Ions are mixed and adsorbed on the surface of the semiconductor layer 13.

Thereafter, as illustrated in FIG. 2D, an inorganic material SiO ₂ , SiNx, or the like is deposited on the entire surface including the gate electrode 15a by chemical vapor deposition to form an interlayer insulating film 16.

Subsequently, the semiconductor layer 13 is activated by RTA (Rapid Thermal Annealing), irradiation of a laser beam using an excimer laser, or thermal annealing using a furnace.

Specifically, the surface of the semiconductor layer 13 is irradiated with a beam of an excimer laser to diffuse the phosphorus ions adsorbed on the surface of the silicon layer into the silicon layer. In other words, the semiconductor layer 13 is melted instantly by the excimer laser irradiation, and the adsorbed phosphorus ions are dissolved into the film.

After completing the activation process as described above, the gate insulating layer 14 and the interlayer insulating layer 16 are etched to expose the source / drain regions 13a and 13b so as to expose the first and second contact holes (71 in FIG. 2). , 72). In order to etch the gate insulating layer 14 and the interlayer insulating layer 16, a dry etching is generally performed. In the dry etching process, a gas is injected into an etching chamber in a high vacuum state and then transformed into a plasma state so as to transform into a plasma state. ) Is used to etch the insulating layer in such a manner as to etch a predetermined region of the layer to be etched, and the accuracy of the pattern is relatively excellent.

Thereafter, as an example of the low resistance metal layer on the interlayer insulating layer 16, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) ), Molybdenum-tungsten (MoW), and the like, and wet etched with HF, BOE, NH ₄ F or a mixture thereof to contact the source / drain regions 13a and 13b, respectively. ) And a data line (17 in FIG. 2) defining a sub-pixel by perpendicularly crossing the gate line.

This completes a polysilicon thin film transistor having polysilicon as an active semiconductor layer.

Next, SiNx and SiO2, which are inorganic materials, are deposited on the entire surface including the source / drain electrodes 17a and 17b by chemical vapor deposition, or BCB (benzoicbutene) and acrylic resin (acryl resin), which are organic materials, are applied to the protective film 18. ).

Subsequently, the substrate is heated in the heat-resistant temperature range of the substrate, and hydrogen atoms contained in the protective film 18 are diffused into the polysilicon layer serving as the semiconductor layer to perform hydrogenation treatment. That is, by bonding hydrogen to the dangling bond of the silicon layer to terminate the dangling bond, the mobility of the carrier is secured, and the silicon layer is stabilized due to the strong bonding of the silicon layer and hydrogen.

After the hydrogenation process is completed as described above, the protective layer 18 is selectively removed to expose the drain electrode 17b to form a third contact hole (73 in FIG. 2).

Finally, a pixel electrode contacting the drain electrode 17b through the third contact hole by depositing and patterning indium tin oxide (ITO) or indium zinc oxide (IZO) on the front surface of the passivation layer 18. (37) is formed.

Thus, the polysilicon thin film transistor array substrate is completed.

As such, the present invention is characterized in that the impurity ion implantation process is easily performed with a metal mask without performing a photoetch process during storage doping.

However, in the above embodiment, as shown in FIG. 4, the storage doping (③) is performed between forming the semiconductor layer and the capacitor lower electrode (S4) and depositing the gate insulating film on the entire surface of the insulating substrate (S5). Although limited to what has been described, it will be apparent to those skilled in the art that various substitutions, modifications, and changes can be made without departing from the spirit and scope of the present invention. something to do.

In other words. As shown in FIG. 4, a storage doping (1) may be performed between the step of depositing amorphous silicon (a-Si) and the step of dehydrogenating hydrogen of the amorphous silicon layer (S2). Storage doping (2) may be performed between step S2 for dehydrogenating hydrogen of the amorphous silicon layer and step S3 of crystallizing the amorphous silicon layer with a polysilicon layer.

As in the former case, when the storage doping is performed after the step S4 of forming the semiconductor layer and the capacitor lower electrode, an alignment process must be performed so that the open portion is correctly aligned to the capacitor lower electrode during the metal mask alignment. As in the latter case, when the storage doping is performed before the step S4 of forming the semiconductor layer and the capacitor lower electrode, since the pattern does not exist at the bottom, the alignment process may be facilitated or omitted.

In the latter case, since the storage doping is performed before the crystallization step S3, the metal mask may be contacted with the amorphous silicon layer. Even if a scratch occurs by contact, the damage is removed in the crystallization step, so that the metal mask may be contacted.

The method of manufacturing a polysilicon TFT array substrate according to the present invention as described above has the following effects.

First, in the present invention, since the storage doping process is performed after only masking the storage capacitor portion with a metal mask without applying the photoetch process during storage doping, the process is simplified, the process cost is much reduced, and the area of equipment is greatly reduced. Will come.

 Second, before the crystallization of the amorphous silicon, storage doping using a metal mask may be performed. In this case, the storage doping may be performed while the metal mask is in contact with the amorphous silicon layer. This is because if a scratch or the like occurs in the amorphous silicon layer by the metal mask, it can be restored through a crystallization process.

As described above, when the metal mask is in contact with the amorphous silicon layer, storage doping may be performed in a desired area more precisely than when the metal mask is not in contact.

Third, when the storage doping is performed by arranging the open portion of the metal mask in the portion where the storage capacitor is formed before the polysilicon layer patterning, there is no separate pattern at the bottom, so it is not necessary to precisely align the metal mask. If possible, the alignment process may be omitted.

Fourth, the process of aligning the metal mask of the wide opening to block the pad portion and the circuit portion area when depositing the insulating material, metal material, the process is performed by the deposition process on the upper surface of the metal mask by the continuous deposition process Frequently, as in the present invention, the use of a metal mask in storage doping is much more advantageous for maintenance and application, such as the cleaning process is much reduced.

Claims (9)

Forming a polysilicon layer on the substrate, Patterning the polysilicon layer to form a semiconductor layer and a capacitor lower electrode; Opening the capacitor lower electrode with a metal mask and performing storage doping; Forming a gate insulating film on the entire surface including the semiconductor layer and the capacitor lower electrode; Forming a gate electrode and a capacitor upper electrode on the gate insulating layer on the semiconductor layer and the capacitor lower electrode; Implanting impurities into the semiconductor layer using the gate electrode as a mask to form a source / drain region; Forming a source / drain electrode in contact with the source / drain region of the semiconductor layer; And forming a pixel electrode in contact with the drain electrode. The method of claim 1, Forming the polysilicon layer, A method of manufacturing a polysilicon TFT array substrate, characterized in that formed by depositing polysilicon on a substrate or crystallization after depositing amorphous silicon. The method of claim 1, Wherein the semiconductor layer and the capacitor lower electrode are integrally formed or separated from each other. Forming an amorphous silicon layer on the substrate, Performing storage doping after opening a predetermined portion of the amorphous silicon layer with a metal mask; Crystallizing the amorphous silicon layer with a polysilicon layer, Patterning the polysilicon layer to form a semiconductor layer and a capacitor lower electrode; Forming a gate insulating film on the entire surface including the semiconductor layer and the capacitor lower electrode; Forming a gate electrode and a capacitor upper electrode on the gate insulating layer on the semiconductor layer and the capacitor lower electrode; Implanting impurities into the semiconductor layer using the gate electrode as a mask to form a source / drain region; Forming a source / drain electrode in contact with the source / drain region of the semiconductor layer; And forming a pixel electrode in contact with the drain electrode. The method of claim 4, wherein The metal mask is a method of manufacturing a polysilicon TFT array substrate, characterized in that arranged to open the portion where the capacitor lower electrode is formed. The method of claim 4, wherein In the step of performing the storage doping, And the metal mask is in contact with or not in contact with the amorphous silicon layer. The method of claim 4, wherein Before or after the step of performing the storage doping after opening a predetermined portion of the amorphous silicon layer with a metal mask, The method of manufacturing a polysilicon TFT array substrate further comprising the step of dehydrogenating the amorphous silicon layer. The method of claim 4, wherein Wherein the semiconductor layer and the capacitor lower electrode are integrally formed or separated from each other. The method of claim 4, wherein When the metal mask is placed, Method for producing a polysilicon TFT array substrate, characterized in that the alignment process of the metal mask is not performed.

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