KR20060104146A - Method for manufacturing of poly-si tft array substrate - Google Patents

Abstract

The present invention provides a method of manufacturing a polysilicon thin film transistor array substrate, further comprising forming an etch stop layer between the active layer and the insulating layer so as not to damage the active layer in forming a contact hole by removing the insulating layer over the active layer. A method of manufacturing an active layer, the method comprising: forming an active layer on a predetermined region of a substrate; forming a gate insulating film on the entire surface including the active layer; forming a gate electrode on the gate insulating film on the active layer; Implanting impurity ions with a gate electrode as a mask to form source / drain regions on both sides of the active layer, sequentially forming an etch stop layer and an interlayer insulating film on the entire surface including the gate electrode, and exposing the etch stop layer. Etching the interlayer dielectric layer over the source / drain regions until the Etching the etch stop layer exposed between the insulating films, etching the gate insulating film exposed between the etch stop layers to form a contact hole through which the source / drain regions are exposed, and source / drain regions through the contact holes. Forming a source / drain electrode in contact with the.

Etch stop layer, etching uniform

Description

Method for manufacturing of poly-Si TFT array substrate

1A to 1D are process cross-sectional views of a polysilicon thin film transistor according to the prior art.

2 and 3 are cross-sectional views of a polysilicon thin film transistor array substrate for explaining the problems caused by the prior art.

4A to 4D are process cross-sectional views of a polysilicon thin film transistor according to a first embodiment of the present invention.

5 is a time chart showing the etching time of the insulating film according to the present invention.

6A and 6B are cross-sectional views of a polysilicon thin film transistor according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

111: insulating substrate 112: gate electrode

113: active layer 113a: source region

113b: drain region 113c: channel region

114: gate insulating film 116: interlayer insulating film

118a: source electrode 118b: drain electrode

179 contact hole 190 etching stop layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing a polysilicon thin film transistor array substrate.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, active matrix liquid crystal display devices are widely used as flat panel display devices widely used in notebooks, personal digital assistants, TVs, aviation monitors, etc. due to low voltage driving, full color implementation, light weight and small size.

A general liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel has a predetermined space and is bonded to the color filter array substrate and the thin film transistor array substrate. And a liquid crystal layer injected between the two substrates.

In this case, the thin film transistor array substrate includes a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and each of the gate lines and data. A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing lines, and a plurality of thin film transistors (TFTs) that are switched by signals of the gate lines to transfer signals of the data lines to each pixel electrode. Film Transistor) is provided.

The thin film transistor can be classified into using an active layer made of amorphous silicon (amorphous silicon: a-Si) and an active layer made of polysilicon having a crystalline phase, depending on which silicon is used as the active layer. .

The active layer made of polysilicon has a carrier mobility of 10 to 100 times higher than the active layer made of amorphous silicon, so that a driving circuit can be made on a substrate, which is advantageous as a switching element of a high resolution panel.

Therefore, liquid crystal display devices using polysilicon as the active layer have been recognized as a technology for realizing next generation high performance intelligent display systems.

Hereinafter, a method of manufacturing a polysilicon thin film transistor array substrate according to the prior art will be described in detail with reference to the accompanying drawings.

1A to 1D are process cross-sectional views of a polysilicon thin film transistor according to the prior art, and FIGS. 2 and 3 are cross-sectional views of a polysilicon thin film transistor array substrate for explaining a problem according to the prior art.

As shown in FIG. 2, a polysilicon layer is formed on the entire surface of the insulating substrate 11 by plasma enhanced chemical vapor deposition (PECVD) and patterned by photolithography to form an active layer 13. .

In addition, the gate insulating layer 14 is formed by depositing SiO ₂ , which is an inorganic material, on the entire surface of the active layer 13, and depositing and patterning a low resistance metal layer thereon to form the gate electrode 12 and the gate wiring (not shown). To form.

Next, source / drain regions 13a and 13b are formed by doping a high concentration of n-type impurity ions into the active layer 13 using the gate electrode 12 as a mask. At this time, the active layer between the source region 13a and the drain region 13b where the impurity ions are not doped by the gate electrode 15 becomes the channel layer 13c.

Subsequently, SiO ₂ , which is an inorganic material, is deposited on the entire surface including the gate electrode 15 to form an interlayer insulating layer 16, and the gate insulating layer 14 and the interlayer insulating layer 16 are etched to form the source / drain regions. Contact holes 79 are formed in which 13a and 13b are exposed.

Specifically, the contact hole forming process consists of the following process.

First, as shown in FIG. 1A, a photoresist 78 is applied on the interlayer insulating film 16 and patterned by an exposure and development process. As shown in FIG. 1B, a photoresist on the active layer 13 is shown. Open (78).

Next, as shown in FIG. 1C, the interlayer insulating film 16 exposed between the photoresist 78 patterns is dry etched. At this time, only the upper portion of the interlayer insulating layer 16 is dry-etched and the lower layer is left.

Thereafter, as shown in FIG. 1D, the contact hole 79 exposing the active layer 13 is exposed by wet etching the lower layer of the interlayer insulating layer 16 and the gate insulating layer 14 exposed between the photoresist 78 patterns. Form. At this time, the reason why the gate insulating film 14 is not dry etched is that there is a risk of damage to the thin active layer by the plasma gas used during the dry etch.

 As such, after forming the contact hole 79 through which the active layer is exposed, as shown in FIG. 2, a low resistance metal layer is deposited and patterned on the interlayer insulating layer 16 to form the source / drain regions 13a, Source / drain electrodes 15a and 15b respectively contacted with 13b) and data lines (not shown) intersecting the gate lines are formed.

Thus, a polysilicon thin film transistor composed of the active layer 13, the gate electrode 12, and the source / drain electrodes 17a and 17b using polysilicon is completed.

Thereafter, SiNx, an inorganic material, is deposited on the entire surface including the source / drain electrodes 15a and 15b by chemical vapor deposition to form a passivation layer 18, and a pixel electrode contacting the drain electrode 15b thereon. 17) to complete the polysilicon thin film transistor array substrate.

However, the manufacturing method of the polysilicon thin film transistor array substrate according to the prior art has the following problems.

That is, as described above, the process of forming the contact hole in the polysilicon thin film transistor structure includes the interlayer insulating film etched by dry etching, followed by the interlayer insulating film and gate insulating film etched by wet etching. The dry etching process causes plasma damage to the polysilicon active layer, so the final process should always be done by wet etching.

However, since the gate insulating film and the interlayer insulating film have different uniformity and deposition forms, and the dry etching and the wet etching also have different etching profiles, defects in etching uniformity are generated when the final process is completed.

That is, as shown in "A" of FIG. 2, the source / drain electrodes may not contact the source / drain regions due to under etch according to the insulation film thickness nonuniformity and the etching condition nonuniformity. As shown in B ″, damage may occur to the polysilicon active layer by overetching the insulating film.

To improve this problem, the present invention further improves final etching uniformity by further depositing an etch stop layer having a very low etch rate before deposition of an interlayer insulating layer, thereby preventing active layer damage caused by over-etching. It is an object of the present invention to provide a method of manufacturing a thin film transistor array substrate.

Method of manufacturing a polysilicon thin film transistor array substrate according to the present invention for achieving the above object comprises the steps of forming an active layer in a predetermined region of the substrate, forming a gate insulating film on the entire surface including the active layer; Forming a gate electrode on the gate insulating layer on the active layer, implanting impurity ions with the gate electrode as a mask to form source / drain regions on both sides of the active layer, and etching the entire surface including the gate electrode Sequentially forming a stop layer and an interlayer insulating film, etching the interlayer insulating film over the source / drain regions until the etch stop layer is exposed, and etching the etch stop layer exposed between the interlayer insulating films; And etching the gate insulating layer exposed between the etch stop layers to form the source / drain regions. Forming a contact hole exposed and forming a source / drain electrode contacting the source / drain region through the contact hole.

Hereinafter, a method of manufacturing a polysilicon thin film transistor array substrate according to the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are process cross-sectional views of a polysilicon thin film transistor according to a first embodiment of the present invention, FIG. 5 is a time diagram showing an insulating film etching process time according to the present invention, and FIGS. 6A and 6B are views of the present invention. Process cross-sectional view of the polysilicon thin film transistor according to the second embodiment.

First, as shown in FIG. 4A, polysilicon is deposited and patterned on the entire surface of the insulating substrate 111 by chemical vapor deposition to form an active layer 113.

Next, the gate insulating layer 114 is formed by depositing SiO ₂ , which is an inorganic material, on the entire surface including the active layer 113, and a low resistance metal layer having a low specific resistance thereon to prevent signal delay. ), Aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW), etc., and deposited HF, BOE, NH ₄ F Or wet etching with a mixture of these to form a gate electrode 112 and a gate wiring (not shown).

The gate electrode 112 is formed to overlap a predetermined portion of the semiconductor layer 113, and a portion where the gate electrode 112 overlaps becomes a channel region of the active layer.

Subsequently, a high concentration of n-type or p-type impurity ions are doped into the semiconductor layer 113 using the gate electrode 112 as a mask to form source / drain regions 113a and 113b. Since the gate electrode 112 overlaps, the semiconductor layer between the source region 113a and the drain region 113b where the impurity ions are not doped becomes the channel layer 113c.

Thereafter, SiNx, an inorganic material, is deposited on the entire surface including the gate electrode 112 to form an etch stop layer 190, and SiO ₂ is deposited on the etch stop layer 190 to form an interlayer insulating film ( 116).

As shown in FIG. 4B, the source / drain regions 113a and 113b etch the interlayer insulating layer 116 thereon to form a contact hole 179 through which the etch stop layer 190 is exposed.

In this case, the interlayer insulating layer may be etched in two or one steps. First, the upper layer of the interlayer insulating layer may be etched and then the two layer insulating layer etching process of wet etching the lower layer of the interlayer insulating layer may be performed, or one dry etching may be performed. The interlayer insulating film etching process may be performed. However, when the interlayer insulating layer is etched in one step, an EPD (End Point Detector) is used. As shown in FIG. 5, when the SiO ₂ etching is completed and the SiNx etching starts, the EPD peak changes. When the EPD peak is stopped and the dry etching process is stopped, the etching stop layer remains uniform.

Thereafter, as shown in FIG. 4C, the etching stop layer 190 exposed between the contact holes 179 is dry-etched to expose the gate insulating layer 114. The dry etching process is used to etch the insulating film by spraying gas into the etching chamber in a high vacuum state and transforming it into a plasma state so that cations or radicals etch a predetermined region of the layer to be etched. Relatively good.

For reference, FIG. 5 is a time diagram showing time versus plasma discharge intensity in a dry etching process, where section 1 is a time for etching SiO ₂ (interlayer insulating film), and section 2 is SiNx (etching stop). Layer) is the time for etching, and section 3 is the time for SiO ₂ (gate insulating film) to be etched, and section 4 is the time for the active layer to be over-etched. Therefore, when the discharge is stopped at the end of the section when the change of the EPD peak is reported, the gate insulating film remains uniform.

Next, as shown in FIG. 4D, the gate insulating layer 114 exposed between the contact holes 179 is wet-etched to expose the source / drain regions 115a and 115b.

As a result, since the insulating film etching unevenness is eliminated, it is possible to prevent underetching or overetching defect. That is, the source / drain regions 115a and 115b on the entire surface of the substrate must be completely opened. Further, an etching stop layer is further provided between the gate insulating layer 114 and the interlayer insulating layer 116, whereby the thickness variation and the etching irregularity of the insulating layer are caused. Under etching or over etching can be prevented.

Afterwards, the low-resistance metal layer on the interlayer insulating layer 116 may include, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), and tantalum (Ta). Source / drain electrodes 118a and 118b deposited on the source / drain regions 115a and 115b by depositing molybdenum-tungsten (MoW) and wet etching with HF, BOE, NH ₄ F or a mixture thereof. ) And a data line (not shown) defining a pixel intersecting the gate line.

As a result, the polysilicon is formed of a top-gate poly, which is formed of a laminated film of an active active layer 113, a gate insulating film 114, a gate electrode 115, an interlayer insulating film 116, and source / drain electrodes 118a and 118b. The silicon thin film transistor is completed. In this case, the polysilicon thin film transistor is formed to be located at the intersection of the gate line and the data line.

Next, although not shown, a protective film is deposited on the entire surface including the source / drain electrodes by depositing an inorganic material, SiNx, SiO _2, by chemical vapor deposition, or by applying an organic material, benzocyclobutene (BCB), or an acrylic resin (acryl resin). And forming a contact hole by selectively removing the passivation layer to expose the drain electrode, and depositing and patterning indium tin oxide (ITO) or indium zinc oxide (IZO), etc., on the entire surface included on the passivation layer. A pixel electrode is formed in the pixel region to contact the drain electrode through the hole.

Thus, the polysilicon thin film transistor array substrate is completed.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

In the above, the present invention has been described in detail by providing an etching stop layer of SiNx between the SiO ₂ gate insulating film and the interlayer insulating film. However, the present invention is not limited thereto, and the SiO ₂ insulating film and SiNx etching are performed between the SiO ₂ gate insulating film and the interlayer insulating film. A stop film may be further provided so as not to be overetched or underetched when the gate insulating film is finally etched.

That is, as shown in FIG. 6A, a gate insulating film 214 that is SiO ₂ is formed on the entire surface including the active layer 213, a gate electrode 212 is formed thereon, and SiO is formed on the entire surface including the gate insulating layer. A first interlayer insulating film 216a of ₂ , an etch stop layer 290 of SiNx, and a second interlayer insulating film 216b of SiO ₂ are laminated.

Thereafter, as shown in FIG. 6B, the second interlayer insulating layer 216b, the etch stop layer 290, and the first interlayer insulating layer 216a are removed by dry etching using an EPD peak to form a contact hole 279. do. As a result, the gate insulating layer remains uniform. The gate insulating layer 214 exposed between the contact holes 279 is removed by wet etching to complete the contact hole 279 in which the active layer 213 is exposed. Therefore, damage to the active layer by plasma can be prevented, and under etch or over etch defect due to uneven thickness of the gate insulating film can be prevented.

The method of manufacturing a polysilicon thin film transistor array substrate according to the present invention as described above has the following effects.

In order to completely open the source / drain regions, the gate insulating film and the interlayer insulating film must be uniformly etched. An etching stop layer is further provided between the gate insulating film and the interlayer insulating film, thereby under-etching or over-etching due to the thickness and etching unevenness of the insulating film. To prevent them.

Therefore, it is possible to prevent defects due to etching irregularities to improve the electrical characteristics of the device.

Claims (15)

Forming an active layer in a predetermined region of the substrate; Forming a gate insulating film on the entire surface including the active layer; Forming a gate electrode on the gate insulating layer on the active layer; Implanting impurity ions into the gate electrode using a mask to form source / drain regions on both sides of the active layer; Sequentially forming an etch stop layer and an interlayer insulating film on the entire surface including the gate electrode; Etching the interlayer dielectric layer over the source / drain regions until the etch stop layer is exposed; Etching the etch stop layer exposed between the interlayer insulating films; Etching a gate insulating layer exposed between the etch stop layers to form a contact hole exposing the source / drain region; And forming a source / drain electrode contacted to the source / drain region through the contact hole. The method of claim 1, The active layer is a polysilicon thin film transistor array substrate manufacturing method, characterized in that formed of a polysilicon layer. The method of claim 1, The etch stop layer is a silicon nitride material, characterized in that the polysilicon transistor array substrate manufacturing method. The method of claim 1, The interlayer insulating film is a method of manufacturing a polysilicon thin film transistor array substrate, characterized in that formed of SiO ₂ . The method of claim 1, The gate insulating film is a method of manufacturing a polysilicon thin film transistor array substrate, characterized in that formed of SiO ₂ . The method of claim 1, Etching the interlayer insulating film, Etching an upper portion of the interlayer insulating film; And etching the lower portion of the interlayer insulating layer until the etch stop layer is exposed. The method of claim 6, In the etching of the upper portion of the interlayer insulating layer, a dry etching process is performed. And etching the lower portion of the interlayer insulating layer to perform a wet etching process. The method of claim 1, The etching of the interlayer dielectric layer may include etching the entire layer using an EPD (End Point Detector). The method of claim 8, And etching the interlayer insulating film to perform a dry etching process. The method of claim 1, In the etching of the etch stop layer, a dry etching process is performed. The method of claim 1, In the etching of the gate insulating film, a method of manufacturing a polysilicon thin film transistor array substrate, characterized in that for performing a wet etching process. The method of claim 1, Before the forming of the etch stop layer, the method of manufacturing a polysilicon thin film transistor array substrate, characterized in that further comprising an insulating film on the gate insulating film. The method of claim 12, The insulating film is a method of manufacturing a polysilicon thin film transistor array substrate, characterized in that to form SiO ₂ . The method of claim 1, Forming a gate wiring simultaneously with the gate electrode; Forming a data line simultaneously with the source / drain electrodes; Forming a protective film on the entire surface including the source / drain electrodes; And forming a pixel electrode contacting the drain electrode through the passivation layer. The method of claim 14, And a polysilicon thin film transistor comprising the active layer, the gate electrode, and the source / drain electrode is formed at an intersection point of the gate line and the data line.

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