CN104122713A - Manufacturing method of liquid crystal displayer array substrate - Google Patents
Manufacturing method of liquid crystal displayer array substrate Download PDFInfo
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- CN104122713A CN104122713A CN201310168698.3A CN201310168698A CN104122713A CN 104122713 A CN104122713 A CN 104122713A CN 201310168698 A CN201310168698 A CN 201310168698A CN 104122713 A CN104122713 A CN 104122713A
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Abstract
The invention provides a manufacturing method of a liquid crystal displayer array substrate. The manufacturing method comprises the steps that a plurality of grids, a plurality of grid lines and a plurality of public electrode lines are formed on the surface of the substrate, a grid insulation layer is formed to cover the substrate, the grids and the public electrode lines, a plurality of pixel electrodes are formed on the grid insulation layer, a passivation layer is formed to cover the whole substrate, a transparent conductive layer sediments on the passivation layer and is etched to form a hole which is at least overlapped with part of the public electrode lines, the passivation layer and the insulation layer are patterned so that a through hole can be formed below the hole, the through hole penetrates through the passivation layer and the grid insulation layer, part of the public electrode lines are exposed, the transparent conductive layer is removed, and a public electrode is formed on the passivation layer to cover the inner surface of the through hole and is connected with the public electrode lines.
Description
Technical field
The present invention relates to a kind of liquid crystal display, relate in particular to a kind of manufacture method of array base palte of liquid crystal display.
Background technology
As the display mode of liquid crystal display, twisted-nematic (Twisted Nematic, TN) mode was widely used always in the past, but which is in displaying principle, and field angle is existed to restriction.
As the method addressing this problem, Transverse electric-field type has been well-known, for example plane internal switch (In Plane Switching, IPS) mode and fringe field switching (Fringe Field Switching, FFS) mode.This Transverse electric-field type forms pixel electrode and common electrode on array base palte, to applying voltage between this pixel electrode and this common electrode, the electric field that makes it generation and this array base palte almost parallel drives liquid crystal molecule in the face substantially parallel with this array base palte face.
But in the array base palte of the IPS of prior art or FFS type liquid crystal display, public electrode is to be connected with public electrode wire by the through hole in passivation layer.In the processing procedure of this through hole of etching, the size of this through hole is difficult to control, and may make the close together of this pixel electrode and this public electrode, and be short-circuited in a certain place, makes pixel all the time in dark state, causes and in display frame, produces color exception.
Summary of the invention
For this reason, the invention provides a kind of manufacture method of array base palte of liquid crystal display, can control preferably size and the position of passivation layer through hole, to avoid pixel electrode and public electrode to be short-circuited, avoid existing in picture color exception.
According to an aspect of the present invention, provide a kind of manufacture method of array base palte, comprising: on substrate surface, form multiple grids, many gate lines and many public electrode wires; Form one deck gate insulator and cover this substrate, this grid and this public electrode wire; Above this gate insulator, form multiple pixel electrodes; Form one deck passivation layer and cover whole this substrate; Above this passivation layer, deposit layer of transparent conductive layer, and etching forms a perforate, this perforate at least with this public electrode line overlap of part; This passivation layer of patterning and this insulation course, to form a through hole below perforate, this through hole runs through this passivation layer and this gate insulator, and exposes part public electrode wire; Remove this transparency conducting layer; Above this passivation layer, form a public electrode, cover the inside surface of this through hole and be connected with this public electrode wire.
Compared to prior art, according to the manufacture method of array base palte provided by the invention, due to the mask that utilizes layer of transparent conductive layer as passivation layer, can control preferably the size of passivation layer through hole, prevent that public electrode and pixel electrode are short-circuited, therefore, can prevent from having color exception in display frame, improve product quality.
Brief description of the drawings
It in Fig. 1-Fig. 8, is the schematic diagram of manufacture LCD (Liquid Crystal Display) array substrate provided by the invention.
Fig. 9 is the vertical view of LCD (Liquid Crystal Display) array substrate provided by the invention.
Main element symbol description
| Array base palte | 100 |
| Substrate | 10 |
| Grid | 11 |
| Public electrode wire | 12 |
| Gate insulator | 13 |
| Pixel electrode | 14 |
| Channel layer | 15 |
| Source electrode | 16a |
| Drain electrode | 16b |
| Thin film transistor (TFT) | 17 |
| Passivation layer | 18 |
| Through hole | 18a |
| Public electrode | 19 |
| Slit | 19a |
| Transparency conducting layer | 20 |
| Perforate | 20a |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Explain with reference to the accompanying drawings the array base palte for liquid crystal display according to embodiments of the invention.
Referring to figs. 1 through Fig. 8, manufacture the method for LCD (Liquid Crystal Display) array substrate according to the embodiment of the present invention, specifically describe as follows.
As shown in Figure 1, provide a substrate 10, this substrate 10 can be transparent glass substrate.On this substrate, form grid 11, gate line (not shown) and public electrode wire 12.The material of this grid 11, gate line and this public electrode wire 12 is conductive material, as metallic aluminium, copper, molybdenum, but is not limited to this.Better, can be also sandwich construction, as molybdenum aluminium molybdenum structure, molybdenum constructed of aluminium or multilayer aluminum structure, but be not limited to this.
As shown in Figure 2, form a gate insulator 13, cover this substrate 10 and this grid 11, this gate line, this public electrode wire 12.These gate insulator 13 materials are dielectric, such as monox, silicon nitride or silicon oxynitride, but are not limited to this.
Then, on this gate insulator 13, form pixel electrode 14, the material of this pixel electrode 14 can be tin indium oxide (ITO) or indium zinc oxide (IZO), but is not limited to this.This pixel electrode 14 can be planar electrode.
As shown in Figure 3, above this grid 11, form channel layer 15.It should be noted that in order to promote the performance of opening the light, conventionally will form ohmic contact layer (not shown).This ohmic contact layer can optionally be formed on the top of this channel layer 15.This channel layer 15 and this ohmic contact layer are semiconductor material such as amorphous silicon, but are not limited to this.In present embodiment, the semiconductor layer that ohmic contact layer is mixed by severe, as severe is mixed nitrogen ion, channel layer 15 is the semiconductor layer slightly mixing, such as slightly mixing nitrogen ion.
This pixel electrode 14 and this channel layer 15 are all positioned at gate insulator 13 tops, and the present invention also can design and first form channel layer 15, rear formation pixel electrode 14(is not shown in the figures).
As shown in Figure 4, above this channel layer 15, form source electrode 16a, drain electrode 16b and many data line (not shown).The material of this source electrode 16a, this drain electrode 16b and this data line is conductor, such as is metallic aluminium, copper, molybdenum, but is not limited to this.In good embodiment, for example, this conductive material can be sandwich construction, such as molybdenum aluminium molybdenum structure, and molybdenum constructed of aluminium or multilayer aluminum structure, but be not limited to this.Wherein, this source electrode 16a is also separated from one another with the top that this drain electrode 16b is positioned at this channel layer 15, and this drain electrode 16b part covers this pixel electrode 14, is connected with this pixel electrode 14.This source electrode 16a, this drain electrode 16b, this channel layer 15 and this grid 11 have formed thin film transistor (TFT) (TFT) 17.This data line intersects and limits multiple sub-pixel area with this gate line, and each sub-pixel area comprises a TFT17 and a pixel electrode 14.
As shown in Figure 5, form one deck passivation layer 18 and cover whole substrate, this passivation layer 18 is inorganic, such as silicon nitride, or organic material, such as acrylate.
Before patterned passivation layer 18, first deposit layer of transparent conductive layer 20, this transparency conducting layer 20 covers this passivation layer 18.The material of this transparency conducting layer 20 can be tin indium oxide (ITO) or indium zinc oxide (IZO), but is not limited to this.
Utilize the mask (not shown) of these passivation layer 18 correspondences first this transparency conducting layer 20 to be carried out to patterning, to form a perforate 20a above corresponding public electrode wire 12.This perforate 20a is at least overlapping with this public electrode wire 12 of part, and this perforate 20a and this pixel electrode 14 are isolated mutually.
Because the material of this transparent electrode layer 20 is different from the material of this passivation layer 18, this gate insulator 13, applicable etching solution is also different, so, in the process of etch passivation layer 18, can't etch into this transparent electrode layer 20.Therefore this transparent electrode layer 20 that, has a perforate 20a also can be used as the mask of this passivation layer 18 of etching.
As shown in Figure 6, utilize the mask of passivation layer 18 and this transparency conducting layer 20 jointly as mask, to these passivation layer 18 and these gate insulator 13 patternings, to define a through hole 18a.This through hole 18a is positioned at the perforate 20a below of this transparency conducting layer 20, and roughly equal with the size of the perforate 20a of this transparency conducting layer 20.This through hole 18a runs through this passivation layer 18 of part and this gate insulator 13 of part, to expose this public electrode wire 12 of part.
Utilizing this transparency conducting layer 20 is mask, can precisely control the position of this through hole 18a, prevent this through hole 18a skew, can prevent in the process of this through hole of etching 18a simultaneously, cause the etching of crossing of this passivation layer 18 and this gate insulator 13, therefore can prevent that the excessive or each through hole 18a size of this through hole 18a is uneven; Because perforate 20a and the pixel electrode 14 of transparency conducting layer are isolated mutually, this through hole 18a also will isolate mutually with this pixel electrode 14, therefore, the public electrode 19 of this through hole of follow-up filling 18a will can not be short-circuited with pixel electrode 14, prevent from producing in display frame color exception.
As shown in Figure 7, remove this transparency conducting layer 20.Remove the method for this transparency conducting layer 20 for example for using this transparency conducting layer 20 of acid solution etching.
As shown in Figure 8, finally above this passivation layer, form public electrode 19.The material of this public electrode 19 can be tin indium oxide (ITO) or indium zinc oxide (IZO), but is not limited to this.This public electrode 19 comprises multiple slit 19a that are arranged in parallel.This public electrode 19 covers the inside surface of this through hole 18a and is connected with public electrode wire 12.
Fig. 9 is the vertical view of this array base palte 100.As shown in Figure 9, this public electrode 19 comprises multiple slit 19a, and slit 19a is roughly " < " font being arranged in parallel, but is not limited to this.This slit 19a can also be bar shaped or other shapes.
These are only one embodiment of the present of invention, the present invention also can design this pixel electrode 14 and have multiple slits, and this public electrode 19 is planar electrode, does not have slit; Or design this pixel electrode 14 and this public electrode 19 and all there are multiple slits.In other words, at least the one in pixel electrode 14 and public electrode 19 has multiple slits, makes can produce transverse electric field between the two.
By above method, can form the array base palte 100 of liquid crystal display provided by the invention.Liquid crystal display provided by the invention can be IPS type liquid crystal display, or FFS type liquid crystal display.
In a word, the present invention utilizes the mask of layer of transparent conductive layer as passivation layer, can control preferably size and the position of passivation layer through hole, prevent that public electrode and pixel electrode are short-circuited, therefore, can prevent from having color exception in display frame, improve product quality.
Those of ordinary skill in the art should be appreciated that its technical scheme that still can record aforementioned each embodiment modifies, or part technical characterictic is wherein equal to replacement; And these amendments or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a manufacture method for LCD (Liquid Crystal Display) array substrate, the method comprises:
On substrate surface, form multiple grids, many gate lines and many public electrode wires;
Form one deck gate insulator and cover this substrate, this grid, this gate line and this public electrode wire;
Above this gate insulator, form multiple pixel electrodes;
Form one deck passivation layer and cover whole this substrate;
Forms layer of transparent conductive layer and cover this passivation layer, and this transparency conducting layer of patterning to be to form a perforate, this perforate at least with this public electrode line overlap of part;
This passivation layer of patterning and this insulation course, to form a through hole below perforate, this through hole runs through this passivation layer and this gate insulator, and exposes part public electrode wire;
Remove this transparency conducting layer;
Above this passivation layer, form a public electrode, cover the inside surface of this through hole and be connected with this public electrode wire.
2. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 1, is characterized in that: this perforate and this pixel electrode are isolated.
3. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 1, is characterized in that: this transparent electrode layer utilizes the mask of this passivation layer to carry out patterning to form this perforate.
4. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 1, is characterized in that: this passivation layer utilizes the mask of this passivation layer and this transparency conducting layer jointly to carry out patterning to form this through hole as mask.
5. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 1, is characterized in that: the size of this perforate and this through hole is roughly equal.
6. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 1, is characterized in that: the material of this transparency conducting layer is tin indium oxide or indium zinc oxide.
7. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 1, is characterized in that: at least one in this pixel electrode and this public electrode has multiple slits that are arranged in parallel.
8. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 1, is characterized in that: this manufacture method is also included in this grid top and forms one deck channel layer.
9. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 8, it is characterized in that: the both sides that this manufacture method is also included in this channel layer form source electrode separated from one another and drain electrode, this drain electrode part covers this pixel electrode, forms many data lines simultaneously.
10. the manufacture method of LCD (Liquid Crystal Display) array substrate as claimed in claim 9, is characterized in that: this grid, this source electrode, this drain electrode and this channel layer have formed thin film transistor (TFT).
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| CN201310168698.3A CN104122713B (en) | 2013-05-09 | 2013-05-09 | A kind of manufacture method of LCD (Liquid Crystal Display) array substrate |
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| CN201310168698.3A CN104122713B (en) | 2013-05-09 | 2013-05-09 | A kind of manufacture method of LCD (Liquid Crystal Display) array substrate |
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| CN104122713A true CN104122713A (en) | 2014-10-29 |
| CN104122713B CN104122713B (en) | 2017-08-29 |
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| CN105161455A (en) * | 2015-07-31 | 2015-12-16 | 深圳市华星光电技术有限公司 | FFS array substrate manufacturing method thereof, and display device |
| CN105487285A (en) * | 2016-02-01 | 2016-04-13 | 深圳市华星光电技术有限公司 | Array substrate and preparing method of array substrate |
| CN105514032A (en) * | 2016-01-11 | 2016-04-20 | 深圳市华星光电技术有限公司 | Manufacturing method of IPS (In-Plane Switching) type TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array substrate and IPS type TFT-LCD array substrate |
| CN105974690A (en) * | 2016-07-22 | 2016-09-28 | 京东方科技集团股份有限公司 | Mask plate, array substrate, display panel and display device |
| CN106292100A (en) * | 2015-05-28 | 2017-01-04 | 鸿富锦精密工业（深圳）有限公司 | Array base palte and there is the display panels of this array base palte |
| CN106920474A (en) * | 2017-05-11 | 2017-07-04 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display panel and display device |
| JPWO2017150262A1 (en) * | 2016-02-29 | 2018-12-13 | シャープ株式会社 | Liquid crystal display |
| CN109061914A (en) * | 2018-08-07 | 2018-12-21 | 京东方科技集团股份有限公司 | Manufacturing method, display base plate, the display device of display base plate |
| CN110676264A (en) * | 2019-09-09 | 2020-01-10 | 深圳市华星光电技术有限公司 | Pixel electrode contact hole design |
| WO2021146907A1 (en) * | 2020-01-21 | 2021-07-29 | 京东方科技集团股份有限公司 | Array substrate and display panel |
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| CN106292100A (en) * | 2015-05-28 | 2017-01-04 | 鸿富锦精密工业（深圳）有限公司 | Array base palte and there is the display panels of this array base palte |
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| CN106920474A (en) * | 2017-05-11 | 2017-07-04 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display panel and display device |
| CN106920474B (en) * | 2017-05-11 | 2020-02-21 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| CN109061914A (en) * | 2018-08-07 | 2018-12-21 | 京东方科技集团股份有限公司 | Manufacturing method, display base plate, the display device of display base plate |
| CN109061914B (en) * | 2018-08-07 | 2021-08-17 | 京东方科技集团股份有限公司 | Manufacturing method of display substrate, display substrate and display device |
| CN110676264A (en) * | 2019-09-09 | 2020-01-10 | 深圳市华星光电技术有限公司 | Pixel electrode contact hole design |
| CN110676264B (en) * | 2019-09-09 | 2021-11-23 | Tcl华星光电技术有限公司 | Pixel electrode contact hole design |
| WO2021146907A1 (en) * | 2020-01-21 | 2021-07-29 | 京东方科技集团股份有限公司 | Array substrate and display panel |
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