CN203720505U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203720505U CN203720505U CN201320870215.XU CN201320870215U CN203720505U CN 203720505 U CN203720505 U CN 203720505U CN 201320870215 U CN201320870215 U CN 201320870215U CN 203720505 U CN203720505 U CN 203720505U
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Abstract
The embodiment of the utility model provides an array substrate and a display device, and relates to the field of display technology. The array substrate comprises a grid electrode of a TFT (thin film transistor) and a grid insulating layer which are formed on the surface of the transparent substrate in sequence, wherein patterns of a semiconductor active layer, patterns of an etching barrier layer and a source electrode and a drain electrode of the TFT are sequentially formed on the surface of the area, corresponding to the grid electrode of the TFT, of the grid insulating layer, the source electrode and the drain electrode of the TFT are contacted with the patterns of the semiconductor active layer through a via hole, the array substrate also comprises a bucking electrode pattern formed between the grid electrode of the TFT and the transparent substrate, an insulating layer is arranged between the grid electrode of the TFT and the bucking electrode pattern, in the region where the grid electrode faces the source electrode, the area of a grid line is smaller than the area of the source electrode, and/or in the region where the grid electrode faces the drain electrode, the area of the grid line is smaller than the area of the drain electrode. Due to the adoption of the array substrate, parasitic capacitance among the source electrode, the drain electrode and the grid electrode of the TFT can be reduced, and the quality of the display device is improved.
Description
Technical field
The utility model relates to display technique field, relates in particular to a kind of array base palte and display device.
Background technology
Along with TFT-LCD(Thin Film Transistor Liquid Crystal Display, Thin Film Transistor-LCD) development of display technique, various novel semi-conductor elements and the application technology in display device thereof have also obtained tremendous progress thereupon.
In the middle of the manufacture process of existing display panel TFT, increasing manufacturer starts to attempt adopting oxide TFT to replace a-Si(amorphous silicon) TFT or LTPS(low temperature polycrystalline silicon) TFT, to obtaining, there is higher-quality demonstration product.Oxide TFT(is Oxide TFT) backplane technology, a kind of backplane technology close with traditional a-Si TFT processing procedure, this technology is partly replaced as oxide semiconductor material by the silicon semiconductor material that is originally applied to a-Si TFT, as the IGZO being most widely used now (Indium Gallium Zinc Oxide, indium gallium zinc oxide) material, forms the semiconductor active layer of TFT.In prior art, the array base-plate structure of a kind of typical oxide TFT as shown in Figure 1, comprise grid 11, the gate insulation layer 12 of the TFT that is formed on successively transparency carrier 10 surfaces and the oxide semiconductor active layer 13 being formed by IGZO, the surface of semiconductor active layer 13 is formed with the etching barrier layer 14 with via hole by composition technique, via hole A, B run through respectively etching barrier layer 14, to expose the semiconductor active layer 13 of bottom, the source electrode 151 of TFT and drain electrode 152 are respectively by via hole A, B and semiconductor active layer 13 conductings.
Adopt oxide TFT to there is preparation temperature requirement with respect to a-Si TFT low, the advantages such as mobility height, this technology can be applicable to that high frequency shows and high resolving power shows product, and with respect to LTPS TFT technology, has that equipment investment cost is low, operation guarantee low cost and other advantages.But its weak point is, in oxide tft array substrate as shown in Figure 1, the source electrode 151 of TFT and drain electrode 152 have one section of long overlapping region with grid 11 respectively, so, the in the situation that of energising, owing to producing stray capacitance Cgs between the source electrode 151 of level difference TFT and grid 11, in like manner between the drain electrode 152 of TFT and grid 11, also will produce stray capacitance Cgd, at grid line 11, pass through the moment of Control of Voltage TFT switch, existence due to stray capacitance, voltage signal when TFT closes on the grid line 11 variation from high to low 152 corresponding output leaping voltages that can make to drain, thereby cause the unexpected reduction of liquid crystal voltage in pixel, this will have a strong impact on the accuracy of pixel electrode voltage, make display frame flicker.
Utility model content
Embodiment of the present utility model provides a kind of array base palte and display device, can reduce the stray capacitance between source, drain electrode and the grid of TFT, improves the quality of display device.
The one side of the utility model embodiment, a kind of array base palte is provided, comprise: the grid and the gate insulation layer that are formed on successively the TFT on transparency carrier surface, on the surface of the area of grid of the corresponding described TFT of described gate insulation layer, be formed with successively source electrode and the drain electrode of the pattern of semiconductor active layer, the pattern of etching barrier layer and described TFT, the source electrode of described TFT and drain electrode contact with the pattern of described semiconductor active layer by via hole respectively; It is characterized in that, also comprise:
Be formed on the grid of described TFT and the guarded electrode pattern between described transparency carrier, between the grid of described TFT and described guarded electrode pattern, there is insulation course;
Region at described grid in the face of described source electrode, the area of described grid line is less than the area of described source electrode; And/or at described grid in the face of the region of described drain electrode, the area of described grid line is less than the area of described drain electrode.
Further, described array base palte also comprises:
Be formed on the first transparency electrode of the patterned surfaces of described etching barrier layer, described the first transparency electrode contacts with the drain electrode of described TFT;
Be formed on the pattern of the passivation layer on described the first transparency electrode surface, TFT region described in the pattern covers of described passivation layer;
Be formed on the second transparency electrode of described passivation layer surface.
Wherein, described the first transparency electrode is pixel electrode, and described the second transparency electrode is public electrode;
And described the first transparency electrode is planar structure, described the second transparency electrode is spaced list structure.
Further, described insulation course adopts organic resin material to make.
In the utility model embodiment, the pattern of described semiconductor active layer adopts the transparent metal oxide material that is characteristic of semiconductor to make.
On the other hand, the utility model embodiment also provides a kind of display device, and described display device can comprise array base palte as above.
A kind of like this array base palte and display device that the utility model embodiment provides, by guarded electrode pattern is set between the grid at TFT and transparency carrier, and between the grid of TFT and guarded electrode pattern, insulation course is set, wherein at grid, face the region of source electrode, the area of grid line is less than the area of source electrode; And/or at grid, face the region draining, the area of grid line is less than the area of drain electrode.Like this because the overlapping region area between parallel plate capacitor two electrodes reduces, capacitance is obviously reduced, thereby can effectively reduce the stray capacitance Cgd existing between the stray capacitance Cgs that exists between the source electrode of TFT and grid and/or the drain electrode that reduces TFT and grid.In addition the electric capacity forming between guarded electrode pattern and the grid of TFT, can shield formed electric capacity between the source-drain electrode of TFT in this region and grid to a great extent.Therefore, according to the utility model, can avoid the output leaping voltage that produces because stray capacitance is excessive bad, effectively improve display frame flicker, improve the quality of display device.
Particularly, the overlapping area of establishing grid and source electrode is a, and the overlapping area of grid and drain electrode is b, Cgs+Cgd=(a+b)/d1, and wherein d1 is the vertical range between grid and source electrode or drain electrode.If the overlapping area of guarded electrode pattern and source electrode is c, the overlapping area of guarded electrode pattern and drain electrode is d, and the vertical range between guarded electrode pattern and source electrode or drain electrode is d2, the electric capacity being formed by guarded electrode pattern can be divided into two parts, with producing capacitor C 1 between the overlapping region of grid and grid, then C1 connects with Cgs+Cgd, makes total capacitance Ct1 further be less than Cgs+Cgd; With the not overlapping region of grid and source electrode with between draining, produce capacitor C 2, C2=(c+d-a-b)/d2.Between total capacitance Ct1 and capacitor C 2, form relation in parallel, again due to Ct1<Cgs+Cgd=(a+b)/d1, and d1<d2, so Ct1+C2< (a+b)/d1+ (c+d-a-b)/d2< (c+d)/d1.And Cgs+Cgd=of the prior art (c+d)/d1, so known by above analysis, according to the utility model, can reduce stray capacitance.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of a kind of array base palte in prior art;
The structural representation of a kind of array base palte that Fig. 2 provides for the utility model embodiment;
The schematic flow sheet of a kind of manufacturing method of array base plate that Fig. 3 provides for the utility model embodiment;
The schematic flow sheet of another manufacturing method of array base plate that Fig. 4 provides for the utility model embodiment;
Fig. 5 is for forming board structure partial top view after guarded electrode pattern and A-A thereof to cut-open view;
Fig. 6 is for forming the board structure schematic diagram after insulation course;
Fig. 7 is for forming board structure partial top view after the grid of TFT and B-B thereof to cut-open view;
Fig. 8 is for forming the board structure schematic diagram after gate insulation layer;
Fig. 9 is for forming board structure partial top view after semiconductor active layer and C-C thereof to cut-open view;
Figure 10 is for forming board structure partial top view after etching barrier layer and D-D thereof to cut-open view;
The source electrode that Figure 11 is formation TFT and the board structure partial top view after drain electrode and E-E thereof are to cut-open view;
Figure 12 is for forming board structure partial top view after the first transparency electrode and F-F thereof to cut-open view.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The array base palte that the utility model embodiment provides, as shown in Figure 2, comprise: the grid 21 and the gate insulation layer 22 that are formed on successively the TFT on transparency carrier 20 surfaces, on the surface in grid 21 regions of gate insulation layer 22 corresponding described TFT, be formed with successively source electrode 251 and the drain electrode 252 of the pattern 23 of semiconductor active layer, the pattern 24 of etching barrier layer and described TFT, the source electrode 251 of described TFT and drain electrode 252 contact with the pattern 23 of semiconductor active layer by via hole (in Fig. 2 shown in dotted line frame) respectively.Further, also comprise:
Be formed on the grid 21 of TFT and the guarded electrode pattern 26 between transparency carrier 20, between the grid 21 of TFT and guarded electrode pattern 26, there is insulation course 27.
Wherein, guarded electrode pattern 26 can adopt various conductive materials, is formed on the surface of transparency carrier 20 by composition technique.Guarded electrode pattern 26 can shelter from the light from backlight, avoids illumination to be mapped to the raceway groove of TFT, therefore can avoid the change of the TFT volt-ampere characteristic that causes due to irradiation, has effectively prevented the rising of element cut-off current IOFF.
Region at grid 21 in the face of source electrode 251, the area of grid line (not shown in Fig. 2) is less than the area of source electrode 251; And/or at grid 21 region in the face of drain electrode 252, area guarded electrode pattern 26 length along grid line direction that the area of grid line is less than drain electrode 252 are less than the length of the grid 21 of TFT.
A kind of like this array base palte that the utility model embodiment provides, by guarded electrode pattern is set between the grid at TFT and transparency carrier, and between the grid of TFT and guarded electrode pattern, insulation course is set, and the region in the face of source electrode at grid wherein, the area of grid line is less than the area of source electrode; And/or at grid, face the region draining, the area of grid line is less than the area of drain electrode.Like this because the overlapping region area between parallel plate capacitor two electrodes reduces, capacitance is obviously reduced, thereby can effectively reduce the stray capacitance Cgd existing between the stray capacitance Cgs that exists between the source electrode of TFT and grid and/or the drain electrode that reduces TFT and grid.In addition the electric capacity forming between guarded electrode pattern and the grid of TFT, can shield formed electric capacity between the source-drain electrode of TFT in this region and grid to a great extent.Therefore, according to the utility model, can avoid the output leaping voltage that produces because stray capacitance is excessive bad, effectively improve display frame flicker, improve the quality of display device.
Particularly, as shown in Figure 2, the overlapping area of establishing grid and source electrode is a, and the overlapping area of grid and drain electrode is b, Cgs+Cgd=(a+b)/d1, and wherein d1 is the vertical range between grid and source electrode or drain electrode.If the overlapping area of guarded electrode pattern and source electrode is c, the overlapping area of guarded electrode pattern and drain electrode is d, and the vertical range between guarded electrode pattern and source electrode or drain electrode is d2, the electric capacity being formed by guarded electrode pattern can be divided into two parts, with producing capacitor C 1 between the overlapping region of grid and grid, then C1 connects with Cgs+Cgd, makes total capacitance Ct1 further be less than Cgs+Cgd; With the not overlapping region of grid and source electrode with between draining, produce capacitor C 2, C2=(c+d-a-b)/d2.Between total capacitance Ct1 and capacitor C 2, form relation in parallel, again due to Ct1<Cgs+Cgd=(a+b)/d1, and d1<d2, so Ct1+C2< (a+b)/d1+ (c+d-a-b)/d2< (c+d)/d1.And Cgs+Cgd=of the prior art (c+d)/d1, so known by above analysis, according to the utility model, can reduce stray capacitance.
It should be noted that, guarded electrode pattern 26 overlay areas can be selected according to actual conditions.In the situation that not affecting aperture opening ratio, guarded electrode pattern 26 can covering source-drain electrode as much as possible and the overlapping region of grid.Known according to parallel plate capacitor formula C=ε S/d, in order to reduce the capacitance between parallel pole, when other conditions are constant, can realize reducing of electric capacity by reducing overlapping region area between two electrodes.In the utility model embodiment, in order to effectively reduce the stray capacitance between TFT source-drain electrode and grid, the electric capacity forming between guarded electrode pattern and the grid of TFT can shield formed electric capacity between the source-drain electrode of TFT in this region and grid to a great extent, thereby can significantly reduce the grid of TFT and the electrode overlapping region area between source-drain electrode, thereby can effectively reduce the impact of the leaping voltage that stray capacitance produces.
In the utility model embodiment, insulation course 27 can adopt the materials such as organic resin material with good insulation properties to make, in the process of practical application, the thickness of insulation course 27 can be selected according to actual needs, and the utility model does not limit this.
It should be noted that, the TFT-LCD array base palte that the utility model embodiment provides goes for FFS(Fringe Field Switching, fringe field switching) type, AD-SDS(Advanced-Super Dimensional Switching, referred to as ADS, senior super dimension field switch) type, IPS(In Plane Switch, transverse electric field effect) type, TN(Twist Nematic, the twisted-nematic) production of the liquid crystal indicator of the type such as type.Wherein, ADS technology is by the longitudinal electric field formation multi-dimensional electric field of the parallel electric field that in same plane, pixel electrode edge produces and pixel electrode layer and the generation of public electrode interlayer, make in liquid crystal cell between pixel electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation conversion, thereby to have improved planar orientation be liquid crystal work efficiency and increased light transmission efficiency.
Above-mentioned which kind of liquid crystal indicator all comprises color membrane substrates and the array base palte that box is shaped.Different, the public electrode of TN type display device is arranged on color membrane substrates, and pixel electrode is arranged on array base palte; Public electrode and the pixel electrode of FFS type display device, ADS type display device and IPS type display device are all arranged on array base palte.
Concrete, as shown in Figure 2, in the utility model embodiment, be to take the explanation that FFS type display device carries out as example.Wherein, array base palte can also comprise:
Be formed on first transparency electrode 281 on pattern 24 surfaces of etching barrier layer, this first transparency electrode 281 contacts with the drain electrode 252 of TFT.
Be formed on the pattern 29 of the passivation layer on the first transparency electrode 281 surfaces, the pattern 29 of this passivation layer covers TFT region.
And the second transparency electrode 282 that is formed on this passivation layer surface.
Wherein, the first transparency electrode 281 can be pixel electrode, and the second transparency electrode 282 can be public electrode, and this first transparency electrode 281 can be planar structure, and the second transparency electrode 282 can be spaced list structure.
In the array base palte of described FFS type display device, the different layer of described public electrode and described pixel electrode arranges, and optional, the electrode that is positioned at upper strata comprises a plurality of strip electrodes, and the electrode that is positioned at lower floor can comprise a plurality of strip electrodes or for plate shaped.In the utility model embodiment, be the electrode that is positioned at lower floor be that plate shaped planar structure is the explanation that example is carried out.Wherein, different layer arranges at least two kinds of patterns, and at least two kinds of different layer settings of pattern refer to, at least double-layer films forms at least two kinds of patterns by composition technique respectively.For two kinds of different layer settings of pattern, refer to, by composition technique, by double-layer films, respectively form a kind of pattern.For example, the different layer setting of public electrode and pixel electrode refers to: by ground floor transparent conductive film, by composition technique, form lower electrode, by second layer transparent conductive film, by composition technique, form upper electrode, wherein, lower electrode is public electrode (or pixel electrode), and upper electrode is pixel electrode (or public electrode).
The array base palte of a kind of like this structure that the utility model embodiment provides goes for IPS type display device equally, different from FFS type display device is, described public electrode and described pixel electrode arrange with layer, described public electrode comprises a plurality of the first strip electrodes, described pixel electrode comprises a plurality of the second strip electrodes, and described the first strip electrode and described the second bar shaped electrode gap arrange.Wherein, with layer, arrange at least two kinds of patterns; At least two kinds of patterns refer to layer setting: same film is formed at least two kinds of patterns by composition technique.For example, public electrode and pixel electrode refer to layer setting: by same transparent conductive film, by composition technique, form pixel electrode and public electrode.Wherein, pixel electrode refers to the electrode for example, being electrically connected to data line by switch element (, can be thin film transistor (TFT)), and public electrode refers to the electrode being electrically connected to public electrode wire.
It should be noted that, in the utility model embodiment, the pattern 23 of semiconductor active layer can adopt the transparent metal oxide material that is characteristic of semiconductor to make.For example, metal-oxide film can comprise: IGZO(indium gallium zinc oxide), IGO(indium gallium oxide), ITZO(indium tin zinc oxide), AlZnO(aluminium zinc oxide) at least one.Adopt a kind of like this transparent metal oxide material to replace a-Si(amorphous silicon) or LTPS(low temperature polycrystalline silicon) semiconductor active layer of TFT formed, with respect to a-Si TFT or LTPS TFT, there is preparation temperature requirement low, the advantages such as mobility height, this technology can be applicable to that high frequency shows and high resolving power shows product, and with respect to LTPS TFT technology, has that equipment investment cost is low, operation guarantee low cost and other advantages.
The display device that the utility model embodiment provides, comprises array base palte as above.
This array base palte specifically comprises and is formed on the grid of TFT and the guarded electrode pattern between transparency carrier to have insulation course between the grid of TFT and guarded electrode pattern; Guarded electrode pattern is less than the length of the grid of described TFT along the length of grid line direction.
It should be noted that display device provided by the utility model can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone, panel computer.
A kind of like this display device that the utility model embodiment provides, comprise array base palte, this array base palte is by arranging guarded electrode pattern between the grid at TFT and transparency carrier, and between the grid of TFT and guarded electrode pattern, insulation course is set, wherein at grid, face the region of source electrode, the area of grid line is less than the area of source electrode; And/or at grid, face the region draining, the area of grid line is less than the area of drain electrode.Like this because the overlapping region area between parallel plate capacitor two electrodes reduces, capacitance is obviously reduced, thereby can effectively reduce the stray capacitance Cgd existing between the stray capacitance Cgs that exists between the source electrode of TFT and grid and/or the drain electrode that reduces TFT and grid.In addition the electric capacity forming between guarded electrode pattern and the grid of TFT, can shield formed electric capacity between the source-drain electrode of TFT in this region and grid to a great extent.Therefore, according to the utility model, can avoid the output leaping voltage that produces because stray capacitance is excessive bad, effectively improve display frame flicker, improve the quality of display device.
The utility model embodiment also provides a kind of manufacturing method of array base plate, and the method as shown in Figure 3, comprising:
S301, on the surface of transparency carrier, by composition PROCESS FOR TREATMENT, form guarded electrode pattern.
Wherein, guarded electrode pattern can adopt various conductive materials, is formed on the surface of transparency carrier by composition technique.
S302, at the substrate surface that is being formed with guarded electrode pattern, form insulation course.
In the utility model embodiment, insulation course 27 can adopt the materials such as organic resin material with good insulation properties to make, in the process of practical application, the thickness of insulation course 27 can be selected according to actual needs, and the utility model does not limit this.
S303, on the surface of insulation course, corresponding guarded electrode pattern position place forms the grid of TFT by composition PROCESS FOR TREATMENT, the region at grid in the face of source electrode, and the area of grid line is less than the area of source electrode; And/or at grid, face the region draining, the area of grid line is less than the area of drain electrode.
A kind of like this manufacturing method of array base plate that the utility model embodiment provides, by guarded electrode pattern is set between the grid at TFT and transparency carrier, and between the grid of TFT and guarded electrode pattern, insulation course is set, wherein at grid, face the region of source electrode, the area of grid line is less than the area of source electrode; And/or at grid, face the region draining, the area of grid line is less than the area of drain electrode.Like this because the overlapping region area between parallel plate capacitor two electrodes reduces, capacitance is obviously reduced, thereby can effectively reduce the stray capacitance Cgd existing between the stray capacitance Cgs that exists between the source electrode of TFT and grid and/or the drain electrode that reduces TFT and grid.In addition the electric capacity forming between guarded electrode pattern and the grid of TFT, can shield formed electric capacity between the source-drain electrode of TFT in this region and grid to a great extent.Therefore, according to the utility model, can avoid the output leaping voltage that produces because stray capacitance is excessive bad, effectively improve display frame flicker, improve the quality of display device.
It should be noted that, guarded electrode pattern covers region can be selected according to actual conditions.In the situation that not affecting aperture opening ratio, guarded electrode pattern can covering source-drain electrode as much as possible and the overlapping region of grid.Known according to parallel plate capacitor formula C=ε S/d, in order to reduce the capacitance between parallel pole, when other conditions are constant, can realize reducing of electric capacity by reducing overlapping region area between two electrodes.In the utility model embodiment, in order to effectively reduce the stray capacitance between TFT source-drain electrode and grid, the electric capacity forming between guarded electrode pattern and the grid of TFT can shield formed electric capacity between the source-drain electrode of TFT in this region and grid to a great extent, thereby can significantly reduce the grid of TFT and the electrode overlapping region area between source-drain electrode, thereby can effectively reduce the impact of the leaping voltage that stray capacitance produces.
Further, the manufacturing method of array base plate that the utility model embodiment provides, as shown in Figure 4, specifically comprises:
S401, on the surface of transparency carrier, by composition PROCESS FOR TREATMENT, form guarded electrode pattern.
In the middle of the actual production process of array base palte, transparency carrier can be specifically that the transparent material that adopts glass or transparent resin etc. to have certain soundness is made.On transparency carrier, need to adopt a composition technique to form guarded electrode pattern.
For example, can be first at surface deposition one deck of transparency carrier, there is certain thickness metal material, by thering is the mask of specific pattern, carry out the final guarded electrode pattern 26 forming as shown in Figure 5 of exposure imaging.
S402, at the substrate surface that is being formed with guarded electrode pattern, form insulation course.
For example, can apply one deck on the surface that is formed with the substrate of guarded electrode pattern and there is certain thickness organic resin material, as shown in Figure 6, to form insulation course 27.This insulation course 27 will cover guarded electrode pattern 26 completely.
S403, on the surface of insulation course, corresponding guarded electrode pattern position place forms the grid of TFT by composition PROCESS FOR TREATMENT, the region at grid in the face of source electrode, and the area of grid line is less than the area of source electrode; And/or at grid, face the region draining, the area of grid line is less than the area of drain electrode.
Wherein, the area of grid line 210 is as shown in Fig. 7 bend part.
For example, can adopt plasma reinforced chemical vapour deposition (PECVD), magnetron sputtering, thermal evaporation or other film build method being formed with on the substrate of insulation course, form metal level.Wherein, this metal level can be the single thin film that the metals such as molybdenum, aluminium, aluminium rubidium alloy, tungsten, chromium, copper form, and can be also the multilayer film that above metallic multilayer forms.Surface at this metal level is formed with photoresist, by having, the mask plate of specific pattern carries out exposure imaging so that photoresist produces pattern, peel off the metal level that does not cover photoresist place, finally on the surface of insulation course, form the grid 21 of TFT, its structure can be as shown in Fig. 7 vertical view, can see, in as Fig. 7, B-B is in cut-open view, and the length of the grid 21 of TFT is greater than guarded electrode pattern 26.
S404, on the surface of substrate that is formed with the grid of TFT, form gate insulation layer.
As shown in Figure 8, visible, on the surface of substrate of pattern 26 that is formed with the first insulation course, be formed with the gate insulation layer 22 of thickness homogeneous.
S405, on the surface of the area of grid of the corresponding TFT of gate insulation layer, by composition PROCESS FOR TREATMENT, form the pattern of semiconductor active layer.
For example, can form the semiconductor active layer with characteristic of semiconductor at the substrate surface that is formed with said structure, by mask exposure, form the pattern 23 of the semiconductor active layer as shown in Fig. 9 vertical view.
It should be noted that, in the utility model embodiment, the pattern 23 of semiconductor active layer can adopt the transparent metal oxide material that is characteristic of semiconductor to make.For example, metal-oxide film can comprise: at least one in IGZO, IGO, ITZO, AlZnO.Adopt a kind of like this transparent metal oxide material to replace a-Si(amorphous silicon) or LTPS(low temperature polycrystalline silicon) semiconductor active layer of TFT formed, with respect to a-Si TFT or LTPSTFT, there is preparation temperature requirement low, the advantages such as mobility height, this technology can be applicable to that high frequency shows and high resolving power shows product, and with respect to LTPS TFT technology, has that equipment investment cost is low, operation guarantee low cost and other advantages.
S406, on the surface of the pattern of semiconductor active layer, by composition PROCESS FOR TREATMENT, form the pattern of the etching barrier layer with via hole.
The pattern 24 of etching barrier layer can be if D-D in Figure 10 be to as shown in cut-open view, concrete, can be by being formed with coating or deposition-etch restraining barrier on the substrate of said structure, by thering is the mask exposure of specific pattern, finally at the source electrode of corresponding TFT and the position of drain electrode, form respectively via hole, the bottom of via hole is the pattern 23 of semiconductor active layer, thereby obtains the pattern 24 of etching barrier layer.
S407, on the surface of the pattern of etching barrier layer, form source electrode and the drain electrode of TFT by composition PROCESS FOR TREATMENT, the source electrode of this TFT and drain electrode contact with the pattern of semiconductor active layer by via hole respectively.
The source electrode 251 that is formed with TFT can be as shown in figure 11 with the board structure of drain electrode 252.
Concrete, the region at grid 21 in the face of source electrode 251, the area of grid line 210 is less than the area of source electrode 251; And/or at grid 21 region in the face of drain electrode 252, the area of grid line 210 is less than the area of drain electrode 252.Wherein, the area of grid line 210 can significantly see with reference to shown in figure 7 from Figure 11, at grid 21 in the face of source electrode 251 or in the face of the region of drain electrode 252, the area of grid line 210 is less than the area of source electrode 251 or drain electrode 252.
S408, on the surface of etching barrier layer, by composition PROCESS FOR TREATMENT, form the first transparency electrode, this first transparency electrode contacts with the drain electrode of TFT.
The board structure that is formed with the first transparency electrode 281 can be as shown in figure 12.
S409, on the surface of the first transparency electrode, by composition PROCESS FOR TREATMENT, form the pattern of passivation layer, the pattern covers TFT region of this passivation layer.
S410, on the surface of passivation layer, by composition PROCESS FOR TREATMENT, form the second transparency electrode.Thereby the final array base palte forming as shown in Figure 2.
Particularly, as shown in figure 11, the overlapping area of establishing grid and source electrode is a, and the overlapping area of grid and drain electrode is b, Cgs+Cgd=(a+b)/d1, and wherein d1 is the vertical range (as shown in Figure 2) between grid and source electrode or drain electrode.If the overlapping area of guarded electrode pattern and source electrode is c, the overlapping area of guarded electrode pattern and drain electrode is d, and guarded electrode pattern and source electrode or drain electrode between vertical range be d2(as shown in Figure 2), the electric capacity being formed by guarded electrode pattern can be divided into two parts, with producing capacitor C 1 between the overlapping region of grid and grid, then C1 connects with Cgs+Cgd, makes total capacitance Ct1 further be less than Cgs+Cgd; With the not overlapping region of grid and source electrode with between draining, produce capacitor C 2, C2=(c+d-a-b)/d2.Between total capacitance Ct1 and capacitor C 2, form relation in parallel, again due to Ct1<Cgs+Cgd=(a+b)/d1, and d1<d2, so Ct1+C2< (a+b)/d1+ (c+d-a-b)/d2< (c+d)/d1.And Cgs+Cgd=of the prior art (c+d)/d1, so known by above analysis, according to the utility model, can reduce stray capacitance.
It should be noted that, be to take the explanation that FFS type display device carries out as example in the utility model embodiment.Wherein, the first transparency electrode 281 can be pixel electrode, and the second transparency electrode 282 can be public electrode, and this first transparency electrode 281 can be planar structure, and the second transparency electrode 282 can be spaced list structure.
In the array base palte of described FFS type display device, the different layer of described public electrode and described pixel electrode arranges, and optional, the electrode that is positioned at upper strata comprises a plurality of strip electrodes, and the electrode that is positioned at lower floor can comprise a plurality of strip electrodes or for plate shaped.In the utility model embodiment, be the electrode that is positioned at lower floor be that plate shaped planar structure is the explanation that example is carried out.Wherein, different layer arranges at least two kinds of patterns, and at least two kinds of different layer settings of pattern refer to, at least double-layer films forms at least two kinds of patterns by composition technique respectively.For two kinds of different layer settings of pattern, refer to, by composition technique, by double-layer films, respectively form a kind of pattern.For example, the different layer setting of public electrode and pixel electrode refers to: by ground floor transparent conductive film, by composition technique, form lower electrode, by second layer transparent conductive film, by composition technique, form upper electrode, wherein, lower electrode is public electrode (or pixel electrode), and upper electrode is pixel electrode (or public electrode).
The array base palte of a kind of like this structure that the utility model embodiment provides goes for the production of the various display device array base paltes such as ADS type display device, IPS type display device or TN type display device equally.Can expect, when the position of pixel electrode or public electrode or shape and structure change, by changing the correlation step in above-mentioned operation, can realize equally the production of various array of structures substrates, in the utility model embodiment, this not enumerated.
Adopt above-mentioned manufacturing method of array base plate, the electric capacity forming between guarded electrode pattern and the grid of TFT can shield formed electric capacity between the source-drain electrode of TFT in this region and grid to a great extent, thereby can significantly reduce the grid of TFT and the electrode overlapping region area between source-drain electrode, like this because the overlapping region area between parallel plate capacitor two electrodes reduces, capacitance is obviously reduced, thereby can effectively reduce the stray capacitance Cgd existing between the stray capacitance Cgs that exists between the source electrode of TFT and grid or the drain electrode that reduces TFT and grid, and then avoid the output leaping voltage that produces because stray capacitance is excessive bad, effectively improve display frame flicker, improve the quality of display device.
The above; it is only embodiment of the present utility model; but protection domain of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, within all should being encompassed in protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of described claim.
Claims (6)
1. an array base palte, comprise: the grid and the gate insulation layer that are formed on successively the TFT on transparency carrier surface, on the surface of the area of grid of the corresponding described TFT of described gate insulation layer, be formed with successively source electrode and the drain electrode of the pattern of semiconductor active layer, the pattern of etching barrier layer and described TFT, the source electrode of described TFT and drain electrode contact with the pattern of described semiconductor active layer by via hole respectively; It is characterized in that, also comprise:
Be formed on the grid of described TFT and the guarded electrode pattern between described transparency carrier, between the grid of described TFT and described guarded electrode pattern, there is insulation course;
Region at described grid in the face of described source electrode, the area of grid line is less than the area of described source electrode; And/or at described grid in the face of the region of described drain electrode, the area of described grid line is less than the area of described drain electrode.
2. array base palte according to claim 1, is characterized in that, described array base palte also comprises:
Be formed on the first transparency electrode of the patterned surfaces of described etching barrier layer, described the first transparency electrode contacts with the drain electrode of described TFT;
Be formed on the pattern of the passivation layer on described the first transparency electrode surface, TFT region described in the pattern covers of described passivation layer;
Be formed on the second transparency electrode of described passivation layer surface.
3. array base palte according to claim 2, is characterized in that, described the first transparency electrode is pixel electrode, and described the second transparency electrode is public electrode;
And described the first transparency electrode is planar structure, described the second transparency electrode is spaced list structure.
4. array base palte according to claim 1, is characterized in that, described insulation course adopts organic resin material to make.
5. according to the arbitrary described array base palte of claim 1-4, it is characterized in that, the pattern of described semiconductor active layer adopts the transparent metal oxide material that is characteristic of semiconductor to make.
6. a display device, is characterized in that, described display device comprises the array base palte as described in as arbitrary in claim 1-5.
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| CN201320870215.XU CN203720505U (en) | 2013-12-26 | 2013-12-26 | Array substrate and display device |
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| CN201320870215.XU CN203720505U (en) | 2013-12-26 | 2013-12-26 | Array substrate and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103728803A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN107092124A (en) * | 2017-05-11 | 2017-08-25 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN110600484A (en) * | 2019-08-30 | 2019-12-20 | 南京中电熊猫平板显示科技有限公司 | Self-luminous array substrate and manufacturing method thereof |
| CN115377115A (en) * | 2021-05-20 | 2022-11-22 | 夏普显示科技株式会社 | Active matrix substrate and liquid crystal display device |
-
2013
- 2013-12-26 CN CN201320870215.XU patent/CN203720505U/en not_active Withdrawn - After Issue
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103728803A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103728803B (en) * | 2013-12-26 | 2015-04-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2015096396A1 (en) * | 2013-12-26 | 2015-07-02 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, and display device |
| US9620524B2 (en) | 2013-12-26 | 2017-04-11 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display device |
| CN107092124A (en) * | 2017-05-11 | 2017-08-25 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| WO2018205620A1 (en) * | 2017-05-11 | 2018-11-15 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| US11574934B2 (en) | 2017-05-11 | 2023-02-07 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same, and display device |
| CN110600484A (en) * | 2019-08-30 | 2019-12-20 | 南京中电熊猫平板显示科技有限公司 | Self-luminous array substrate and manufacturing method thereof |
| CN115377115A (en) * | 2021-05-20 | 2022-11-22 | 夏普显示科技株式会社 | Active matrix substrate and liquid crystal display device |
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