CN105448823A - Oxide thin film transistor array base plate and manufacturing method and liquid crystal display panel - Google Patents

Oxide thin film transistor array base plate and manufacturing method and liquid crystal display panel Download PDF

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CN105448823A
CN105448823A CN201511000256.3A CN201511000256A CN105448823A CN 105448823 A CN105448823 A CN 105448823A CN 201511000256 A CN201511000256 A CN 201511000256A CN 105448823 A CN105448823 A CN 105448823A
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layer
region
thin film
film transistor
electrode
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CN201511000256.3A
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邹忠飞
李海波
郑会龙
何钰莹
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昆山龙腾光电有限公司
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An oxide thin film transistor array base plate and a manufacturing method thereof, comprising: manufacturing an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer comprising a first region, a second region and a third region; manufacturing a grid electrode and a grid electrode insulation layer forming the oxide thin film transistor on the oxide semiconductor layer, wherein the grid electrode insulation layer covers the first region of the oxide semiconductor layer; carrying out ion injection to the second region and the third region of the oxide semiconductor layer on the premise that the first region is covered by the oxide semiconductor layer, respectively converting the second region and the third region from semiconductors into a first electrode and a second electrode, wherein the second electrode is taken as a pixel electrode, the semiconductor property of the first region of the oxide semiconductor layer is kept, the first region is taken as the groove region of the oxide thin film transistor; forming a first passivation layer on the susbtrate, forming a data wire on the first passivation layer, wherein the data wire is filled in the through hole of the first passivation layer and is electrically connected with the first electrode.

Description

氧化物薄膜晶体管阵列基板及制作方法与液晶显示面板 Oxide thin film transistor array substrate and a method for manufacturing the liquid crystal display panel

技术领域 FIELD

[0001]本发明涉及液晶显示的技术领域,特别涉及一种氧化物薄膜晶体管阵列基板及制作方法,以及具有该氧化物薄膜晶体管阵列基板的液晶显示面板。 [0001] The present invention relates to the technical field of liquid crystal display, and particularly relates to an oxide thin film transistor array substrate and a fabrication method, a liquid crystal and a thin film transistor array substrate of the display panel oxide.

背景技术 Background technique

[0002] 随着显示技术的发展,液晶显示面板(Liquid Crystal Display,LCD)因其轻便、低辐射等优点越来越受到人们的欢迎。 [0002] With the development of display technology, liquid crystal display panels (Liquid Crystal Display, LCD) because of its lightweight, low radiation, etc. more and more popular. 液晶显示面板包括对置的彩色滤光片基板(colorfilter,CF)和薄膜晶体管阵列基板(TFT array)以及夹置在两者之间的液晶层(LClayer)。 The liquid crystal display panel includes a color filter substrate opposed (colorfilter, CF) and a thin film transistor array substrate (TFT array) and a liquid crystal layer (LClayer) sandwiched therebetween.

[0003]非晶硅(a-Si)是目前普遍用于制作阵列基板上薄膜晶体管(TFT)的半导体层材料,但非晶硅由于存在因自身缺陷而导致的电子迀移率低、稳定性差等问题,使它在显示领域的运用受到了限制。 [0003] The amorphous silicon (a-Si) is commonly used semiconductor material layer on a thin film transistor array substrate (TFT), but due to the amorphous silicon due to the presence of an electron Gan own shortcomings resulting shift rate, poor stability and other issues, the use of it in the display area is limited. 随着显示面板的分辨率不断提高,非晶硅薄膜晶体管已经无法满足高分辨率显示面板的正常充电需求,为解决此问题,高电子迀移率的氧化物薄膜晶体管替代非晶硅薄膜晶体管诞生。 With the resolution of the display panel is ever increasing, amorphous silicon thin film transistor has been unable to meet the demand for high-resolution display panel of the normal charge, in order to solve this problem, the oxide thin film transistor high rate of alternative electronic Gan shift amorphous silicon thin film transistor birth . 氧化物薄膜晶体管(oxide TFT)是指半导体沟道采用氧化物半导体制备的薄膜晶体管,氧化物半导体层材料的典型代表有IGZ0(Indium Gallium ZincOxide,铟镓锌氧化物)、ITZ0(Indium Tin Zinc Oxide,铟锡锌氧化物)等。 Oxide thin film transistor (oxide TFT) refers to a semiconductor channel thin film transistor prepared in an oxide semiconductor, the oxide semiconductor layer material typical are IGZ0 (Indium Gallium ZincOxide, indium gallium zinc oxide), ITZ0 (Indium Tin Zinc Oxide , indium tin zinc oxide) and the like. 由于氧化物半导体具备电子迀移率高、工艺温度低、光透过性高等特点,因此成为目前薄膜晶体管显示领域的研究热点之一。 Since the oxide semiconductor includes an electronic Gan shift rate, process temperature is low, and high light transmission, and therefore one of the thin film transistor display become a hot topic.

[0004]在制备薄膜晶体管阵列基板时,如果利用传统的背沟道蚀刻(back channeletched,BCE)方式制作薄膜晶体管,在沟道处进行湿蚀刻(wet etching)制作源极和漏极时会对沟道处的半导体层造成伤害,所以需要在半导体层上制作一层蚀刻阻挡层(EtchStopper),通过蚀刻阻挡层对半导体层进行保护,防止在制作源极和漏极时的蚀刻工艺对半导体层造成损伤。 When will [0004] In preparing a thin film transistor array substrate, if back channel etched using conventional (back channeletched, BCE) fabricating a thin film transistor embodiment, wet etching (wet etching) forming the source and drain at the channel a semiconductor layer of a channel at the damage, it is necessary to produce a layer of etch stop layer (EtchStopper) on the semiconductor layer, the semiconductor layer is protected by the etching stopper layer, etching process to prevent the production of the source and drain of the semiconductor layer damage.

[0005]目前薄膜晶体管大多采用底栅结构,底栅结构的薄膜晶体管中,栅极(gate)与上方源极(source)和漏极(drain)的图形要有一定的交叠,导致在栅极与源极的交叠区产生寄生电容Cgs,以及在栅极与漏极的交叠区产生寄生电容Cgd,造成增加扫描线和数据线的负载(loading)。 [0005] Most of the current thin film transistor using a bottom-gate structure, the thin film transistor bottom gate structure, the gate (Gate) and above the source (source) and drain (Drain) pattern to have a certain overlap, resulting in the gate and the source electrode overlapping region a parasitic capacitance Cgs, Cgd and a parasitic capacitance in the overlapping region of the gate and the drain, resulting in increased load of the scanning lines and the data lines (loading). 而且,薄膜晶体管采用底栅结构和蚀刻阻挡层结构时,要考虑蚀刻阻挡层与半导体层、源极及漏极之间的交叠区设计,造成薄膜晶体管无法小型化,降低了开口率,也增大了寄生电容。 Further, using the thin film transistor bottom gate structure and the etching barrier layer structure, to consider the etching stop layer and the semiconductor layer, the overlapping area between the design source and drain, resulting in miniaturization of the thin film transistor can not be reduced aperture ratio, and increases the parasitic capacitance.

[0006]另外,在液晶显示面板中,像素电极一般由透明的IT0(Indium Tin Oxide,氧化铟锡)制成。 [0006] Further, the liquid crystal display panel, the pixel electrodes are generally made of transparent IT0 (Indium Tin Oxide, Indium Tin Oxide). 在制作TFT的半导体层和像素电极时,需要采用两道光罩制程,以分别制作TFT的半导体层和像素电极,导致需要更多的光罩(mask)使用数量以及更复杂的制作工艺,使制作成本上升,降低了生产效率。 When the semiconductor layer forming a TFT and a pixel electrode, need two mask process for fabricating a semiconductor layer, respectively, and a pixel electrode of the TFT, resulting in the need for more number reticle (mask) using a more complex production process and the production rising costs, reducing production efficiency.

发明内容 SUMMARY

[0007]本发明目的在于提供一种氧化物薄膜晶体管阵列基板及制作方法,通过采用顶栅结构的氧化物半导体TFT,减少了寄生电容的产生,同时利用离子注入同时形成像素电极,减少制程,降低成本和提高生产效率。 [0007] The object of the present invention is to provide an oxide thin film transistor array substrate and a manufacturing method, by using an oxide semiconductor TFT top-gate structure, reducing the generation of parasitic capacitance, while simultaneously using ion implantation to form the pixel electrode, reducing the manufacturing process, reduce costs and increase productivity.

[0008]本发明实施例提供一种氧化物薄膜晶体管阵列基板的制作方法,所述制作方法包括: [0008] The manufacturing method of embodiments of the present invention provides an oxide thin film transistor array substrate, the manufacturing method comprising:

[0009]在衬底上制作形成氧化物半导体层,其中所述氧化物半导体层包括第一区域、第二区域和第三区域; [0009] Production of the oxide semiconductor layer is formed on a substrate, wherein the oxide semiconductor layer comprises a first region, second and third regions;

[0010]在所述衬底上连续形成栅极绝缘层薄膜和栅极金属层薄膜,其中所述栅极绝缘层薄膜覆盖所述氧化物半导体层,所述栅极金属层薄膜覆盖所述栅极绝缘层薄膜; [0010] continuously forming a gate insulating layer and the gate metal film layer film on the substrate, wherein the gate insulating layer covering the thin film of the oxide semiconductor layer, the gate metal layer of the film covering the gate gate insulating film layer;

[0011]对所述栅极金属层薄膜和所述栅极绝缘层薄膜进行图形化,使所述栅极金属层薄膜在被图形化之后形成氧化物薄膜晶体管的栅极,使所述栅极绝缘层薄膜在被图形化之后形成栅极绝缘层,其中所述栅极绝缘层覆盖所述氧化物半导体层的第一区域; [0011] the gate metal layer and the gate insulating layer thin film patterning the gate metal layer forming the gate oxide film of the thin film transistor after being patterned so that the gate forming a gate insulating film layer after the insulating layer is patterned, wherein the gate insulating layer covering a first region of the oxide semiconductor layer;

[0012]在所述氧化物半导体层的第一区域被所述栅极绝缘层覆盖的前提下,对所述氧化物半导体层的第二区域和第三区域进行离子注入,使所述第二区域和所述第三区域由半导体分别转变为第一电极和第二电极,其中所述第二电极作为像素电极,所述第一区域保持为半导体性质并作为氧化物薄膜晶体管的沟道区; [0012] provided by the gate insulating layer covering the first region in the oxide semiconductor layer under a second region of the oxide semiconductor layer and the third ion implantation region, the second region and the third semiconductor region are changed from the first and second electrodes, wherein the second electrode as a pixel electrode, the first semiconductor region is maintained and the properties as a channel region of the oxide thin film transistor;

[0013]在所述衬底上形成第一钝化层,其中所述第一钝化层覆盖所述第一电极、所述栅极和所述第二电极,并在所述第一钝化层中与所述第一电极相对应的位置形成通孔; [0013] formed in the first passivation layer on the substrate, wherein the first passivation layer covering the first electrode, the gate electrode and the second electrode, and the first passivation the first electrode layer is formed at a position corresponding to a through hole;

[0014]在所述第一钝化层上形成数据线,其中所述数据线填入所述第一钝化层的通孔中与所述第一电极电连接; [0014] The data line formed on the first passivation layer, wherein the data line is filled vias of the first passivation layer is electrically connected to the first electrode;

[0015]在所述第一钝化层上形成第二钝化层,其中所述第二钝化层覆盖所述数据线。 [0015] a second passivation layer on the first passivation layer, wherein the second passivation layer covering the data line.

[0016]进一步地,对所述栅极金属层薄膜和所述栅极绝缘层薄膜进行图形化的步骤具体包括: [0016] Further, the gate metal layer and the gate insulating layer thin film patterning step comprises:

[0017]在所述栅极金属层薄膜上涂覆一层光阻层,对所述光阻层进行曝光和显影,利用显影留下的光阻层图案作为遮罩对所述栅极金属层薄膜进行一次湿蚀刻,所述栅极金属层薄膜在被湿蚀刻之后形成所述栅极; [0017] coated with a photoresist layer on the gate metal thin film layer, the photoresist layer is exposed and developed by using a developing the photoresist layer pattern as a mask to leave said gate metal layer a thin film is wet etching of the gate metal film layer is formed after the gate electrode is wet-etched;

[0018]再以所述光阻层图案作为遮罩对所述栅极绝缘层薄膜进行一次干蚀刻,所述栅极绝缘层薄膜在被干蚀刻之后形成所述栅极绝缘层。 [0018] In the photoresist layer is then patterned as a mask layer on the gate insulating film is a dry etching, the gate insulating film layer is formed after the gate insulating layer is dry-etched.

[0019]进一步地,所述制作方法还包括在所述第二钝化层上制作形成公共电极。 [0019] Further, the manufacturing method further comprises a second passivation layer on the common electrode were formed was prepared.

[0020]进一步地,在所述衬底上制作形成所述氧化物半导体层之前,所述制作方法还包括在所述衬底上先制作一层挡光层,所述挡光层所处的位置对应于所述氧化物半导体层的第一区域。 Before [0020] Further, formed on the substrate made of the oxide semiconductor layer, the manufacturing method further comprising on said substrate to produce a layer of light blocking layer, the light blocking layer is located position corresponding to a first region of the oxide semiconductor layer.

[0021]进一步地,对所述氧化物半导体层进行离子注入的方式为在PECVD设备中,用Η离子或者Ar离子对所述氧化物半导体层进行等离子体处理。 Embodiment [0021] Further, the oxide semiconductor layer of the ion implantation apparatus as PECVD, plasma of the oxide semiconductor layer Η Ar ions or plasma treatment.

[0022]本发明实施例还提供一种氧化物薄膜晶体管阵列基板,包括: Example [0022] The present invention also provides an oxide thin film transistor array substrate, comprising:

[0023]衬底; [0023] a substrate;

[0024]形成在所述衬底上的氧化物半导体层,所述氧化物半导体层包括第一区域、第二区域和第三区域; [0024] forming an oxide layer on the semiconductor substrate, the oxide semiconductor layer comprises a first region, second and third regions;

[0025]形成在所述氧化物半导体层上的栅极绝缘层,所述栅极绝缘层覆盖所述氧化物半导体层的第一区域; [0025] forming a gate insulating layer on the oxide semiconductor layer, a gate insulating layer covering a first region of the oxide semiconductor layer;

[0026]形成在所述栅极绝缘层上的氧化物薄膜晶体管的栅极,所述栅极与所述栅极绝缘层自对准,所述氧化物半导体层的第二区域和第三区域在进行离子注入之后由半导体分别转变为第一电极和第二电极,所述第二电极作为像素电极,所述第一区域保持为半导体性质并作为氧化物薄膜晶体管的沟道区; A gate oxide thin film transistor [0026] is formed on the gate insulating layer, the gate and the self-aligned gate insulating layer, a second region of the oxide semiconductor layer and the third region after performing the ion implantation are changed from the first semiconductor electrode and the second electrode, the second electrode as a pixel electrode, the first semiconductor region is maintained and the properties as a channel region of the oxide thin film transistor;

[0027]形成在所述衬底上的第一钝化层,所述第一钝化层覆盖所述第一电极、所述栅极和所述第二电极,所述第一钝化层在与所述第一电极相对应的位置形成有通孔; [0027] forming a first passivation layer on the substrate, the first passivation layer covering the first electrode, the gate electrode and the second electrode, the first passivation layer forming a position corresponding to a through hole of the first electrode;

[0028]形成在所述第一钝化层上的数据线,所述数据线填入所述第一钝化层的通孔中与所述第一电极电连接; [0028] forming a first passivation layer on the data lines, the data lines filling the vias in the first passivation layer is electrically connected to the first electrode;

[0029]形成在所述第一钝化层上的第二钝化层,所述第二钝化层覆盖所述数据线。 [0029] a second passivation layer on the first passivation layer, the second passivation layer covering the data line.

[0030]进一步地,所述氧化物薄膜晶体管阵列基板还包括形成在所述衬底上的挡光层,所述氧化物半导体层覆盖在所述挡光层上,所述挡光层所处的位置对应于所述氧化物半导体层的第一区域。 [0030] Further, the oxide thin film transistor array substrate further comprises forming a light blocking layer on the substrate, the oxide semiconductor layer overlying the light-blocking layer, the light blocking layer is located the position corresponding to the first region of the oxide semiconductor layer.

[0031]进一步地,所述氧化物薄膜晶体管阵列基板还包括形成在所述第二钝化层上的公共电极。 [0031] Further, the oxide thin film transistor array substrate further comprises a common electrode formed on the second passivation layer.

[0032 ]进一步地,所述氧化物半导体层的材料为IGZO。 [0032] Further, the material of the oxide semiconductor layer is IGZO.

[0033]本发明实施例还提供一种液晶显示面板,包括氧化物薄膜晶体管阵列基板和彩色滤光片基板以及夹置在所述氧化物薄膜晶体管阵列基板与所述彩色滤光片基板之间的液晶层,所述氧化物薄膜晶体管阵列基板为上述的氧化物薄膜晶体管阵列基板。 [0033] and sandwiched the oxide thin film transistor array substrate and the color filter substrate between the oxide thin film transistor array substrate and the color filter substrate according to the present invention further provides a liquid crystal display panel, comprising a liquid crystal layer, the oxide thin film transistor array substrate of the above-mentioned oxide thin film transistor array substrate.

[0034]本发明实施例提供的氧化物薄膜晶体管阵列基板及制作方法,采用顶栅结构的氧化物半导体TFT,栅极与源/漏之间没有交叠区,可减少寄生电容,增大开口率。 [0034] The oxide thin film transistor array substrate and a manufacturing method provided in the embodiment of the present invention, a top-gate structure of the TFT oxide semiconductor, there is no overlap between the gate region and the source / drain, the parasitic capacitance can be reduced, increasing the opening rate. 在制作完成栅极绝缘层和栅极之后,利用对氧化物半导体层进行离子注入的方式制作形成像素电极,即在形成半导体沟道区时同时形成像素电极,可省去单独制作像素电极的光罩和蚀刻制程。 After finished gate insulating layer and gate electrode by way of the oxide semiconductor layer is formed by ion implantation of making the pixel electrode, i.e., the pixel electrode is formed simultaneously when forming a semiconductor channel region, the light can be omitted to create separate pixel electrode cover and etching process. 现有制程中,氧化物半导体层和像素电极需要两次独立的蚀刻制程来分别制作,因此本发明可以省去一道光罩制程,减少了光罩的使用数量,降低了制作成本和提升了生产效率。 In the conventional process, the oxide semiconductor layer and a pixel electrode requires two separate etching process to produce, respectively, the present invention is thus omitted a masking process, reduces the number of mask, reduce production costs and enhance productivity effectiveness.

附图说明 BRIEF DESCRIPTION

[0035]图1A至图1H为本发明实施例在制备氧化物薄膜晶体管阵列基板时的局部剖面示意图。 [0035] FIGS. 1A to 1H schematic partial cross-sectional embodiment in the preparation of an oxide thin film transistor array substrate of the embodiment of the present invention.

[0036]图2为本发明另一实施例中氧化物薄膜晶体管阵列基板的局部剖面示意图。 A partial schematic cross-sectional view of the embodiment of an oxide thin film transistor array substrate [0036] FIG 2 a further embodiment of the present invention.

具体实施方式 Detailed ways

[0037]为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及实施例,对本发明的具体实施方式、结构、特征及其功效,详细说明如后。 [0037] To further elaborate the technical means and effects the present invention is predetermined to achieve the object of the invention taken in conjunction with the accompanying drawings and the following embodiments, a specific embodiment, structure, characteristics and efficacy of the present invention, as described later in detail.

[0038]图1A至图1H为本发明实施例在制备氧化物薄膜晶体管阵列基板时的局部剖面示意图,该制作方法包括: [0038] FIGS. 1A to 1H is a partially schematic cross-sectional view Example preparing an oxide thin film transistor array substrate of the embodiment of the invention, the manufacturing method comprising:

[0039]如图1A所示,在衬底11上制作形成氧化物半导体层12。 [0039] As shown in FIG. 1A, on the substrate 11 forming the oxide semiconductor layer 12 is formed. 衬底11可以是玻璃、石英、娃片或其它柔性衬底如塑料、不锈钢等。 The substrate 11 may be glass, quartz, baby or other flexible sheet substrate such as a plastic or stainless steel. 氧化物半导体层12可以是IGZ0(Indium GalliumZinc Oxide,铟嫁锌氧化物)、ITZ0(Indium Tin Zinc Oxide,铟锡锌氧化物)或ZnO(Zincoxide,氧化锌)等氧化物半导体材料。 The oxide semiconductor layer 12 may be IGZ0 (Indium GalliumZinc Oxide, Indium Zinc Oxide married), ITZ0 (Indium Tin Zinc Oxide, Indium Tin Zinc Oxide) or ZnO (Zincoxide, zinc oxide) or the like oxide semiconductor material. 在衬底11上制作氧化物半导体层12时,可以通过例如磁控溅射或热蒸发等方法在衬底11上先沉积形成一层氧化物半导体薄膜,然后再通过蚀刻工艺(例如包括上光阻、曝光、显影、蚀刻、去光阻等步骤)对该氧化物半导体薄膜进行蚀刻图形化,以在衬底11上制作形成氧化物半导体层12。 On the substrate 11 made of the oxide semiconductor layer 12, an oxide semiconductor thin film layer may be formed by, for example magnetron sputtering or thermal evaporation, etc. to be deposited on the substrate 11, and then by an etching process (e.g., including glazing resistance, exposure, development, etching, photo resist etc. step) of etching the oxide semiconductor thin film pattern, formed on the substrate 11 to form the oxide semiconductor layer 12.

[0040]如图1B所示,在衬底11上依次连续形成栅极绝缘层薄膜13和栅极金属层薄膜14共两层薄膜。 As shown in [0040] FIG. 1B, successively forming a gate insulating layer and the gate metal film 13 is a thin film layer 14 of two-layer film on the substrate 11. 栅极绝缘层薄膜13例如为氧化娃(S1x)、氮化娃(SiNx)或氮氧化娃(S1Nx)薄膜,栅极金属层薄膜14可以采用0、1、11、1&、]\/[0、41、(:11等金属或合金,也可以采用由多层金属薄膜构成的复合薄膜。栅极绝缘层薄膜13可通过等离子体增强化学气相沉积(PECVD)等方法沉积形成在衬底11上并覆盖氧化物半导体层12,栅极金属层薄膜14可通过磁控溅射或热蒸发等方法沉积形成并覆盖栅极绝缘层薄膜13。 The gate insulating layer 13, for example, oxide film Wa (S1x), baby nitride (SiNx) or oxynitride Wa (S1Nx) film, a gate metal film layer 14 may be employed 0,1,11,1 &,] \ / [0 , 41, (: 11 or a metal alloy, may also be used in a multilayer composite film composed of a metal thin film layer, a gate insulating film 13 may be deposited on the substrate 11 is formed by plasma enhanced chemical vapor deposition (PECVD) method and the like. and cover the oxide semiconductor layer 12, the gate metal layer 14 may be deposited film formed by magnetron sputtering or thermal evaporation and the like gate insulating layer covering the thin film 13.

[0041 ]如图1C所示,在栅极金属层薄膜14上涂覆一层光阻层,对光阻层进行曝光和显影,利用显影留下的光阻层图案20作为遮罩对栅极金属层薄膜14进行一次湿蚀刻工艺,栅极金属层薄膜14在被湿蚀刻之后形成氧化物薄膜晶体管的栅极14a。 [0041] 1C, the photoresist layer 14 coated with a layer of gate metal film on the photoresist layer is exposed and developed, leaving the photoresist layer by the developing pattern 20 as a mask the gate a metal thin film layer 14 is a wet etching process, the gate metal layer 14 is formed thin gate oxide thin film transistor 14a after being wet-etched.

[0042]如图1D所示,在蚀刻完栅极金属层薄膜14之后,接着再以该光阻层图案20作为遮罩对栅极绝缘层薄膜13进行一次干蚀刻工艺,栅极绝缘层薄膜13在被干蚀刻之后形成栅极绝缘层13a。 [0042] As shown in FIG. 1D, after completion of the etching of the gate metal layer film 14, followed in the photoresist layer pattern 20 as a mask layer on the gate insulating film 13 is a dry etching process, the gate insulating film layer 13 a gate insulating layer 13a after being dry-etched. 在上述两次蚀刻步骤中,均以该光阻层图案20作为遮罩进行蚀刻,因此栅极14a和栅极绝缘层13a之间具有自对准效果。 In the two above-mentioned etching step, the photoresist layer are pattern 20 as a mask by etching, thus having the effect of self-alignment between the gate electrode 13a and the gate insulating layer 14a. 栅极绝缘层13a局部地覆盖在氧化物半导体层12上,氧化物半导体层12包括被栅极绝缘层13a覆盖的第一区域A和未被栅极绝缘层13a覆盖的第二区域B和第三区域C。 The gate insulating layer 13a partially overlying the oxide semiconductor layer 12, the oxide semiconductor layer 12 includes a first area A and the gate insulating layer 13a not covered with the gate insulating layer 13a covering the second region B and three-zone C.

[0043]如图1E所示,在氧化物半导体层12的第一区域A被栅极绝缘层13a覆盖的前提下,对氧化物半导体层12进行离子注入,使氧化物半导体层12的第二区域B和第三区域C由半导体分别转变为第一电极122和第二电极123。 [0043] As shown, the oxide semiconductor layer under the premise of the first region A 12 is covered with the gate insulating layer 13a, the oxide semiconductor layer 12 by ion implantation 1E, a second oxide semiconductor layer 12 region B and the third semiconductor region C were changed from a first electrode 122 and the second electrode 123. 在对氧化物半导体层12进行离子注入时,可以在PECVD设备中,用Η离子或者Ar离子等对氧化物半导体层12进行等离子体处理。 When the oxide semiconductor layer 12 by ion implantation, can be performed on the oxide semiconductor layer by plasma treatment Η ions such as Ar ions, or 12 in a PECVD apparatus. 例如向PECVD设备的反应腔室内通入H2或Ar气体,其中通入H2或Ar气体的流量控制在2000〜SOOOsccm(标准状况下毫升/分钟)之间,施加的射频功率控制在4400〜5360W(瓦)之间,并控制等离子体处理的时间在60〜120s(秒)之间。 For example, introduced into the reaction chamber of a PECVD apparatus Ar gas or H2, where H2, or into the flow control between the Ar gas (ml / min under standard conditions) 2000~SOOOsccm, RF power is applied to the control 4400~5360W ( between W), and controls the plasma processing time between 60~120s (s). 在经过前述等离子体处理之后,Η离子或者Ar离子注入至氧化物半导体层12的第二区域Β和第三区域C中,使氧化物半导体层12的第二区域B和第三区域C由半导体转变为导体,分别形成第一电极122和第二电极123,其中第一电极122作为与数据线16相连的导通电极,第二电极123作为每个像素区域的像素电极。 After the plasma treatment, [eta] or ion implantation of Ar ions to the oxide layer of the second semiconductor region 12 and the third region C Β, the oxide semiconductor layer in the second region 12 B and the third region C of a semiconductor into a conductor, a first electrode 122 and second electrode 123 are formed, in which a first conductive electrode 122 connected to the data line 16 as a through electrode, the second electrode 123 as a pixel electrode in each pixel region. 当氧化物半导体层12选用IGZ0时,其透过率在80%左右,基本上与ΙΤ0的透过率相当,因此第二电极123可以作为透明像素电极。 When the selection IGZ0 12 when the oxide semiconductor layer, the transmittance of about 80%, and the transmittance ΙΤ0 substantially equivalent, and thus the second electrode 123 can be used as the transparent pixel electrode. 氧化物半导体层12的第一区域A由于被栅极绝缘层13a覆盖保护而不会受到离子注入的影响,因此仍然保持为半导体性质并作为氧化物薄膜晶体管的沟道区121。 The oxide semiconductor layer of the first region A 12 due to the gate covered with a protective insulating layer 13a without being affected by the ion implantation, the channel region 121 and therefore remains as an oxide semiconductor properties of the thin film transistor.

[0044]对氧化物半导体层12进行离子注入之后,去除该光阻层图案20。 [0044] After the oxide semiconductor layer 12 by ion implantation, the photoresist layer pattern 20 is removed. 在其他实施例中,该光阻层图案20也可以在对栅极绝缘层薄膜13进行干蚀刻之后,在对氧化物半导体层12进行离子注入之前去除。 In other embodiments, the patterned photoresist layer 20 may be performed after the gate insulating film layer 13 by dry etching, removing the oxide semiconductor layer 12 prior to ion implantation.

[0045]如图1F所示,在衬底11上形成第一钝化层15,第一钝化层15覆盖第一电极122、栅极14a和第二电极123,并在第一钝化层15中与第一电极122相对应的位置形成通孔150。 [0045] As shown, the first passivation layer 15 is formed on the substrate 11 1F, the first passivation layer 15 covers the first electrode 122, second electrode 123 and the gate electrode 14a and the first passivation layer 15 with the first electrode 122 at positions corresponding to the through hole 150 is formed. 第一钝化层15例如为氧化硅、氮化硅或氮氧化硅薄膜,可通过PECVD等方法形成在衬底11上并覆盖栅极14a以及第一电极122和第二电极123,然后再通过蚀刻工艺(例如包括上光阻、曝光、显影、蚀刻、去光阻等步骤)对第一钝化层15进行蚀刻图形化,以在第一钝化层15中与第一电极122相对应的位置处形成通孔150。 The first passivation layer 15, for example, silicon oxide, silicon nitride or a silicon oxynitride film may be formed on the substrate 11 and covering the gate electrode 14a and the first electrode 122 and the second electrode 123 by a method such as PECVD, and then through etch process (e.g., including a photoresist, exposure, development, etching, photo resist etc. step) of etching the first passivation layer 15 patterned to the first passivation layer 15 and the first electrode 122 corresponding to the the through hole 150 is formed at a position.

[0046]如图1G所示,在第一钝化层15上形成数据线16,数据线16通过第一钝化层15中的通孔150与第一电极122电连接。 [0046] As shown in FIG. 1G, the data line 16 is formed on the first passivation layer 15, data line 16 to the first electrode 150 are connected through the through hole 122 of the first passivation layer 15. 数据线16可以采用0、胃、1^&、10^1、(:11等金属或合金,也可以采用由多层金属薄膜构成的复合薄膜。在第一钝化层15上形成数据线16时,可以通过例如磁控溅射或热蒸发等方法在第一钝化层15上沉积一层第二金属层,再通过一次蚀刻工艺(例如包括上光阻、曝光、显影、蚀刻、去光阻等步骤)对该第二金属层进行蚀刻图形化,以在第一钝化层15上形成数据线16,同时数据线16填入第一钝化层15的通孔150中与第一电极122电连接。 Data lines 16 0 may be employed, stomach, & ^ 1, 10 ^ 1, (: 11 or a metal alloy, may also be used a multilayer composite film composed of a metal thin film formed in the data line 16 on the first passivation layer 15. when, for example, by magnetron sputtering or thermal evaporation method such as depositing a second metal layer on the first passivation layer 15, once again by an etching process (e.g., including a photoresist, exposure, development, etching, delustering step hindrance or the like) on the second patterned metal layer is etched, to form the data line 16 on the first passivation layer 15, while data line 16 is filled in the through hole 150 of the first passivation layer 15 and the first electrode 122 are electrically connected.

[0047]如图1H所示,在第一钝化层15上形成第二钝化层17,第二钝化层17覆盖数据线16。 [0047] FIG. 1H, a second passivation layer 17 is formed on the first passivation layer 15, the second passivation layer 17 covering the data line 16. 第二钝化层17例如为氧化硅、氮化硅或氮氧化硅薄膜,可通过PECVD等方法形成在第一钝化层15上并覆盖数据线16,并且还可以通过一次干蚀刻工艺(例如包括上光阻、曝光、显影、蚀亥IJ、去光阻等步骤)对第二钝化层17进行蚀刻,以在第二钝化层17的外围区域(非显示区域)形成外围线路的过孔(图未示)。 The second passivation layer 17, for example, silicon oxide, silicon nitride or a silicon oxynitride film may be formed on the first passivation layer covers the data lines 15 and 16 by PECVD or the like, and also by a dry etching process (e.g. including photoresist, exposure, development, etching Hai IJ, etc. Stripping step) on the second passivation layer 17 is etched to the peripheral region of the second passivation layer 17 (the non-display region) is formed through a peripheral line hole (not shown).

[0048]至此,制作完成的氧化物薄膜晶体管阵列基板,可以作为扭曲向列模式(TwistedNematic,TN)的液晶显示面板的阵列基板,该液晶显示面板还包括彩色滤光片基板(图未示)以及夹设在彩色滤光片基板和阵列基板之间的液晶层(图未示),在彩色滤光片基板上还制作形成有公共电极(图未示)。 [0048] Thus, the finished oxide thin film transistor array substrate, the array substrate may be distorted as the liquid crystal display panel, nematic mode (TwistedNematic, TN), and the liquid crystal display panel further includes a color filter substrate (not shown) and a liquid crystal layer (not shown) interposed between the substrate and the color filter array substrate, the color filter substrate formed with a common electrode is also produced (not shown).

[0049]或者,如图1H所示,再在第二钝化层17上制作公共电极18。 [0049] Alternatively, as shown in FIG. 1H, and then make the common electrode 18 on the second passivation layer 17. 公共电极18可以通过例如磁控溅射或热蒸发等方法先在第二钝化层17上沉积一层透明导电材料层,然后通过一道蚀刻工艺(例如包括上光阻、曝光、显影、蚀刻、去光阻等步骤)对该透明导电材料层进行蚀刻图形化,以在第二钝化层17上形成公共电极18。 The common electrode 18 may be, for example, by magnetron sputtering or thermal evaporation, etc. to the layer of transparent conductive material layer 17 is deposited on the second passivation layer, and then an etching process (e.g., including a photoresist, exposure, development, etching, Stripping step etc.) is etched patterned to form the common electrode 18 on the second passivation layer 17 to the transparent conductive material layer. 本实施例中,公共电极18在每个像素区域被蚀刻形成为具有多个条状电极部,例如呈梳子状。 In this embodiment, the common electrode 18 is etched to form a plurality of strip electrode portions to have such a comb shape in each pixel area. 公共电极18例如为氧化铟锡(ΙΤ0)、氧化铟锌(ΙΖ0)或氧化铝锌等。 The common electrode 18 is, for example, indium tin oxide (ΙΤ0), indium zinc oxide (ΙΖ0) or aluminum zinc oxide and the like. 如此,用于驱动液晶偏转的像素电极(即第二电极123)与公共电极18同时形成在阵列基板上,使阵列基板可以作为边缘场开关模式(Fringe FieldSw it ch i ng,FFS)的液晶显示面板的阵列基板。 Thus, the pixel electrodes for driving the liquid crystal deflected (i.e., the second electrode 123) is formed simultaneously with the common electrode 18 on the array substrate, the array substrate so as fringe field switching (Fringe FieldSw it ch i ng, FFS) liquid crystal display the array substrate panel.

[0050]氧化物半导体在受到短波长小于375nm的光照射时,漏电流会增大,为了进一步改善氧化物薄膜晶体管的特性,请参图2,图2为本发明另一实施例中氧化物薄膜晶体管阵列基板的局部剖面示意图,本实施例中在衬底11上制作形成氧化物半导体层12之前,先在衬底11上先制作一层挡光层19,挡光层19所处的位置对应于氧化物半导体层12的第一区域A。 Oxide in Example [0050] When the oxide semiconductor light irradiated by short wavelength less than 375nm, the leakage current will increase, in order to further improve the characteristics of the oxide TFT, refer to FIG. 2, FIG. 2 of another embodiment of the present invention. a partial schematic cross-sectional view of the TFT array substrate, before the 12 position, in the first layer on the substrate 11 to produce a light blocking layer, the oxide semiconductor layer 19, the light blocking layer 19 is produced in which the embodiment is formed on the substrate 11 in this embodiment corresponding to the oxide semiconductor layer of the first region 12 A. 挡光层19可以通过蚀刻或印刷的方式形成,可以采用不透光的非金属材料或者金属材料。 The light blocking layer 19 may be formed by etching or printing method, an opaque non-metallic material or a metal material may be employed. 若挡光层19采用金属材料时,还包括在挡光层19上覆盖一层绝缘层,使氧化物半导体层12再形成在该绝缘层上,通过该绝缘层将氧化物半导体层12与下面金属的挡光层19隔开并绝缘。 If the light blocking layer 19 is made of metal, further comprising an insulating layer is covered with a layer on the light blocking layer 19, the oxide semiconductor layer 12 is further formed on the insulating layer, through the insulating layer and the oxide semiconductor layer 12 below a metal light blocking layer 19 is spaced apart and insulated. 另外,在后续蚀刻制作栅极14a和栅极绝缘层13a时,可以采用与制作挡光层19时相同的光罩,使挡光层19、栅极14a、栅极绝缘层13a和氧化物半导体层12的第一区域A(即沟道区121)均相互对准。 Further, in subsequent etching of the gate insulating layer 14a and the gate 13a, the same mask may be used when 19 and making the light blocking layer, the light blocking layer 19, gate electrode 14a, a gate insulating layer 13a and the oxide semiconductor the first area a (i.e., the channel region 121) layer 12 are aligned with each other. 本实施例中通过在氧化物薄膜晶体管的沟道区121下方设置一层挡光层19,避免了衬底11下方短波长光的照射对氧化物薄膜晶体管的特性造成不利影响。 In the present embodiment under the oxide thin film transistor by a channel region 121 is provided in one embodiment the light blocking layer 19, the substrate 11 is avoided under the irradiation of short-wavelength light adversely affect the characteristics of the oxide thin film transistor.

[0051]本发明实施例还提供一种液晶显示面板,包括彩色滤光片基板和氧化物薄膜晶体管阵列基板以及夹置在彩色滤光片基板与氧化物薄膜晶体管阵列基板之间的液晶层,该氧化物薄膜晶体管阵列基板为上述的氧化物薄膜晶体管阵列基板。 [0051] The present invention further provides a liquid crystal display panel comprising a color filter substrate and an oxide thin film transistor array substrate and a liquid crystal layer sandwiched between the color filter substrate and the oxide thin film transistor array substrate, the oxide thin film transistor array substrate of the above-mentioned oxide thin film transistor array substrate.

[0052]本发明实施例提供氧化物薄膜晶体管阵列基板及其制作方法,采用顶栅结构的氧化物半导体TFT,栅极与源/漏之间没有交叠区,可减少寄生电容,增大开口率。 [0052] The embodiment provides an oxide thin film transistor array substrate and the manufacturing method of the present invention, a top-gate structure of the TFT oxide semiconductor, there is no overlap between the gate region and the source / drain, the parasitic capacitance can be reduced, increasing the opening rate. 在制作完成栅极绝缘层和栅极之后,利用对氧化物半导体层进行离子注入的方式制作形成像素电极,即在形成半导体沟道区时同时形成像素电极,可省去单独制作像素电极的光罩和蚀刻制程。 After finished gate insulating layer and gate electrode by way of the oxide semiconductor layer is formed by ion implantation of making the pixel electrode, i.e., the pixel electrode is formed simultaneously when forming a semiconductor channel region, the light can be omitted to create separate pixel electrode cover and etching process. 现有制程中,氧化物半导体层和像素电极需要两次独立的蚀刻制程来分别制作,因此本发明可以省去一道光罩制程,减少了光罩的使用数量,降低了制作成本和提升了生产效率。 In the conventional process, the oxide semiconductor layer and a pixel electrode requires two separate etching process to produce, respectively, the present invention is thus omitted a masking process, reduces the number of mask, reduce production costs and enhance productivity effectiveness.

[0053]以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。 [0053] The above are only preferred embodiments of the present invention only, not limitation of the present invention in any form, although the invention has been disclosed above by the preferred embodiments, but not intended to limit the present invention, anyone familiar with Those skilled in the art, without departing from the scope of the technical solution of the present invention, when the content of the above techniques can be used to make minor modifications disclosed as equivalent variations or modifications equivalent embodiments, but all without departing from the technical content of the present invention, according to technical essence of the invention is a simple modification of any of the above embodiments made equivalent modifications and variations, provided they fall within the scope of the present invention.

Claims (10)

1.一种氧化物薄膜晶体管阵列基板的制作方法,其特征在于,所述制作方法包括: 在衬底(11)上制作形成氧化物半导体层(12),其中所述氧化物半导体层(12)包括第一区域(A)、第二区域(B)和第三区域(C); 在所述衬底(11)上连续形成栅极绝缘层薄膜(13)和栅极金属层薄膜(14),其中所述栅极绝缘层薄膜(13)覆盖所述氧化物半导体层(12),所述栅极金属层薄膜(14)覆盖所述栅极绝缘层薄膜(13); 对所述栅极金属层薄膜(14)和所述栅极绝缘层薄膜(13)进行图形化,使所述栅极金属层薄膜(14)在被图形化之后形成氧化物薄膜晶体管的栅极(14a),使所述栅极绝缘层薄膜(13)在被图形化之后形成栅极绝缘层(13a),其中所述栅极绝缘层(13a)覆盖所述氧化物半导体层(12)的第一区域(A); 在所述氧化物半导体层(12)的第一区域(A)被所述栅极绝缘层(13a)覆盖的前提下,对所述氧化物半导体层(12)的第 CLAIMS 1. A method of manufacturing an oxide thin film transistor array substrate, wherein, said production method comprising: on a substrate (11) of the oxide semiconductor layer (12) formed in the production, wherein the oxide semiconductor layer (12 ) comprises a first region (A), a second region (B) and the third region (C); a gate insulating layer is formed continuously in a thin film on the substrate (11) (13) and the gate metal film layer (14 ), wherein said gate insulating layer film (13) covering the oxide semiconductor layer (12), the gate metal film layer (14) covering the gate insulating film layer (13); the gate a thin film metal layer (14) and the gate insulating layer film (13) patterning the layer of said gate metal film (14) forming a gate oxide thin film transistor (14a) after being patterned, the gate insulating layer of said thin film (13) forming a gate insulating layer (13a) after being patterned, wherein the gate insulating layer (13a) covering a first region of the oxide semiconductor layer (12) ( a); the premise covered by the gate insulating layer (13a) in a first region (a) of the oxide semiconductor layer (12), the first oxide semiconductor layer (12) 区域(B)和第三区域(C)进行离子注入,使所述第二区域(B)和所述第三区域(C)由半导体分别转变为第一电极(122)和第二电极(123),其中所述第二电极(123)作为像素电极,所述第一区域(A)保持为半导体性质并作为氧化物薄膜晶体管的沟道区(121); 在所述衬底(11)上形成第一钝化层(15),其中所述第一钝化层(15)覆盖所述第一电极(122)、所述栅极(14a)和所述第二电极(123),并在所述第一钝化层(15)中与所述第一电极(122)相对应的位置形成通孔(150); 在所述第一钝化层(15)上形成数据线(16),其中所述数据线(16)填入所述第一钝化层(15)的通孔(150)中与所述第一电极(122)电连接; 在所述第一钝化层(15)上形成第二钝化层(17),其中所述第二钝化层(17)覆盖所述数据线(16)。 Region (B) and the third region (C) by ion implantation, the second region (B) and the third region (C) into the first semiconductor electrodes (122) and a second electrode (123 ), wherein said second electrode (123) as the pixel electrode, the first region (a) holding a semiconductor properties as a channel region and an oxide thin film transistor (121); in the substrate (11) forming a first passivation layer (15), wherein said first passivation layer (15) covering the first electrode (122), the gate (14a) and said second electrode (123), and the first passivation layer (15) with said first electrode (122) formed at a position corresponding to the through-hole (150); a data line (16) on said first passivation layer (15), wherein said data line (16) of the fill (122) is electrically connected to the first electrode of the first passivation layer (15) through holes (150); said first passivation layer (15) is formed on the second passivation layer (17), wherein the second passivation layer (17) covering the data line (16).
2.如权利要求1所述的氧化物薄膜晶体管阵列基板的制作方法,其特征在于,对所述栅极金属层薄膜(14)和所述栅极绝缘层薄膜(13)进行图形化的步骤具体包括: 在所述栅极金属层薄膜(14)上涂覆一层光阻层,对所述光阻层进行曝光和显影,利用显影留下的光阻层图案(20)作为遮罩对所述栅极金属层薄膜(14)进行一次湿蚀刻,所述栅极金属层薄膜(14)在被湿蚀刻之后形成所述栅极(14a); 再以所述光阻层图案(20)作为遮罩对所述栅极绝缘层薄膜(13)进行一次干蚀刻,所述栅极绝缘层薄膜(13)在被干蚀刻之后形成所述栅极绝缘层(13a)。 2. The manufacturing method of an oxide thin film transistor array substrate as claimed in claim, wherein the film gate metal layer (14) and the gate insulating layer film (13) patterning step of comprises: a gate metal layer on said thin film (14) coated with a photoresist layer, the photoresist layer is exposed and developed using a developer remaining photoresist layer pattern (20) as a mask to the gate metal film layer (14) is a wet etching of the gate metal film layer (14) forming the gate (14a) after being wet-etched; then patterning the photoresist layer (20) as a mask layer on the gate insulating film (13) is a dry etching, the gate insulating layer film (13) forming the gate insulating layer (13a) after being dry-etched.
3.如权利要求1所述的氧化物薄膜晶体管阵列基板的制作方法,其特征在于,所述制作方法还包括在所述第二钝化层(17)上制作形成公共电极(18)。 The manufacturing method of an oxide thin film transistor array substrate 1 of claim, wherein said method further comprises making on the second passivation layer (17) forming a common electrode production (18).
4.如权利要求1所述的氧化物薄膜晶体管阵列基板的制作方法,其特征在于,在所述衬底(11)上制作形成所述氧化物半导体层(12)之前,所述制作方法还包括在所述衬底(11)上先制作一层挡光层(19),所述挡光层(19)所处的位置对应于所述氧化物半导体层(12)的第一区域(A)。 4. The manufacturing method of an oxide thin film transistor array substrate as claimed in claim, characterized in that, prior to (12) produced in the oxide semiconductor layer is formed on the substrate (11), said manufacturing method further includes on the substrate (11) to produce a layer of light blocking layer (19), the first stop position at which the light absorbing layer region (19) corresponding to the oxide semiconductor layer (12) (a ).
5.如权利要求1所述的氧化物薄膜晶体管阵列基板的制作方法,其特征在于,对所述氧化物半导体层(12)进行离子注入的方式为在PECVD设备中,用Η离子或者Ar离子对所述氧化物半导体层(12)进行等离子体处理。 5. The method of fabricating an oxide thin film transistor array substrate as claimed in claim, wherein the oxide semiconductor layer manner (12) for ion implantation in a PECVD apparatus using Ar ions or ions Η the oxide semiconductor layer (12) plasma treatment.
6.一种氧化物薄膜晶体管阵列基板,其特征在于,包括: 衬底(11); 形成在所述衬底(11)上的氧化物半导体层(12),所述氧化物半导体层(12)包括第一区域(A)、第二区域(B)和第三区域(C); 形成在所述氧化物半导体层(12)上的栅极绝缘层(13a),所述栅极绝缘层(13a)覆盖所述氧化物半导体层(12)的第一区域(A); 形成在所述栅极绝缘层(13a)上的氧化物薄膜晶体管的栅极(14a),所述栅极(14a)与所述栅极绝缘层(13a)自对准,所述氧化物半导体层(12)的第二区域(B)和第三区域(C)在进行离子注入之后由半导体分别转变为第一电极(122)和第二电极(123),所述第二电极(123)作为像素电极,所述第一区域(A)保持为半导体性质并作为氧化物薄膜晶体管的沟道区(121); 形成在所述衬底(11)上的第一钝化层(15),所述第一钝化层(15)覆盖所述第一电极(122)、所述栅极(14a)和所述第二电极(123),所述第一钝 An oxide thin film transistor array substrate comprising: a substrate (11); forming the oxide semiconductor layer in the substrate (12) (11), the oxide semiconductor layer (12 ) comprises a first region (a), a second region (B) and the third region (C); formed in the oxide semiconductor layer (gate insulating layer (13a) on 12), said gate insulating layer (13a) covering the first region (a) of the oxide semiconductor layer (12); forming a gate oxide thin film transistor on the gate insulating layer (13a) to (14a), said gate ( 14a) self-aligned with the gate insulating layer (13a), a second region of the oxide semiconductor layer (12), (B) and a third region (C) is performed after the ion implantation are changed from the first semiconductor an electrode (122) and a second electrode (123), said second electrode (123) as the pixel electrode, the first region (a) holding a semiconductor properties as a channel region and an oxide thin film transistor (121) ; forming a first passivation layer (15) (11) of said substrate, said first passivation layer (15) covering the first electrode (122), the gate (14a) and the said second electrode (123), said first obtuse 层(15)在与所述第一电极(122)相对应的位置形成有通孔(150); 形成在所述第一钝化层(15)上的数据线(16),所述数据线(16)填入所述第一钝化层(15)的通孔(150)中与所述第一电极(122)电连接; 形成在所述第一钝化层(15)上的第二钝化层(17),所述第二钝化层(17)覆盖所述数据线(16)。 Layer (15) is formed with a through hole (150) with said first electrode (122) corresponding to a position; formed on the data line (16) (15) of the first passivation layer, the data line (16) filled in the through hole (150) a first passivation layer (15) (122) is electrically connected to the first electrode; forming on the first passivation layer (15) of the second a passivation layer (17), the second passivation layer (17) covering the data line (16).
7.如权利要求6所述的氧化物薄膜晶体管阵列基板,其特征在于,所述氧化物薄膜晶体管阵列基板还包括形成在所述衬底(11)上的挡光层(19),所述氧化物半导体层(12)覆盖在所述挡光层(19)上,所述挡光层(19)所处的位置对应于所述氧化物半导体层(12)的第一区域(A) 0 7. The oxide thin film transistor array substrate according to claim 6, wherein the oxide thin film transistor array substrate further comprises forming a light blocking layer in the substrate (19) (11), said an oxide semiconductor layer (12) overlaid on said light blocking layer (19), the position at which the light blocking layer (19) corresponds to a first region of the oxide semiconductor layer (12) (a) 0
8.如权利要求6所述的氧化物薄膜晶体管阵列基板,其特征在于,所述氧化物薄膜晶体管阵列基板还包括形成在所述第二钝化层(17)上的公共电极(18)。 The oxide thin film transistor array substrate as claimed in claim 6, wherein the oxide thin film transistor array substrate further comprises a common electrode (18) on the second passivation layer (17).
9.如权利要求6所述的氧化物薄膜晶体管阵列基板,其特征在于,所述氧化物半导体层(12)的材料为IGZO。 9. The oxide thin film transistor array substrate according to claim 6, characterized in that the material of the oxide semiconductor layer (12) is IGZO.
10.—种液晶显示面板,包括氧化物薄膜晶体管阵列基板和彩色滤光片基板以及夹置在所述氧化物薄膜晶体管阵列基板与所述彩色滤光片基板之间的液晶层,其特征在于,所述氧化物薄膜晶体管阵列基板为权利要求6至9任一项所述的氧化物薄膜晶体管阵列基板。 10.- kinds of liquid crystal display panel, comprising an oxide thin film transistor array substrate and a color filter substrate and a liquid crystal layer sandwiched between said oxide thin film transistor array substrate and the color filter substrate, wherein the oxide thin film transistor array substrate as claimed oxide thin film transistor array substrate according to any one of claims 6-9.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105914213A (en) * 2016-06-01 2016-08-31 深圳市华星光电技术有限公司 Array substrate and preparation method thereof
CN106229346A (en) * 2016-08-31 2016-12-14 深圳市华星光电技术有限公司 Oxide semiconductor thin film transistor and manufacturing method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633176A (en) * 1992-08-19 1997-05-27 Seiko Instruments Inc. Method of producing a semiconductor device for a light valve
CN1353329A (en) * 2000-11-15 2002-06-12 松下电器产业株式会社 Thin film transistor array and its manufacturing method and display board using same
CN1577014A (en) * 2003-06-27 2005-02-09 Lg.菲利浦Lcd株式会社 In-plane switching mode liquid crystal display device and method for fabricating the same
CN101051134A (en) * 2006-04-06 2007-10-10 株式会社半导体能源研究所 Liquid crystal display device, semiconductor device, and electronic appliance
CN101145564A (en) * 2005-11-25 2008-03-19 香港科技大学 Active matrix display base plate preparing method
CN102543860A (en) * 2010-12-29 2012-07-04 京东方科技集团股份有限公司 Manufacturing method of low-temperature polysilicon TFT (thin-film transistor) array substrate
CN103441128A (en) * 2013-05-27 2013-12-11 南京中电熊猫液晶显示科技有限公司 TFT array substrate and manufacturing method thereof
CN104517972A (en) * 2013-10-07 2015-04-15 乐金显示有限公司 Display device and method of fabricating the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633176A (en) * 1992-08-19 1997-05-27 Seiko Instruments Inc. Method of producing a semiconductor device for a light valve
CN1353329A (en) * 2000-11-15 2002-06-12 松下电器产业株式会社 Thin film transistor array and its manufacturing method and display board using same
CN1577014A (en) * 2003-06-27 2005-02-09 Lg.菲利浦Lcd株式会社 In-plane switching mode liquid crystal display device and method for fabricating the same
CN101145564A (en) * 2005-11-25 2008-03-19 香港科技大学 Active matrix display base plate preparing method
CN101051134A (en) * 2006-04-06 2007-10-10 株式会社半导体能源研究所 Liquid crystal display device, semiconductor device, and electronic appliance
CN102543860A (en) * 2010-12-29 2012-07-04 京东方科技集团股份有限公司 Manufacturing method of low-temperature polysilicon TFT (thin-film transistor) array substrate
CN103441128A (en) * 2013-05-27 2013-12-11 南京中电熊猫液晶显示科技有限公司 TFT array substrate and manufacturing method thereof
CN104517972A (en) * 2013-10-07 2015-04-15 乐金显示有限公司 Display device and method of fabricating the same

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CN105914213A (en) * 2016-06-01 2016-08-31 深圳市华星光电技术有限公司 Array substrate and preparation method thereof
WO2017206269A1 (en) * 2016-06-01 2017-12-07 深圳市华星光电技术有限公司 Array substrate and preparation method therefor
CN105914213B (en) * 2016-06-01 2019-02-22 深圳市华星光电技术有限公司 Array substrate and preparation method thereof
CN106229346A (en) * 2016-08-31 2016-12-14 深圳市华星光电技术有限公司 Oxide semiconductor thin film transistor and manufacturing method thereof

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