KR20060038076A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on an insulating substrate and an insulating substrate, and is positioned between a source region and a drain region, a source region and a drain region, and a source region and a channel region, and a region between the drain region and the channel region. A semiconductor layer having a lightly doped region, a first insulating layer formed on the semiconductor layer, a gate insulating layer having a second portion having a thickness thinner than the first portion, and a gate insulating layer formed on the first insulating layer. A gate line having a gate electrode positioned to overlap the channel and the lightly doped region, a data line having a source electrode crossing and insulated from the gate line and connected to the source region, and a drain facing the source electrode and electrically connected to the drain region Pixel electrode connected to electrode and drain electrode It includes.

Thin film transistor, low concentration doping area

Description

Thin film transistor array panel and method for manufacturing the same {Thin film transistor array panel and method for manufacturing the same}

As shown in FIG. 1, it is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1;

3A, 4A, 5A, and 7A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A;

6 is a cross-sectional view at the next step of FIG. 5B,

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A;

8 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

9 is a cross-sectional view taken along the line IX-IX'-IX "of FIG. 8,

10A, 11A, 12A, and 13A are layout views in an intermediate step of manufacturing the thin film transistor array panel according to the exemplary embodiments illustrated in FIGS. 8 and 9.

FIG. 10B is a cross-sectional view taken along the line Xb-Xb'-Xb "of FIG. 10A,                 

FIG. 11B is a cross-sectional view taken along the line XIb-XIb′-XIb ″ of FIG. 11A;

12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ of FIG. 12A, and

13A is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of FIG. 13A,

14 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along the line XV-XV ′ of FIG. 14;

FIG. 16 is a cross-sectional view at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 14 and 15.

17A is a layout view at the next step of FIG. 16,

FIG. 17B is a cross-sectional view taken along the line XVIIb-XVIIb ′ of FIG. 17A.

* Description of symbols on the main parts of the drawings *

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

153: source region 154: channel region

155: drain region 171: data line

171a: data metal piece 171b: data connection

173 Source electrode 175 Drain electrode

190: pixel electrode

160, 601, 602: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method for manufacturing the same, and more particularly, to a thin film transistor array panel using polycrystalline silicon as a semiconductor layer and a method for manufacturing the same.

A thin film transistor array panel is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a thin film transistor formed by crossing a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transmitting an image signal, disposed in each pixel, and connected to the gate line and the data line; And a pixel electrode connected to the thin film transistor.

The thin film transistor includes a semiconductor layer forming a channel and a gate electrode which is a part of the gate line, a source electrode which is a part of the data line, and a drain electrode facing the source electrode around the semiconductor layer. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

In this case, the semiconductor layer may be formed of amorphous silicon and crystalline silicon according to the crystal state of silicon. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used for semiconductor layers of switching devices of display devices using glass having a low melting point as a substrate.

Since the polysilicon thin film transistor using polycrystalline silicon as a semiconductor layer has a much higher driving speed than an amorphous silicon thin film transistor, a driving circuit for driving a pixel together with the thin film transistor in the pixel region can be formed on the substrate together with the thin film transistor. have.

However, polysilicon thin film transistors require a low concentration doped region to prevent punch through and the like, and lateral stresses induced in drain junctions are generated when hot concentrations are formed due to hot carriers. Therefore, there is a problem that the characteristics of the thin film transistor are deteriorated.

The present invention provides a thin film transistor array panel having a low concentration doped region capable of minimizing the stress in the lateral direction, and a method of manufacturing the same.

A thin film transistor array panel according to the present invention for achieving the above object is formed on an insulating substrate, an insulating substrate, a channel region, a source region and a channel region and a drain located between the source region and the drain region, the source region and the drain region A semiconductor layer having a lightly doped region located between the region and the channel region, a gate insulating film formed on the semiconductor layer and having a first portion corresponding to the channel region, a second portion having a thickness thinner than the first portion, and a gate insulating film A gate line having a gate electrode formed thereon and positioned over the first portion and overlapping the channel and the lightly doped region, a data line having a source electrode connected to the source region and insulated from and crossing the gate line, facing the source electrode and having a drain Drain electrode, drain electrically connected to area It includes a pixel electrode that is connected with the pole.

The first interlayer insulating layer formed between the drain electrode and the data line and the pixel electrode and the first interlayer insulating layer formed on the first interlayer insulating layer and connected to the drain region through the contact hole formed on the first interlayer insulating layer are formed on the drain electrode. It is preferable to include the pixel electrode which is formed on the 2nd interlayer insulation film and the 2nd interlayer insulation film, and is connected with the drain electrode through the contact hole formed in the 2nd interlayer insulation film.

Alternatively, the data line is formed of the same material on the same layer as the gate line, and is formed on the data metal piece formed between the gate line and a distance away from the gate line, on the interlayer insulating layer covering the gate line, and electrically crossing the source region and the gate line. It is preferable to include a data connection to connect to.

In addition, the first part may be formed of the first and second insulating films, and the second part may be formed of the first insulating film.

At this time, it is preferable that the first insulating film is made of silicon oxide, and the second insulating film is made of silicon nitride.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including: forming a semiconductor layer on an insulating substrate, forming an insulating layer on the semiconductor layer, and etching the insulating layer to a different thickness to form a first portion And forming a gate insulating film having a second portion thicker than the first portion, forming a low concentration doped region by doping the gate insulating layer with a low concentration of conductive impurity ions in the semiconductor layer with a doping mask, and defining a channel region, Forming a gate line having a gate electrode overlapping the first portion on the gate insulating layer, forming a source and a drain region by doping the semiconductor layer with a high concentration of conductive impurity ions in the semiconductor layer using the gate electrode as a mask; Forming a first interlayer insulating film to cover the semiconductor layer, and over the first interlayer insulating film Forming a data line having a source electrode connected to the source region, and forming a pixel electrode electrically connected to the drain region on the first interlayer insulating layer.

The forming of the pixel electrode may include forming a drain electrode connected to the drain region through the first contact hole on the first interlayer insulating layer and a second interlayer having a second contact hole exposing the drain electrode on the drain electrode. And forming an insulating film, wherein the pixel electrode is connected to the drain electrode through the second contact hole.

Alternatively, the forming of the data line may include forming a data metal piece between the gate line and the gate line with a same material on the same layer as the gate line, and connecting the source electrode and electrically connecting the data metal piece across the gate line. It is preferable to include forming a connection.                     

The forming of the gate insulating film may include forming a first insulating film and forming a second insulating film on the first insulating film.

In this case, in the forming of the gate insulating film, it is preferable that the first part is formed of the first and second insulating films, and the second part is formed of the first insulating film by removing the second insulating film.

The first insulating film is preferably formed of silicon oxide, and the second insulating film is preferably formed of silicon nitride.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

1 is a layout view schematically illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 and 2, a blocking film 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and a high concentration of N-type or P-type conductive impurity ions is formed on the blocking film 111. The semiconductor layer 150 including the source region 153 and the drain region 155 and the channel region 154 positioned therebetween is formed.

A low concentration doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 in which the conductive impurity ions are lightly doped.

First and second gate insulating layers 140 and 142 are formed on the semiconductor layer 150. The first gate insulating layer 142 is made of silicon oxide, and the second gate insulating layer 142 is made of silicon nitride. The first gate insulating layer 140 covers the semiconductor layer 150, and the second gate insulating layer 142 corresponds to the channel region 154 and the lightly doped region 152 of the semiconductor layer 150.

A gate line 121 extending in one direction is formed on the substrate 110, and a portion of the gate line 121 extends to overlap the second gate insulating layer 142 corresponding to the channel region 154. A portion of the overlapping gate line 121 is used as the gate electrode 124 of the thin film transistor. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157.

The gate line 121 and the storage electrode line 131 include a conductive film made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy. In addition to the conductive film, other materials, particularly indium tin oxide (ITO) or indium (IZO), may be used. chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and their alloys (eg, molybdenum-tungsten (MoW) alloys) with good physical, chemical and electrical contact properties with zinc oxide). It may have a multilayer film structure including another conductive film. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

Sides of the gate line 121 and the storage electrode line 131 are formed to be tapered, and the tapered shape is formed so that the layers formed thereon can be in close contact with each other.

A first interlayer insulating film 601 made of silicon oxide, silicon nitride, or the like is formed on the gate line 121, the gate electrode 124, the storage electrode 133, and the storage electrode line 131. The first interlayer insulating layer 601 has first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155.

A data line 171 is formed on the interlayer insulating layer 601 to cross the gate line 121 and define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode of the thin film transistor. Used as One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown).

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

The drain electrode 175 and the data line 171 may also be formed of a conductive film such as aluminum (Al) or an aluminum alloy, such as a gate line. In addition to the conductive film, other materials, especially indium tin oxide (ITO), may be used. Or chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and alloys thereof having good physical, chemical and electrical contact properties with indium zinc oxide (IZO). [Molybdenum-tungsten (MoW) alloys ] It may have a multilayer film structure including another conductive film made of such. An example of such a structure is a chromium / aluminum-neodymium (AlNd) alloy. In the case of the double film, the aluminum-based conductive film is preferably positioned below the other conductive film, and in the case of the triple film, the aluminum-based conductive film is preferably positioned as the intermediate layer.

The second interlayer insulating layer 602 is entirely formed on the first interlayer insulating layer 601 on which the first drain electrode 175 and the data line 171 are formed. The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602.                     

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.

3A, 4A, 5A, and 7A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the present invention, and FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A, and FIG. 4B. Is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A, FIG. 5B is a cross-sectional view taken along the line V-V' of FIG. 5A, FIG. 6 is a cross-sectional view at the next step of FIG. 5B, and FIG. 7B is FIG. 7A Sectional view taken along the line VIIb-VIIb 'of FIG.

First, as shown in FIGS. 3A and 3B, the blocking film 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, or sapphire may be used as the transparent insulating substrate 110. The blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 °. do. Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film not doped with impurities is formed to a thickness of 500 kPa or more by a method such as chemical vapor deposition. Preferably it is formed to a thickness of 500 ~ 1,200Å. The amorphous silicon film is then crystallized by ELA (eximer laser annealing) method, furnace annealing method, sequential lateral solidification method (SLS) method, metal induced crystallization method and the like to form a polycrystalline silicon film. Form.

Thereafter, a semiconductor layer 150 made of polycrystalline silicon is formed by patterning the photolithography process using a photomask. The first and second gate insulating layers 140 and 400 are stacked to cover the semiconductor layer 150.

The first gate insulating layer 140 may be formed of silicon oxide, and the second gate insulating layer 400 may be formed of silicon nitride.

Next, as illustrated in FIGS. 4A and 4B, the second gate insulating layer 400 is etched by a photolithography process to form a second gate insulating layer 142 corresponding to a predetermined region of the semiconductor layer 150.

Thereafter, the semiconductor layer 150 is lightly doped with conductive impurity ions using the second gate insulating layer 142 as a mask to form a lightly doped region 152. The semiconductor layer 150 under the second gate insulating layer 142 is not doped and subsequently becomes the channel region 154 of the thin film transistor.

Next, as shown in FIGS. 5A and 5B, a conductive film is formed on the entire surface of the substrate, and then patterned to form a gate line 121 having the gate electrode 124 and a storage electrode line 131 having the storage electrode 133. . In this case, the gate electrode 124 is patterned to cover the second gate insulating layer 142.

Thereafter, the semiconductor layer 150 is heavily doped with conductive impurity ions using the gate electrode 124 and the sustain electrode 133 as a mask to form the source region 153 and the drain region 155. Due to the high concentration doping, the low concentration doped region 152 is reduced to a size corresponding to the width difference between the gate electrode 124 and the second gate insulating layer 142.

The semiconductor layer 150 under the storage electrode 133 may be the storage electrode region 157, and a doped region 150P may be formed due to a pattern difference between the semiconductor layer 150 and the conductive layers 124 and 133. .

Next, as illustrated in FIGS. 6A and 6B, an insulating material is stacked on the entire surface of the substrate 110 including the gate electrode 124 to form a first interlayer insulating layer 601. In this case, the first interlayer insulating layer 601 may be formed of silicon oxide, silicon nitride, or the like.

Subsequently, predetermined regions of the first interlayer insulating layer 601 and the first gate insulating layer 140 are etched to expose the first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively. Form.

Next, a data conductive layer is formed on the first interlayer insulating layer 601 including the first and second contact holes 161 and 162, and then the data line 171 and the drain having the source electrode 173 by a photolithography process. An electrode 175 is formed.

The data line 171 is connected to the source region 153 through the first contact hole 161, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 162.

Next, as shown in FIGS. 7A and 7B, after forming the second interlayer insulating layer 602 on the source electrode 173 and the drain electrode 175, the third contact hole 163 may be etched by a photolithography process. Form.

The second interlayer insulating film 602 has excellent planarization characteristics and is formed of an organic material having photosensitivity, a-Si: C: O, a-Si: formed by plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials such as O: F or silicon nitride, which is an inorganic material.                     

1 and 2, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the inside of the third contact hole 163. Afterwards, the contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line is patterned. The pixel electrode 190 is connected to the drain electrode 175 of the pixel region through the third contact hole 163.

When the second interlayer insulating layer 602 is formed of a low dielectric constant material of 4.0 or less, the pixel electrode 190 may overlap the data line 171 to improve the aperture ratio of the pixel.

Second Embodiment

8 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along the line IX-IX′-IX ″ of FIG. 8.

In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are simultaneously formed, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 8 and 9, the blocking layer 111 is formed on the transparent insulating substrate 110. A semiconductor layer including a source region 153, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor between the conductive layer and the dopant having a high concentration of conductive impurities on the blocking layer 111. 150 is formed. In addition, conductive impurities are doped at a lower concentration than the source and drain regions 153 and 155 between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150. It is.

The first gate insulating layer 140 covering the semiconductor layer 150, the lightly doped region 152 of the semiconductor layer 150, and the second gate insulating layer 142 corresponding to the channel region 154 are disposed on the semiconductor layer 150. Formed.

A gate line 121 extending in one direction is formed on the first and second gate insulating layers 140 and 142, and a portion of the gate line 121 extends to correspond to the channel region 154. ) And a portion overlap and serve as the gate electrode 124. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157.

The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. In addition, the data metal piece 171a may enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).                     

The gate line 121 and the data metal piece 171a include a conductive film made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, and in addition to the conductive film, other materials, particularly indium tin oxide (ITO) or indium (IZO) chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo) and their alloys (eg, molybdenum-tungsten (MoW) alloys) with good physical, chemical and electrical contact properties with zinc oxide). It may have a multilayer film structure including another conductive film. An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

An interlayer insulating layer 160 is formed to cover the gate line 121 and the storage electrode line 131. The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 made of ITO or IZO, which is a transparent conductive material, are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 and the storage electrode line 131 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121 and the storage electrode line 131. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate line 121 and the data metal piece 171a, respectively.                     

The contact auxiliary member 82 is not essential to serve to protect adhesion between the end of the data line 171a and the external device and to protect them, and application thereof is optional.

A method of manufacturing the thin film transistor array panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 8 and 9 described with reference to FIGS. 10A to 13B.

10A, 11A, 12A, and 13A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 10B is along the line Xb-Xb'-Xb "of FIG. 10A. 11B is a cross-sectional view taken along the line XIb-XIb'-XIb "in FIG. 11A, and FIG. 12B is a cross-sectional view taken along the line XIIb-XII'-XII" in FIG. 12A, and XIIIb-XIIIb in FIG. 13A. A cross section taken along the line '-XIIIb'.

First, as shown in FIGS. 10A and 10B, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. . Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film not doped with impurities is formed to a thickness of 500 kPa or more by a method such as chemical vapor deposition. Preferably it is formed to a thickness of 500 ~ 1,200Å. Then, the amorphous silicon film is crystallized by ELA method, furnace heat treatment method, SLS method, MIC method and the like to form a polycrystalline silicon film.

Thereafter, the polycrystalline silicon film is photo-etched using a photomask to form a semiconductor layer 150 made of polycrystalline silicon. The first and second gate insulating layers 140 and 400 are stacked to cover the semiconductor layer 150. The first gate insulating layer 140 may be formed of silicon oxide, and the second gate insulating layer 400 may be formed of silicon nitride.

First, as illustrated in FIGS. 11A and 11B, the second gate insulating layer 400 is etched by a photolithography process to form a second gate insulating layer 142 corresponding to a predetermined region of the semiconductor layer 150. The semiconductor layer 150 is lightly doped with conductive impurity ions using the second gate insulating layer 142 as a mask to form a lightly doped region 152. In this case, the lightly doped region 152 is a channel region 154 of the thin film transistor.

Next, as shown in FIGS. 12A and 12B, after the conductive film is deposited on the entire surface of the substrate, the gate electrode 121 having the gate electrode 124 and the storage electrode line 131 having the storage electrode 133 are formed by a photolithography process. And the data metal piece 171a is formed. The gate electrode 124 is patterned to cover the second gate insulating layer 142.

Sides of the gate line 121, the storage electrode line 131, and the data metal piece 171a are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Next, the semiconductor layer 150 is heavily doped with conductive impurity ions using the gate electrode 124 and the storage electrode 133 as a mask to form source and drain regions 153 and 155. Due to the high concentration doping, the low concentration doped region 152 is reduced to a size corresponding to the width difference between the gate electrode 124 and the second gate insulating layer 142.

The semiconductor layer 150 under the storage electrode 133 may be the storage electrode region 157, and a doped region 150P may be formed due to a pattern difference between the semiconductor layer 150 and the conductive layers 124 and 133. .

Next, as shown in FIGS. 13A and 13B, an interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

Next, as shown in FIGS. 8 and 9, a conductive film is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. And the pixel electrode 190 and the contact assistant member 82.

Here, the data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line 121 and the data metal piece 171b to improve the aperture ratio of the pixel region.

Third Embodiment

In the above-described embodiment, the gate insulating film is formed in double, but the gate insulating film may be formed in a single layer. When the gate insulating film is formed in a single layer, the insulating film forming process time can be saved more than when forming a double layer.

FIG. 14 is a layout view of a thin film transistor array panel according to a third exemplary embodiment of the present invention, and FIG. 15 is a cross-sectional view taken along the line XV-XV ′ of FIG. 14.

As shown in Figs. 14 and 15, most of the interlayer structures are the same as in the first embodiment. However, in the third embodiment, the gate insulating layer 140 is formed of a single layer. The gate insulating layer 140 has a first portion A corresponding to the channel region 154 and a second portion B formed at a portion except the channel region 154. The first portion A is formed thicker than the second portion B.

The manufacturing method thereof will be described in detail with reference to FIGS. 16 to 17B and FIGS. 3A to 5B, 14 and 15.

FIG. 16 is a cross-sectional view at an intermediate stage in the method of manufacturing a thin film transistor array panel according to the present invention, FIG. 17A is a layout view at a next step in FIG. 16, and FIG. 17B is a cross-sectional view taken along the line XVIIb-XVIIb ′ of FIG. 17A. to be.

First, as shown in FIGS. 3A and 3B, the blocking film 111 and the semiconductor layer 150 are formed on the transparent insulating substrate 110.

16, the gate insulating layer 140 is formed to cover the semiconductor layer 150. The gate insulating layer 140 is preferably formed of silicon oxide or silicon nitride. Thereafter, the gate insulating layer 140 is removed by a predetermined thickness by a photolithography process using an optical mask so that the gate insulating layer 140 has the first and second portions A and B. FIG.

Thereafter, the semiconductor layer 150 is lightly doped with conductive impurity ions using a gate insulating layer 140 having a different thickness to form a lightly doped region 152. The semiconductor layer 150 under the first portion A is not doped and subsequently becomes the channel region 154 of the thin film transistor.

Next, as shown in FIGS. 17A and 17B, a conductive film is formed on the entire surface of the substrate and then patterned to form a gate line 121 having the gate electrode 124 and a storage electrode line 131 having the storage electrode 133. . In this case, the gate electrode 124 is patterned to cover the first portion A of the gate insulating layer 140.

Thereafter, the semiconductor layer 150 is heavily doped with conductive impurity ions using the gate electrode 124 and the sustain electrode 133 as a mask to form the source region 153 and the drain region 155. Due to the high concentration doping, the low concentration doped region 152 is reduced to a size corresponding to the width difference between the gate electrode 124 and the first portion A of the gate insulating layer 140.

The semiconductor layer 150 under the storage electrode 133 may be the storage electrode region 157, and a doped region 150P may be formed due to a pattern difference between the semiconductor layer 150 and the conductive layers 124 and 133. .

Subsequent processes proceed in the same manner as FIGS. 6A to 7B of the first embodiment, and as shown in FIGS. 14 and 15, a transparent material on the second interlayer insulating layer 602 including the inside of the third contact hole 163. Phosphorus indium tin oxide (ITO), indium zinc oxide (IZO), etc. are deposited and then patterned to form a contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or data line. do. The pixel electrode 190 is connected to the drain electrode 175 of the pixel region through the third contact hole 163.

When the second interlayer insulating layer 602 is formed of a low dielectric constant material of 4.0 or less, the pixel electrode 190 may overlap the data line 171 to improve the aperture ratio of the pixel.

Although not described in a separate embodiment, the gate insulating layer 140 may be formed as a single layer in the structure of the second embodiment as in the third embodiment.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the double gate insulating layer or the gate insulating layer having different thicknesses is used, the thin film transistor array panel covering the low concentration doped region may be easily formed. Accordingly, a high quality thin film transistor array panel capable of reducing lateral stresses between the source and drain regions and the gate electrode may be provided.

Claims (11)

Insulation board, A semiconductor formed on the insulating substrate and having a source region and a drain region, a channel region located between the source region and a drain region, a source region and a channel region, and a lightly doped region located between the drain region and the channel region layer, A gate insulating layer formed on the semiconductor layer and having a first portion corresponding to a channel region and a second portion having a thickness thinner than that of the first portion, A gate line formed on the gate insulating layer and having a gate electrode disposed on the first portion and overlapping the channel and the lightly doped region, A data line insulated from and intersecting the gate line and having a source electrode connected to the source region; A drain electrode facing the source electrode and electrically connected to the drain region, A pixel electrode connected to the drain electrode Thin film transistor array panel comprising a. In claim 1, A first interlayer insulating film formed between the drain electrode and the data line and the pixel electrode; A drain electrode formed on the first interlayer insulating layer and connected to the drain region through a contact hole formed in the first interlayer insulating layer; A second interlayer insulating film formed on the drain electrode, And a pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode through a contact hole formed in the second interlayer insulating layer. In claim 1, The data line is formed of the same material on the same layer as the gate line and is formed between the gate line and a distance from the gate line; And a data connection part formed on the interlayer insulating layer covering the gate line and electrically connecting the data metal piece across the source region and the gate line. The method according to any one of claims 1 to 3, The first portion is composed of first and second insulating films, The second portion is a thin film transistor array panel made of a first insulating film. In claim 4, The first insulating film is made of silicon oxide, The second insulating film is a thin film transistor array panel made of silicon nitride. Forming a semiconductor layer on the insulating substrate, Forming an insulating film on the semiconductor layer, Etching the insulating film partially to a different thickness to form a gate insulating film having a first portion and a second portion thicker than the first portion, Forming a low concentration doped region by doping the semiconductor layer with a low concentration of conductive impurity ions in the semiconductor layer using a doping mask, and defining a channel region; Forming a gate line on the gate insulating layer, the gate line having a gate electrode overlapping the first portion; Doping the semiconductor layer with a high concentration of conductive impurity ions using the gate electrode as a mask to form source and drain regions; Forming a first interlayer insulating film to cover the gate line and the semiconductor layer; Forming a data line having a source electrode connected to the source region on the first interlayer insulating layer; Forming a pixel electrode electrically connected to the drain region on the first interlayer insulating layer Method of manufacturing a thin film transistor array panel comprising a. In claim 6, Forming the pixel electrode, Forming a drain electrode on the first interlayer insulating layer, the drain electrode being connected to the drain region through a first contact hole; Forming a second interlayer insulating film having a second contact hole exposing the drain electrode over the drain electrode, The pixel electrode is formed to be connected to the drain electrode through the second contact hole. In claim 6, Forming the data line, Forming a data metal piece between the gate line and the gate line by the same material on the same layer as the gate line, And forming a data connection part connected to the source electrode and electrically connecting the data metal piece across the gate line. The compound according to any one of claims 7 to 8, The gate insulating film forming step may include forming a first insulating film; And forming a second insulating film on the first insulating film. In claim 9, And forming the gate insulating layer, wherein the first portion is formed of the first and second insulating layers, and the second portion is formed of the first insulating layer by removing the second insulating layer. In claim 9, The first insulating film is formed of silicon oxide, And the second insulating film is formed of silicon nitride.

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