KR100992126B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

       The thin film transistor array panel according to the present invention includes an insulating substrate, a barrier layer formed on the insulating substrate and heavily doped with a first conductivity type impurity, a source region formed on the barrier layer and heavily doped with a second conductivity type impurity; A semiconductor layer having a drain region, a source region and a drain region doped with a doped channel region, a gate insulating layer formed on the semiconductor layer, a gate line formed on the gate insulating layer and having a gate electrode overlapping the channel region, A first interlayer insulating film formed on the gate line and having first and second contact holes exposing the source and drain regions, respectively, and a source electrode formed on the first interlayer insulating film and connected to the source region through the first contact hole. And a drain region formed on the data line and the interlayer insulating layer through the second contact hole. The drain electrode is formed on the result, the data line and the drain electrode are formed over the second interlayer insulating film, the second interlayer insulating film having a third contact hole that exposes the drain electrode includes a pixel electrode connected to the drain electrode.

       Thin Film Transistors, LDDs, Electronic Barriers

Description

Thin film transistor array panel and manufacturing method thereof

       1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

       FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ',

       3A, 4A, 6A, and 7A are layout views illustrating a method of manufacturing a thin film transistor array panel according to a first embodiment of the present invention according to a process sequence thereof.

       3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

       4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

       5 is a cross-sectional view at the next step of FIG. 4B,

       FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

       FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A;

       8 is a layout view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

       FIG. 9 is a cross-sectional view taken along the line IX-IX ′ of FIG. 8;

       10A, 11A, and 13A are layout views showing a method of manufacturing a thin film transistor array panel according to a second embodiment of the present invention according to a process sequence thereof;

       FIG. 11B is a cross-sectional view taken along the line XIb-XIb′-XIb ″ of FIG. 11A;

       12 is a sectional view at the next step of FIG. 11b,

       FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb ″ of FIG. 13A.

       ※ Explanation of symbols on main parts of drawing ※

       110: insulating substrate 111: blocking film

       112: barrier layer 121: gate line

       124: gate electrode 131: sustain electrode line

       133 sustain electrode 140 gate insulating film

       150: semiconductor layer 153: source region

       154: channel region 155: drain region

       171: data line 173: source electrode

       175: drain electrode 190: pixel electrode

       BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method of manufacturing the same, and more particularly, to a thin film transistor array panel using polycrystalline silicon as a semiconductor layer and a method of manufacturing the same.

       A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor array panel includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transferring an image signal, and includes a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like. It is included.

       The thin film transistor includes a semiconductor layer forming a channel and a gate electrode connected to the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode with respect to the semiconductor layer. The thin film transistor is a switching element that controls an image signal transmitted to a pixel electrode through a data line according to a scan signal transmitted through a gate line.

       In this case, the semiconductor layer may be made of amorphous silicon, polycrystalline silicon, or the like, and the thin film transistor may be divided into a top gate method and a bottom gate method according to a relative position with the gate electrode. In the case of a polysilicon thin film transistor array panel, a top gate method in which a gate electrode is located above the semiconductor layer is mainly used.

       The top gate method has a merit of forming a driving circuit for operating the thin film transistor together with the thin film transistor because the driving speed of the thin film transistor is much faster than that of the bottom gate method.

       However, there is a problem in that the hot carrier of the semiconductor layer escapes to the blocking film and the like, thereby causing a decrease in channels, thereby degrading the characteristics of the semiconductor layer. In order to prevent such a phenomenon, the reduction phenomenon can be minimized by doping heavy ions to the semiconductor layer adjacent to the blocking layer. However, the semiconductor layer formed in the thin film transistor is formed to have an electron barrier formed by ion implantation of 500 Å or more. it's difficult.

       The present invention for solving the above problems provides a thin film transistor array panel and a method of manufacturing the same that can easily form an electronic barrier to minimize the reduction of the channel.

       A thin film transistor array panel according to the present invention for achieving the above object is formed on an insulating substrate, an insulating substrate, a barrier layer doped with a high concentration of the first conductivity type impurities, a barrier layer formed on the barrier layer, the second conductivity type impurities are high concentration A semiconductor layer having a source region and a drain region doped with a semiconductor region and a channel region which is not doped with impurities, a gate insulating layer formed on the semiconductor layer, and formed on the gate insulating layer and overlapping the channel region. A first interlayer insulating film having a first and second contact holes formed on the gate line and a gate line having a gate electrode and exposing a source region and a drain region, respectively, and formed on the first interlayer insulating film and through the first contact hole A data line having a source electrode connected to the data line and formed on the interlayer insulating layer; A second interlayer insulating layer formed on the drain electrode, the data line and the drain electrode connected to the drain region through the urging and having a third contact hole exposing the drain electrode, and a pixel formed on the second interlayer insulating layer and connected to the drain electrode An electrode.

       Another thin film transistor array panel according to the present invention for achieving the above object is formed on an insulating substrate, an insulating substrate and formed on the barrier layer, the barrier layer in which the first conductivity type impurities are heavily doped, and the second conductivity type impurities are A semiconductor layer having a heavily doped source region, a drain region, and a channel region not doped with impurities, a gate insulating film formed over the semiconductor layer, a gate line formed over the gate insulating film and partially overlapping the channel region, and a neighboring gate line Interposed between the data metal piece, the interlayer insulating film formed on the data line, the gate line, and the data metal piece, which are positioned at a predetermined distance apart from each other and are perpendicular to the gate line, and electrically connect the data metal piece through the contact hole while crossing the gate line. Data connection, interlayer insulation Formed on and comprises a pixel electrode that is connected through the contact hole and the drain region.

       It is preferable to further include a blocking film formed on the front surface of the substrate and positioned below the barrier layer.

       In addition, it is preferable to further include a low concentration doped region formed between the drain region and the channel region between the source region and the channel region and doped with low concentration of the second conductivity type impurities.

       In this case, the gate line preferably overlaps with the lightly doped region.

       The first conductivity type impurity is a P type conductivity impurity and the second conductivity type impurity is an N type conductivity impurity.

       According to another aspect of the present invention, a method of manufacturing a thin film transistor array panel includes forming a first amorphous silicon film doped with a first conductivity type impurity on an insulating substrate, and wherein the impurities are not doped on the first amorphous silicon film. Forming a non-crystalline second amorphous silicon film, crystallizing and patterning the first and second amorphous silicon films to form a polycrystalline silicon pattern, forming a gate insulating film over the polycrystalline silicon pattern, forming a gate insulating film over the gate insulating film, and a portion of the polycrystalline silicon pattern Forming an overlapping gate line; forming a semiconductor layer having a source region, a channel region, and a drain region by doping a high concentration of a second conductivity type impurity in a predetermined region of the polysilicon pattern using the gate line as a mask; Forming a first interlayer insulating film to cover the layer, wherein the source region and the source region Forming a drain electrode connected to the data line and the drain region having a source electrode connected thereto, forming a second interlayer insulating film on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode on the second interlayer insulating film It includes a step.

       Another method of manufacturing the thin film transistor array panel according to the present invention for achieving the above object is to form a first amorphous silicon film doped with a first conductivity type impurity on an insulating substrate, and dopants are not doped on the first amorphous silicon film. Forming a non-crystalline second amorphous silicon film, crystallizing and patterning the first and second amorphous silicon films to form a polycrystalline silicon pattern, forming a gate insulating film over the polycrystalline silicon pattern, forming a gate insulating film over the gate insulating film, and a portion of the polycrystalline silicon pattern Forming a data metal piece spaced apart from the overlapping gate line and gate line by a predetermined distance, and using a gate line as a mask to dope a predetermined amount of the second conductivity type impurity in a predetermined region of the polycrystalline silicon pattern to obtain a source region, a channel region, and a drain. Forming a semiconductor layer having a region, the interlayer insulating film covering the semiconductor layer Forming a pixel electrode having a source electrode connected to the source region on the interlayer insulating layer, a data connection portion connected to the data metal piece, and a pixel electrode connected to the drain region.

       The method may further include forming a blocking film on the insulating substrate.

       The first conductivity type impurity is a P type conductivity impurity and the second conductivity type impurity is an N type conductivity impurity.

       DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

       In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.                     

       Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

       [First Embodiment]

       1 is a layout view of a display area of a thin film transistor array panel for explaining an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

       As illustrated, a blocking film 111 is formed on the transparent insulating substrate 110. The semiconductor layer 150 including the source region 153, the drain region 155, and the channel region 154 is formed on the blocking layer 111. A lightly doped drain 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154.

       The lightly doped region 152 prevents leakage current or punch through. The source region 153 and the drain region 155 are heavily doped with N-type impurities, and the lightly doped region 152 is doped with N-type impurities at low concentration. In addition, the channel region 154 is in an intrinsic semiconductor state in which impurities are not doped.

       A barrier layer 112 is formed between the blocking film 111 and the semiconductor layer 150. P-type conductive impurities are heavily doped in the barrier layer 112 to act as an electron barrier of the N-type channel formed between the source region 153 and the drain region 155, thereby generating hot carriers (hot) generated in the channel. The carrier may be prevented from escaping to the blocking layer 111.                     

       A gate insulating layer 140 made of silicon oxide or the like is formed on the semiconductor layer 150. In addition, a gate line 121 extending in one direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154 of the semiconductor layer 150. The portion overlapping the channel region 154 is used as the gate electrode 124 of the thin film transistor, and may also overlap (not shown) the lightly doped region 152.

       In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

       The first interlayer insulating layer 601 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

       A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode (eg, a thin film transistor). 173). One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit.

       A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

       A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 163 exposing the drain electrode 175.

       The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 163.

       A method of manufacturing the thin film transistor array panel according to the first embodiment of the present invention described above will be described in detail with reference to FIGS. 1 and 2 described above with reference to FIGS. 3A to 7B.

       3A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention, FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A, and FIG. 4A is a next step of FIG. 3A. 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A, FIG. 5 is a cross-sectional view at the next step of FIG. 4B, FIG. 6A is a layout view at the next step of FIG. 5, and FIG. 6B 6A is a cross-sectional view taken along the line VIb-VIb 'of FIG. 6A, FIG. 7A is a layout view of the next step of FIG. 6A, and FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb' of FIG. 7A.

       First, as illustrated in FIGS. 3A and 3B, the blocking layer 111 is formed by depositing silicon oxide (SiO 2) or silicon nitride (SiN x) on the transparent insulating substrate 110.

Thereafter, an amorphous silicon film doped with impurities and an amorphous silicon film not doped with impurities are sequentially stacked using a plasma chemical vapor deposition apparatus. The amorphous silicon film doped with impurities is doped with a P-type conductive impurity, for example, boron (B) or the like at a high concentration. Since P-type impurities are injected in the form of B ₂ H ₆ and contain a large amount of hydrogen, hydrogen is removed by a dehydrogenation process in a nitrogen atmosphere. At this time, hydrogen of the amorphous silicon film that is not doped with impurities may also be removed.

       The amorphous silicon film is formed to a thickness of 400 ~ 600Å, wherein the amorphous silicon film doped with impurities is formed to less than 100Å.

       Thereafter, the amorphous silicon film is crystallized by laser annealing, furnace annealing, or SLS (sequential lateral solidification), and then patterned by photolithography to form a polysilicon pattern 150A and a barrier layer 112. .

       As shown in FIGS. 4A and 4B, an insulating material such as silicon nitride or silicon oxide is deposited on the polycrystalline silicon pattern 150A by chemical vapor deposition to form a gate insulating layer 140. Thereafter, titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is deposited on the gate insulating layer 140 to form a metal film.

       Then, after the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. In this case, the metal film is patterned using the photoresist pattern as a mask to form the gate line 121 and the storage electrode line 131. When the storage capacitor is sufficient, the storage electrode line 131 and the storage electrode 133 are not formed. Here, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photosensitive film pattern PR.

       Side surfaces of the gate line 121 and the storage electrode line 131 are formed to be tapered to increase adhesion to the upper layer.

       Then, the semiconductor layer 150 having the source and drain regions 153 and 155 is formed by doping N-type impurities such as P and As in the polycrystalline silicon pattern 150A with high concentration using the photoresist pattern PR as a mask. .

       Next, as shown in FIG. 5, after removing the photoresist pattern PR, the semiconductor layer 150 is lightly doped with N-type impurities using the gate line 121 and the storage electrode line 131 as a mask to form a low concentration doped region 152. The semiconductor layer 150 having () is completed.

       The semiconductor layer positioned between the source region 153 and the drain region 155 becomes the channel region 154 of the thin film transistor.

       As described above, the lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern, or by forming spacers or the like on sidewalls of the gate lines.

       6A and 6B, a first interlayer insulating layer 601 is formed on the entire surface of the substrate 110 and etched by a photolithography process to expose the source and drain regions 153 and 155. The contact holes 161 and 162 are formed.                     

       The interlayer insulating layer 160 has excellent planarization characteristics, and is formed of a-Si: C: O, a-Si: O: organic material having photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials, such as F, or an inorganic material, such as silicon nitride can be formed.

       Next, tungsten, titanium, aluminum, or an alloy thereof is deposited on the first interlayer insulating film in a single layer or a plurality of layers to form a metal film. Subsequently, the metal film is patterned by a photolithography process to form a data line 171 and a drain electrode 175 having source electrodes 173 connected to the source and drain regions, respectively, through the contact holes 161 and 162.

       Sidewalls of the data line 171 and the drain electrode 175 may be formed to be tapered to improve adhesion to the upper layer.

       As shown in FIGS. 7A and 7B, a second interlayer insulating layer 602 covering the data line 171 and the drain electrode 175 is formed. Thereafter, the second interlayer insulating layer 602 is patterned by a photolithography process to form a third contact hole 163 exposing the drain electrode 175.

       The second interlayer insulating film 601 may also be formed of the same material as the first interlayer insulating film 160.

       1 and 2, a transparent conductive film such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like is formed on the second interlayer insulating film, and then patterned and drained through the third contact hole 163. The pixel electrode 190 connected to the electrode 175 is formed.

       When the second interlayer insulating layer 602 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the data line and the gate line to improve the aperture ratio of the pixel region.

       As described above, the P-type barrier layer 112 formed between the N-type semiconductor layer 150 and the blocking film 111 acts as an electron barrier of the N-type channel to form a hot portion of the channel formed between the source region and the drain region. The carrier exits the barrier and the channel is not reduced.

       Second Embodiment

       FIG. 8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line IX-IX′-IX of FIG. 8.

       In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are formed at the same time, the number of masks can be reduced as compared with the first embodiment.

       More specifically, as shown in FIGS. 8 and 9, the blocking layer 111 is formed on the transparent insulating substrate 110, and the source region 153, the drain region 155, and the channel region 154 are formed on the transparent insulating substrate 110. ) And the lightly doped region 152 is formed. The barrier layer 112 is formed between the semiconductor layer and the blocking layer 111.

       The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150. A gate line 121 extending in the horizontal direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends in the vertical direction to partially overlap the semiconductor layer 150, and overlaps the semiconductor layer 150. A portion of the gate lines 121 and 124 is used as the gate electrode 124.

       One end of the gate line 121 may be formed larger than the width of the gate line 121 to receive a scan signal from an external circuit (not shown).

       In addition, the storage electrode line 131 is formed in the same layer with the same material as the gate line 121 so that the storage electrode line 131 is formed to be parallel to the gate line 121 and is positioned in parallel. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 disposed under the storage electrode 133 becomes the storage electrode region 157.

       The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is formed not to be connected to the gate lines 121 and 124 between two adjacent gate lines 121 and 124. In addition, the data metal piece 171a may enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).

       An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate lines 121 and 124 and the storage electrode lines 131 and 133.

       The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate lines 121 and 124 and the storage electrode lines 131 and 133 in the vertical direction.                     

       The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate lines 121 and 124 and the storage electrode lines 131 and 133. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate lines 121 and 124 and the data metal piece 171a, respectively.

       The contact auxiliary member 82 is connected to the end of the data metal piece 171a through the contact hole 162. The contact auxiliary member 82 is not essential to serve to protect the adhesion between the end of the data metal piece 171a and the external device and to protect them, and application thereof is optional. In particular, when the driving circuit is formed together with the thin film transistor in the display area, it is not formed.

       A method of manufacturing the thin film transistor array panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 8 and 9 previously described with reference to FIGS. 10A to 13B.

       FIG. 10A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along the line Xb-Xb'-Xb 'of FIG. 10A, and FIG. FIG. 11B is a cross-sectional view taken along the line XIb-XIb′-XIb ″ in FIG. 11A, FIG. 12A is a layout in the next step of FIG. 11A, and FIG. 12B is the XIIb-XIIb in FIG. 11A. 13A is a layout view of the next step of FIG. 12A, and FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of FIG. 13A. As shown in FIGS. 10A and 10B, the blocking film 111 is formed by depositing silicon oxide (SiO 2) or silicon nitride (SiN x) on the transparent insulating substrate 110.

       Subsequently, an amorphous silicon film doped with impurities and an amorphous silicon film not doped with impurities are sequentially stacked using a plasma chemical vapor deposition apparatus. The amorphous silicon film doped with impurities is doped with a P-type conductive impurity, for example, boron (B) or the like at a high concentration.

Since the P-type impurity may be injected in the form of B ₂ H ₆ , a large amount of hydrogen may be included in the amorphous silicon film, and thus hydrogen is removed by a dehydrogenation process in a nitrogen atmosphere.

       The amorphous silicon film is crystallized by laser heat treatment, furnace heat treatment, and SLS, and then patterned to form the polycrystalline silicon pattern 150 and the barrier layer 112.

       As illustrated in FIGS. 11A and 11B, an insulating material such as silicon nitride or silicon oxide is deposited on the polycrystalline silicon pattern 150 by chemical vapor deposition to form a gate insulating layer 140. Thereafter, titanium, aluminum, tungsten, or an alloy thereof is deposited on the gate insulating layer 140 in a single layer or a plurality of layers to form a metal layer.

       Then, after the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. In this case, the metal film is patterned using the photoresist pattern PR to form the gate lines 121 and 124, the storage electrode lines 131 and 133, and the data metal piece 171a. When the storage capacitor is sufficient, the storage electrode line 131 and the storage electrode 133 are not formed. Here, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photosensitive film pattern PR.

       Then, the semiconductor layer 150 having the source and drain regions 153 and 155 is formed by doping the polycrystalline silicon pattern 150 with N-type impurities, for example, P and As, using the photoresist pattern PR as a mask. .

       Next, as shown in FIG. 12, after the photoresist pattern PR is removed, the semiconductor layer 150 is lightly doped with N-type impurities using the gate lines 121 and 124 as a mask to include a low concentration doped region 152. The semiconductor layer 150 is completed.

       In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

       The polysilicon pattern positioned between the source region 153 and the drain region 155 becomes the channel region 154 which is not doped with impurities.

       As described above, the lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern, or by forming spacers or the like on sidewalls of the gate lines.                     

       As shown in FIGS. 13A and 13B, the interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

       Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The fourth contact hole 164 exposing one end portion of the third contact hole 163, the gate lines 121 and 124, and the data metal piece 171a is formed.

       When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

       8 and 9, a conductive layer is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. And the pixel electrode 190 and the contact assistant member 82.

       The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

       In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line and the data metal piece to improve the aperture ratio of the pixel region.

       As described above, by forming a barrier layer doped with a conductive impurity opposite to the conductive impurity doped in the source region and the drain region under the semiconductor layer, it is used as an electron barrier of the channel so that the hot carrier of the channel is formed. It can be prevented from exiting to the barrier.

       Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As described above, when the barrier layer is formed between the semiconductor layer and the blocking film, hot carriers of the semiconductor layer do not flow into the blocking film due to the barrier layer. Therefore, it is possible to minimize the deterioration of the characteristics of the thin film transistor due to the reduction of the channel.

Claims (10)

Insulation board, A blocking film formed on the insulating substrate, A barrier layer formed on the blocking layer and doped with a high concentration of a first conductivity type impurity, A semiconductor layer formed on the barrier layer and having a source region and a drain region, and a channel region located between the source region and the drain region; A gate insulating film formed on the semiconductor layer, A gate line formed on the gate insulating layer and having a gate electrode overlapping the channel region; A first interlayer insulating layer formed on the gate line and having first and second contact holes exposing source and drain regions, respectively; A data line formed on the first interlayer insulating layer and having a source electrode connected to the source region through the first contact hole; A drain electrode formed on the interlayer insulating layer and connected to the drain region through the second contact hole; A second interlayer insulating layer formed on the data line and the drain electrode and having a third contact hole exposing the drain electrode; A pixel electrode formed on the second interlayer insulating layer and connected to the drain electrode Including, And a second conductive dopant in a high concentration in the source region and the drain region. Insulation board, A blocking film formed on the insulating substrate, A barrier layer formed on the blocking layer and doped with a high concentration of a first conductivity type impurity, A semiconductor layer formed on the barrier layer and having a source region and a drain region, and a channel region located between the source region and the drain region, A gate insulating film formed on the semiconductor layer, A gate line formed on the gate insulating layer and overlapping the channel region; A data metal piece positioned a predetermined distance apart from the neighboring gate lines and extending in a direction perpendicular to the gate line; An interlayer insulating film formed on the gate line and the data metal piece, A data connection part formed on the interlayer insulating film and crossing the gate line to electrically connect the data metal piece through a contact hole; A pixel electrode formed on the interlayer insulating layer and connected to the drain region through a contact hole; And a second conductive dopant in a high concentration in the source region and the drain region.   The method of claim 1 or 2,   And the barrier layer is a crystallized silicon layer.        The method of claim 1 or 2,        And a lightly doped region formed between the source region and the channel region between the drain region and the channel region, and lightly doped with a second conductivity type impurity.        In claim 4,        The gate line overlaps the lightly doped region.        The method of claim 1 or 2,        The first conductivity type impurity is a P type conductivity impurity, and the second conductivity type impurity is an N type conductivity type impurity panel. Forming a blocking film made of silicon nitride on the insulating substrate, Forming a first amorphous silicon film doped with a first conductivity type impurity on the blocking film; Forming a second amorphous silicon film on the first amorphous silicon film, Crystallizing and patterning the first amorphous silicon film and the second amorphous silicon film to form a polycrystalline silicon pattern and a barrier layer, respectively; Forming a gate insulating film on the polycrystalline silicon pattern, Forming a gate line overlapping the polycrystalline silicon pattern on the gate insulating layer; Forming a semiconductor layer having a source region, a channel region, and a drain region by doping a high concentration of a second conductivity type impurity in the polycrystalline silicon pattern using the gate line as a mask; Forming a first interlayer insulating film to cover the semiconductor layer, Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer. Forming a first amorphous silicon film doped with a first conductivity type impurity on the insulating substrate, Forming a second amorphous silicon film on the first amorphous silicon film, Crystallizing and patterning the first amorphous silicon film and the second amorphous silicon film to form a polycrystalline silicon pattern and a barrier layer, respectively; Forming a gate insulating film on the polycrystalline silicon pattern, Forming a gate line overlapping the polysilicon pattern and a data metal piece spaced apart from the gate line on the gate insulating layer; Forming a semiconductor layer having a source region, a channel region, and a drain region by doping a high concentration of a second conductivity type impurity in the polycrystalline silicon pattern using the gate line as a mask; Forming an interlayer insulating film to cover the semiconductor layer; And forming a data connection part connecting the data metal piece across the source region and the gate line and a pixel electrode connected to the drain region on the interlayer insulating layer. delete In claim 7 or 8, The first conductivity type impurity is a P type conductivity impurity, And the second conductivity type impurity is an N type conductivity impurity.

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