KR100870017B1 - Method of fabricating for thin film transistor array panel - Google Patents

Abstract

The method for manufacturing a thin film transistor substrate according to the present invention comprises the steps of laminating an amorphous silicon layer on an insulating substrate, crystallizing the amorphous silicon layer, and then patterning to form a polycrystalline silicon layer, a gate insulating layer, a conductive layer on the polycrystalline silicon layer Laminating a layer and a photosensitive layer, patterning the photosensitive layer to form a photosensitive layer pattern, etching the conductive layer using the photosensitive layer pattern as a mask to form a gate wiring having a predetermined width smaller than the photosensitive layer pattern, and Forming a source region doped with n-type or p-type impurities, a drain region, or a channel region not doped with impurities in the polysilicon layer using the layer pattern as a mask; after removing the photosensitive layer pattern, the gate wiring is used as a mask for the impurities Doping to form a low concentration impurity region, forming a first interlayer insulating layer over the gate wiring, and forming a first interlayer Forming a first contact hole exposing the source region and a second contact hole exposing the drain region in the insulating layer, and forming a data line and a second contact hole connected to the source region through the first contact hole on the first interlayer insulating layer. Forming a data line including a drain electrode connected to the drain region through the data line, forming a second interlayer insulating layer on the data line, and forming a third contact hole exposing the drain electrode on the second interlayer insulating layer And forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating layer.

Thin Film Transistor Board, LDD

Description

The manufacturing method of a thin film transistor substrate {METHOD OF FABRICATING FOR THIN FILM TRANSISTOR ARRAY PANEL}

1A to 1F illustrate a method of manufacturing a thin film transistor substrate according to the prior art, in the order of a process.

2 is a cross-sectional view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

3A to 3G are views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention according to a process sequence.

4 is a cross-sectional view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

5A through 5E are views illustrating a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention, in the order of a process.

※ Explanation of symbols on main parts of drawing ※

110: insulating substrate 111: blocking layer

123: gate electrode 140: gate insulating layer

150 polycrystalline silicon layer 152 lightly doped region

153: source region 154: channel region

155: drain region 171: data line

175: drain electrode 190: pixel electrode                 

204: barrier layer

The present invention relates to a method for manufacturing a thin film transistor substrate.

In general, a thin film transistor substrate (TFT) has a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transferring an image signal, and is connected to the gate line and the data line. The transistor includes a transistor, a pixel electrode connected to the thin film transistor, a gate insulating layer covering and insulating the gate wiring, and an interlayer insulating layer covering and insulating the thin film transistor and the data wiring.

Such a thin film transistor may be formed using polycrystalline silicon or amorphous silicon, and when using polycrystalline silicon, field mobility becomes larger than when using amorphous silicon. May occur. Therefore, when the thin film transistor is formed using polycrystalline silicon, a lightly doped region is formed in the polycrystalline silicon layer positioned between the source region, the gate electrode, the drain region, and the gate electrode to reduce the leakage current.

A method of manufacturing such a thin film transistor substrate is as follows.

As shown in FIG. 1A, after forming the blocking layer 111 and the amorphous silicon layer on the transparent insulating substrate 110, the amorphous silicon layer is crystallized by heat treatment. Subsequently, the polycrystalline silicon layer 150 is formed by patterning the photolithography process.

As shown in FIG. 1B, after the gate insulating layer 140, the aluminum layer 201, the chromium layer 202, and the photosensitive layer are stacked on the polysilicon layer 150, the photosensitive layer is patterned to form a photosensitive layer pattern PR. ).

As shown in FIG. 1C, the chromium layer 202 and the aluminum layer 201 are etched using the photosensitive layer pattern PR as a mask to form the sacrificial layer 203, the gate electrode 123, and the gate line (not shown). To form a gate wiring comprising a. At this time, since the aluminum layer 201 is more easily etched than the chromium layer 202, the aluminum layer 201 forms an undercut structure as shown.

As shown in FIG. 1D, after removing the photoresist layer pattern PR, a high concentration of impurity ions are implanted using the sacrificial layer 203 as a mask, thereby source source 153, drain region 155, and channel region not doped with impurities. 154 is formed.

As shown in FIG. 1E, after the sacrificial layer 203 is removed, low concentration doped regions 152 are formed by implanting low concentration impurity ions using the gate wiring as a mask.

The first interlayer insulating layer 801 is formed on the gate wirings. The first interlayer insulating layer 801 includes a first contact hole 161 exposing the source region 153 and a second contact hole 162 exposing the drain region 155.

As shown in FIG. 1F, the conductive layer is formed on the first interlayer insulating layer 801 and then patterned to form the data line 171 and the drain electrode 175. The data line 171 is connected to the source region 153 and the drain electrode 175 is formed to be connected to the drain region 155.                         

Thereafter, a second interlayer insulating layer 802 including a third contact hole 163 exposing the drain electrode 175 is formed on the drain electrode. The pixel electrode 190 is formed on the second interlayer insulating layer 802 to be connected to the drain electrode 175 through the third contact hole.

In this way, a sacrificial layer is required to form the lightly doped region. In addition, aluminum in the aluminum layer may diffuse into the lower silicon layer to deteriorate characteristics of the thin film transistor.

It is therefore an object of the present invention to simplify the process and to provide a thin film transistor substrate and a method of manufacturing the same, in which aluminum is not diffused.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention includes the steps of laminating an amorphous silicon layer on an insulating substrate, crystallizing the amorphous silicon layer, and then patterning to form a polycrystalline silicon layer, polycrystalline silicon Stacking a gate insulating layer, a conductive layer and a photosensitive layer on the layer, patterning the photosensitive layer to form a photosensitive layer pattern, etching the conductive layer using the photosensitive layer pattern as a mask, and having a gate having a predetermined width smaller than the photosensitive layer pattern Forming a wiring, forming a source region doped with an n-type or p-type impurity, a drain region, a channel region not doped with an impurity in the polycrystalline silicon layer using the photosensitive layer pattern as a mask, and then removing the photosensitive layer pattern Doping impurities using the gate wiring as a mask to form a low concentration impurity region; first interlayer insulation on the gate wiring Forming a layer, forming a first contact opening exposing the source region and a second contact opening exposing the drain region in the first interlayer insulating layer, and forming a source contact through the first contact opening on the first interlayer insulating layer. Forming a data line including a data line to be connected and a drain electrode connected to the drain region through a second contact hole, forming a second interlayer insulating layer on the data line, and exposing the drain electrode on the second interlayer insulating layer Forming a third contact hole, and forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating layer.

Another method includes laminating an amorphous silicon layer on an insulating substrate, crystallizing the amorphous silicon layer, and then patterning to form a polycrystalline silicon layer, laminating a gate insulating layer, a conductive layer, a photosensitive layer on the polycrystalline silicon layer, Patterning the photosensitive layer to form a photosensitive layer pattern; etching the conductive layer using the photosensitive layer pattern as a mask to form gate wiring and data metal pieces having a predetermined width smaller than the photosensitive layer pattern; and using the photosensitive layer pattern as a mask Forming a source region, a drain region, and a channel region not doped with an n-type or p-type impurity in the polysilicon layer, removing the photosensitive layer pattern, and then doping the impurities with a gate wiring and a data metal piece as a mask. Forming a low concentration impurity region, forming an interlayer insulating layer over the gate wiring and the data metal piece, the layer Forming a first contact opening exposing a source region, a second contact opening exposing a drain region, and a third contact opening exposing a data metal piece in the interlayer insulating layer, the source region through the first contact opening on the interlayer insulating layer And a data connection part connected to the data metal piece through the third contact hole and a pixel electrode connected to the drain region through the second contact hole.

In this case, the data metal piece is formed between two adjacent gate lines, and the data connection part is formed to intersect the gate line.

The conductive layer formed in these methods consists of a double layer of a molybdenum tungsten layer and an aluminum layer, and the molybdenum tungsten layer serves as a barrier layer for blocking the diffusion of aluminum. Moreover, it is preferable to use high heat resistance for a photosensitive layer.

A thin film transistor substrate according to the present invention for achieving another object of the present invention is a gate formed on a polycrystalline silicon layer, a polycrystalline silicon layer including a source region, a drain region, a channel region, a lightly doped region formed on an insulating substrate A gate line including an insulating layer, a gate line formed to extend in one direction on the gate insulating layer, a gate electrode formed to correspond to a channel region as a part of the gate line, and a gate line including a gate pad formed at one end of the gate line, and on the gate line A first interlayer insulating layer formed on the first contact hole to expose the source region, the first interlayer insulating layer to expose the drain region, a data line crossing the gate line and connected to the source region through the first contact hole; 2 drain electrode connected to the drain region through the contact hole, at one end of the data line A second data interlayer insulating layer formed on the data line, the second interlayer insulating layer including a third contact hole exposing a drain electrode, and a second interlayer insulating layer formed on the data line and through the third contact hole. And a pixel electrode connected to the drain electrode, and the gate wiring includes a barrier layer formed of molybdenum tungsten and an aluminum layer formed of aluminum on the barrier layer.                     

Or a polycrystalline silicon layer including a source region, a drain region, a channel region, and a lightly doped region, a gate insulating layer formed on the polycrystalline silicon layer, and a gate line extending in one direction on the gate insulating layer, A gate electrode formed to correspond to the channel region as a part of the gate line, a gate wiring including a gate pad formed at one end of the gate line, a data metal piece formed on the gate insulating layer between the gate lines, the gate wiring and the data metal piece And an interlayer insulating layer including a first contact hole exposing the source region, a second contact hole exposing the drain region, a third contact hole exposing the data metal piece, and formed on the interlayer insulating layer to intersect the gate wiring. Data through the first and third contacts A data connection part connected to the piece, the pixel electrode being formed on the interlayer insulating layer and connected to the drain region through the second contact hole, and the gate wiring and the data metal piece being formed of a barrier layer made of molybdenum tungsten, It consists of an aluminum layer formed of aluminum.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity.

Now, a thin film transistor substrate and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings.                     

2 is a cross-sectional view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 3A to 3G are diagrams sequentially illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a thin film transistor substrate according to an exemplary embodiment of the present invention includes a transparent insulating substrate 110, a blocking layer 111 formed on the insulating substrate 110, and a predetermined portion on the blocking layer 111. A gate formed in the region and formed on the polycrystalline silicon layer 150 and the polycrystalline silicon layer 150 including the source region 153, the channel region 154, the drain region 155, and the lightly doped region 152. An insulating layer 140, a barrier layer 204 formed on the gate insulating layer 140 corresponding to the channel region 154, a gate electrode 175, and a gate electrode 175 formed on the barrier layer 204. A first interlayer insulating layer 801 and a first interlayer including a first contact hole 161 formed thereon and exposing a second contact hole 162 exposing a drain region 155. A second contact with the data line 171 formed on the insulating layer 801 and connected to the source region 153 through the first contact hole 161. The third contact hole 163 formed on the drain electrode 175, the data line 171, and the drain electrode 175 connected to the drain region 155 through the urging 162 and exposing the drain electrode 175. And a pixel electrode 190 formed on the second interlayer insulating layer 802 including the second interlayer insulating layer 802 and connected to the drain electrode 175 through the third contact hole 163. .

In the method of manufacturing the thin film transistor substrate, first, as shown in FIG. 3A, the blocking layer 111 and the amorphous silicon layer are sequentially stacked on the transparent insulating substrate 110. The amorphous silicon layer is heat-treated to crystallize and then patterned by photolithography to form the polycrystalline silicon layer 150.

In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 may be formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) and forming an amorphous silicon layer ( 150A) is formed by depositing amorphous silicon by Chemical Vapor Deposition (CVD). And heat treatment uses a laser annealing (furnace annealing) or furnace annealing (furnace annealing).

As shown in FIG. 3B, the gate insulating layer 140, the molybdenum tungsten layer 201, the aluminum layer 202, and the photosensitive layer are stacked on the polycrystalline silicon layer 150.

The photosensitive layer pattern PR is formed by patterning the photosensitive layer by a predetermined width wider than the gate wiring to be formed. Here, the photosensitive layer has a high heat resistance and serves as a mask for impurity doping that proceeds later.

The molybdenum tungsten layer 201 is a barrier layer for preventing the aluminum of the aluminum layer 202 from diffusing into the lower silicon layer and is formed to a minimum thickness. Preferably it is formed in 300 ~ 500nm.

As shown in FIG. 3C, the gate layer is formed by etching the aluminum layer 202 using the photosensitive layer pattern PR as a mask. Subsequently, the molybdenum tungsten layer 201 is etched to form the barrier layer 204.

The gate wiring includes a gate line (not shown) formed long in one direction, a gate electrode 123 which is a part of the gate line, and a gate pad (not shown) formed at one end of the gate line.

The gate line and the barrier layer may be formed to be narrower by a predetermined width than the photosensitive layer pattern PR by controlling an etching time or an etchant. In addition, it is possible to simultaneously etch using an etchant without an etching selectivity between the aluminum layer and the molybdenum tungsten layer.

Thereafter, a high concentration of impurities are injected into the polysilicon layer 150 using the photosensitive layer pattern PR as a mask to form the source region 153, the drain region 155, and the channel region 154. The channel region 154 is a region where impurities are not implanted and is disposed under the gate electrode 123 and separates the source region 153 and the drain region 155.

As shown in FIG. 3D, after the photosensitive layer PR is removed, impurities are implanted at low concentration using the gate wiring as a mask to form a low concentration impurity region 152.

The low concentration impurity region 152 is formed by a predetermined width, where the predetermined width refers to a difference between the width of the photosensitive layer pattern PR and the width of the gate wiring.

As shown in FIG. 3E, an insulating material is stacked on the entire surface of the substrate to form a first interlayer insulating layer 801.

Thereafter, the first contact hole 161 and the second contact hole 162 exposing the source region 153 and the drain region 155 are formed in the first interlayer insulating layer 801 by a photolithography method.

As shown in FIG. 3F, a conductive layer is formed on the first interlayer insulating layer 801 and then patterned to form a data line including a data line 171 and a drain electrode 175.

The data line 171 is formed to cross the gate line to define the pixel area, and is connected to the source area 153 through the first contact hole 161. The drain electrode 175 is connected to the drain region 155 through the second contact hole 162.

As shown in FIG. 3G, an insulating material is laminated on the first interlayer insulating layer 801 to form a second interlayer insulating layer 802.

Thereafter, a third contact hole 163 exposing the drain electrode 175 is formed in the second interlayer insulating layer 802 by a photolithography method. The ITO is deposited on the second interlayer insulating layer 802 and then patterned to form the pixel electrode 190. The pixel electrode 190 is connected to the drain electrode 175 through the third contact hole 163.

Second Embodiment

4A and 4B are a layout view and a cross-sectional view of a thin film transistor substrate according to a second embodiment of the present invention, respectively. As illustrated, a polysilicon layer 150 including a source region 153, a drain region 155, a channel region 154, and a lightly doped region 152 is formed on the transparent insulating substrate 110. The gate insulating layer 140 is formed on the polycrystalline silicon layer 150.

A gate line 121 extending in the horizontal direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends in the vertical direction to partially overlap the polycrystalline silicon layer 150, and the polycrystalline silicon layer 150 ) And a portion of the gate line 121 overlapped with each other becomes a gate electrode 123.

A gate pad 125 for receiving a scan signal from an external circuit (not shown) is formed at one end of the gate line 121. Hereinafter, the gate electrode 123, the gate line 121, and the gate pad 125 are referred to as gate wirings.

In addition, the storage electrode line may be formed on the same layer with the same material as the gate line 121 so as to be spaced apart from the gate line 121 in parallel with the gate line 121 to increase the storage capacitance. At this time, a portion of the storage electrode line overlapping the polycrystalline silicon layer 150 becomes a storage electrode, and the polycrystalline silicon layer 150 positioned below the storage electrode becomes a storage region.

The data metal piece 171a is formed on the same layer as the gate line 121 to extend in a direction perpendicular to the gate line 121 while being spaced apart from the gate line 121 by a predetermined distance. The data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. The data metal piece 171a includes a data pad (not shown) for receiving an image signal from an external circuit (not shown).

A barrier layer 204 is interposed between the gate wirings 121, 123, and 125 and the data metal piece 171a and the gate insulating layer 140. The barrier layer 204 is formed of molybdenum tungsten as a layer for preventing the aluminum forming the gate line from being diffused into the polycrystalline silicon layer 150. In the case where the sustain wiring is formed, the sustain wiring is also formed on the barrier layer in the same manner as the gate wiring. An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate wirings 121, 123, and 125 and the data metal piece 171a.

The data connector 171b, the pixel electrode 190, the auxiliary gate pad 95, and the auxiliary data pad (not shown) are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through a third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the first contact hole 161. It is connected to the source region 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the auxiliary gate pad 95. The auxiliary data pad is connected to the gate pad 125 and the data pad through the fourth contact hole 164 and the fifth contact hole (not shown) formed in the interlayer insulating layer 160, respectively.

A method of forming a thin film transistor having such a structure is as follows.

First, as shown in FIG. 5A, the blocking layer 111 and the amorphous silicon layer are laminated on the insulating substrate 110 and heat treated to crystallize. Thereafter, an amorphous silicon layer is patterned to form a polycrystalline silicon layer 150, and a gate insulating layer 140, a molybdenum tungsten layer 201, an aluminum layer 202, and a photosensitive layer are stacked on the polycrystalline silicon layer 150. . The photosensitive layer is patterned to form the photosensitive layer pattern PR.

The molybdenum tungsten layer 201 is a barrier layer for preventing the aluminum of the aluminum layer 202 from diffusing into the lower silicon layer and is formed to a minimum thickness. Preferably it is formed in 300 ~ 500nm.

The photosensitive layer is patterned wider by a predetermined width than the wiring to be formed to form the photosensitive layer pattern PR. Here, the photosensitive layer has a high heat resistance and serves as a mask when doping impurities later.

As shown in FIG. 5B, the aluminum layer 202 is etched using the photosensitive layer pattern PR as a mask to form a gate wiring and a data metal piece 701a having a predetermined width smaller than that of the photosensitive layer pattern PR. At this time, the molybdenum tungsten layer 201 is also etched together to form a barrier layer 204 having the same pattern as the gate wiring and the data metal piece 701a.

As shown in FIG. 5C, the polycrystalline silicon layer is heavily doped with n-type or p-type impurities using a photosensitive layer pattern (PR) turn as a mask so that the source region 153, the drain region 155, and the impurities are not doped. Channel region 154 is formed.

Thereafter, the photoresist layer pattern PR is removed, and then the doped impurities are lightly doped into the polysilicon layer 150 using the gate wiring and the data metal piece 701a as a mask to form the low concentration ion region 152. The low concentration ion region 152 is formed in the channel region 154 positioned between the source region 153 and the gate electrode 123, and the drain region 155 and the gate electrode 123.

As shown in FIG. 5D, an interlayer insulating layer 160 is formed over the gate wiring and the data metal piece 701a. The first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the third contact hole exposing the data metal piece 701a may be formed by a photolithography process. 163).

As shown in FIG. 5E, the first contact hole 161 is connected to the source region 153 through the interlayer insulating layer 160, and the data metal piece 701a is connected through the third contact hole 163. The pixel electrode 190 connected to the drain region 155 is formed through the data connector 701b and the second contact hole 162.

Although the preferred embodiments of the present invention have been described in detail as described above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the present invention.

As described above, by forming the molybdenum tungsten layer according to the present invention, it is possible to prevent the aluminum of the aluminum layer from diffusing into the polycrystalline silicon layer.

In addition, by using the high heat-resistant photosensitive layer, the process of forming the chromium layer for forming the low concentration doped region can be omitted, thereby simplifying the process.

Claims (9)

Laminating an amorphous silicon layer on the insulating substrate, Crystallizing the amorphous silicon layer, followed by patterning to form a polycrystalline silicon layer, Stacking a conductive layer and a photosensitive layer comprising a double layer of a gate insulating layer, a molybdenum tungsten layer, and an aluminum layer on the polycrystalline silicon layer; Patterning the photosensitive layer to form a photosensitive layer pattern; Etching the conductive layer using the photosensitive layer pattern as a mask to form a gate wiring having a width narrower than that of the photosensitive layer pattern; Forming a source region, a drain region, and a channel region not doped with impurities in the polycrystalline silicon layer using the photosensitive layer pattern as a mask; Removing the photosensitive layer pattern and then doping impurities using the gate wiring as a mask to form a low concentration impurity region; Forming a first interlayer insulating layer on the gate wiring; Forming a first contact hole exposing a source region and a second contact hole exposing a drain region in the first interlayer insulating layer, Forming a data line on the first interlayer insulating layer, the data line including a data line connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole; Forming a second interlayer insulating layer on the data line; Forming a third contact hole exposing the drain electrode on the second interlayer insulating layer, Forming a pixel electrode on the second interlayer insulating layer and connected to the drain electrode through the third contact hole; Method of manufacturing a thin film transistor substrate comprising a. Laminating an amorphous silicon layer on the insulating substrate, Crystallizing the amorphous silicon layer, followed by patterning to form a polycrystalline silicon layer, Stacking a conductive layer and a photosensitive layer comprising a double layer of a gate insulating layer, a molybdenum tungsten layer, and an aluminum layer on the polycrystalline silicon layer; Patterning the photosensitive layer to form a photosensitive layer pattern; Etching the conductive layer using the photosensitive layer pattern as a mask to form a gate wiring and a data metal piece having a narrower width than the photosensitive layer pattern; Forming a source region, a drain region, and a channel region not doped with impurities in the polycrystalline silicon layer using the photosensitive layer pattern as a mask; Removing the photosensitive layer pattern and then doping impurities using the gate wiring and the data metal piece as a mask to form a low concentration impurity region; Forming an interlayer insulating layer over said gate wiring and data metal piece, Forming a first contact hole exposing the source region, a second contact hole exposing the drain region, and a third contact hole exposing the data metal piece in the interlayer insulating layer; A data connection part connected to the source region through the first contact hole and connected to the data metal piece through the third contact hole and a pixel electrode connected to the drain region through the second contact hole on the interlayer insulating layer; Forming steps Method of manufacturing a thin film transistor substrate comprising a. The method of claim 2, The data metal piece is formed between two adjacent gate lines, and the data connection part is formed to cross the gate line. delete delete The method of claim 1 or 2, The photosensitive layer is a method of manufacturing a thin film transistor substrate having high heat resistance. The method of claim 1 or 2, And the gate wiring is narrower by the width of the lightly doped region than the photoresist pattern. delete delete

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