KR100848097B1 - A method for fabricating a thin film transistor array panel - Google Patents

Abstract

First, an amorphous silicon layer is laminated and crystallized on an insulating substrate, and then patterned to form a polycrystalline silicon layer, and a gate wiring and a sustain electrode wiring are formed on the gate insulating layer covering the polycrystalline silicon layer. Subsequently, a source region doped with n-type or p-type impurities, a drain region, and a channel region not doped with impurities are formed in the polysilicon layer, and then a first interlayer insulating layer is formed over the gate wiring and the sustain electrode wiring. Subsequently, a photolithography process using a photoresist pattern having a different thickness is used to pattern the first interlayer insulating layer to form a first contact hole exposing the source region and a second contact hole exposing the drain region, thereby forming an upper portion of the upper portion of the storage electrode wiring. A portion is etched to form a trench. Next, a data line including a data line and a drain electrode connected to the source region and the drain region, respectively, is formed on the first interlayer insulating layer through the first and second contact holes. Subsequently, a third contact hole exposing the drain electrode is formed in the second interlayer insulating layer covering the data wiring, and the transparent conductive film and the reflective conductive film are sequentially stacked and patterned on the second interlayer insulating layer to drain through the third contact hole. A pixel electrode formed of a transparent conductive film and a reflective conductive film having openings in the pixel region is formed.

Thin film transistor substrate, transparent conductive film, reflective conductive film, photosensitive film, photolithography process

Description

A method for fabricating a thin film transistor array panel

1 is a layout view of a thin film transistor array substrate according to an embodiment of the present invention,

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1;

3A, 4A, 5A, 6A, and 7A are layout views illustrating a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention according to a process sequence thereof.

3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 3A;

FIG. 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A and shows the next step of FIG. 3B;

FIG. 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A and shows the next step of FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5A and illustrates the next step of FIG. 4B;

FIG. 5C is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and shows the next step in FIG. 5B.

FIG. 5D is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and shows the next step in FIG. 5C.

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and shows the next step in FIG. 5D;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrates the next step of FIG. 6B;

FIG. 8A is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A and illustrates the next step of FIG. 7B;

FIG. 8B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A and illustrates the next step of FIG. 8A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

123: gate electrode 131: sustain electrode line

133: sustain electrode 140: gate insulating layer

150 polycrystalline silicon layer 151 channel region

152: source region 154: drain region

171: data line 173: drain electrode

190: pixel electrode

The present invention relates to a thin film transistor array substrate and a method of manufacturing the same.

The thin-film transistor substrate (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and a data line, and a pixel connected to the thin film transistor. And an electrode, a gate insulating layer covering and insulating the gate wiring, and a second interlayer insulating layer covering and insulating the thin film transistor and the data wiring.

The thin film transistor includes a semiconductor layer forming a gate electrode and a channel, which are part of a gate wiring, a source electrode and a drain electrode, which are part of a data wiring, a gate insulating layer, a second interlayer insulating layer, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

Such a thin film transistor has an amorphous silicon layer or a polycrystalline silicon layer as an active layer, and may be divided into a top gate method and a bottom gate method according to a relative position of the gate electrode and the active layer. In the case of a polysilicon thin film transistor array substrate, a top gate method in which a gate electrode is located above the semiconductor layer is mainly used.

In the top gate method, a polycrystalline silicon layer is formed on an insulating substrate, a gate insulating layer is formed on the polycrystalline silicon layer, and a gate wiring and a sustain electrode line are formed on the gate insulating layer. Further, a first interlayer insulating layer is formed on the gate wiring and the sustain electrode line, and a data wiring is formed on the first interlayer insulating layer. The pixel electrode is formed on the same layer as the data line or on the second interlayer insulating layer formed on the data line.

At this time, parasitic capacitance is formed between the data wiring separated by the first interlayer insulating layer and the data wiring separated by the gate wiring or the second interlayer insulating layer and the pixel electrode. Since such parasitic capacitance degrades the display quality of a display device using a thin film transistor substrate, it is desirable to suppress the parasitic capacitance to be as small as possible. To this end, a technology for forming the second interlayer insulating layer with an organic insulating material having a low dielectric constant has been developed. However, in such a structure, since the first and second interlayer insulating layers are formed between the sustain electrode line and the pixel electrode, it is difficult to sufficiently secure the storage capacitance.

On the other hand, an array substrate on which a polysilicon thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, in order to reduce the production cost, it is preferable to reduce the number of masks. Currently, eight or nine masks are used.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate capable of minimizing parasitic capacitance and ensuring sufficient storage capacity.

Another object of the present invention is to provide a method of manufacturing a thin film transistor array substrate that can minimize the manufacturing cost.

In order to achieve the above object, in the present invention, when a photoresist pattern having a different thickness is patterned with an etching mask, the thickness of the insulating film is thinner than other portions on the top of the storage electrode line when forming a contact hole for exposing the wiring. The reflective conductive film and the transparent conductive film forming the electrode are formed together.

In more detail, in the method for manufacturing a thin film transistor array substrate according to the present invention, an amorphous silicon layer is laminated and crystallized on a transparent insulating substrate, and then patterned to form a polycrystalline silicon layer. Next, a gate insulating layer covering the polysilicon layer is formed, and a gate wiring and a sustain electrode wiring are formed on the gate insulating layer. Subsequently, a source region doped with n-type or p-type impurities, a drain region, and a channel region not doped with impurities are formed in the polysilicon layer, and then a first interlayer insulating layer is formed over the gate wiring and the sustain electrode wiring. Subsequently, the first interlayer insulating layer is patterned by a photolithography process having one photoresist pattern to etch a portion of the upper portion of the sustain electrode wiring while forming a first contact hole exposing a source region and a second contact hole exposing a drain region. Form a trench. Subsequently, a data line including a data line connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole is formed on the first interlayer insulating layer, and then on the data interconnection layer. An insulating layer is formed. Subsequently, a third contact hole exposing the drain electrode is formed on the second interlayer insulating layer, and a pixel electrode connected to the drain electrode is formed on the second interlayer insulating layer through the third contact hole.

In this case, the photoresist pattern corresponds to the trench and corresponds to the first portion having the first thickness and the remaining portion except for the first and second contact holes, and the second portion having the second thickness thicker than the first portion, and the first and the first portion. It is preferable to have a thickness corresponding to the two contact holes and thinner than the first portion.

The pixel electrode may be formed of a transparent conductive film made of a transparent conductive material and a reflective conductive film made of a conductive material having openings and reflectivity. The transparent conductive film and the reflective conductive film may be formed by a photolithography process using a single photoresist pattern. It is preferable to pattern.

At this time, the photoresist pattern corresponds to the opening and has a first portion having a first thickness and a second conductive portion corresponding to the reflective conductive film and having a second thickness thicker than the first portion, and having a thickness smaller than that of the first portion. It includes a third part except two parts.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a polysilicon thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 and 2, in the thin film transistor array substrate according to the embodiment of the present invention, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and the blocking layer The polysilicon layer 150 including the source region 152, the drain region 154, and the channel region 151 positioned between the source region 152 and the drain region 154 is formed on the 111.

A gate insulating layer 140 made of silicon nitride or silicon oxide is formed on the substrate 110 to cover the polycrystalline silicon layer 150.

A gate line 121 extending in the horizontal direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends in the vertical direction to partially overlap the polycrystalline silicon layer 150, and the polycrystalline silicon layer ( The gate line 121 partially overlapping the 150 becomes the gate electrode 123 of the thin film transistor.

In addition, the storage electrode line 131 is parallel to the gate line 121 on the gate insulating layer 140, and is formed on the same layer using the same material. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and a corresponding portion of the polycrystalline silicon layer 150 becomes the storage electrode region 156.

Hereinafter, the gate line 121 and the gate electrode 123 are referred to as gate wirings, and the sustain electrode 133 and the sustain electrode line 131 are referred to as sustain electrode wirings.

A first interlayer insulating layer 801 is formed on the gate insulating layer 140 on which the gate wirings 121 and 123 and the sustain electrode wirings 131 and 133 are formed and covers them, and is made of an insulating material having a low dielectric constant. The first interlayer insulating layer 801 includes a first contact hole 141 and a second contact hole 142 that expose the source region 152 and the drain region 154, together with the gate insulating layer 140. . In this case, the first interlayer insulating layer 801 positioned on the storage electrode 133 has a thickness thinner than that of other portions.

The data line 171 is formed long in the vertical direction on the first interlayer insulating layer 801 to cross the gate line 121, and is connected to the source region 152 through the first contact hole 141. In addition, the drain electrode 175 is connected to the upper layer through the second contact hole 142 and extends to the upper portion of the sustain electrode 133. In this case, the drain electrode 175 is electrically connected to the pixel electrodes 191 and 192 formed thereafter, and the first interlayer insulating layer 801 between the drain electrode 175 and the storage electrode 133 is formed to have a higher thickness than that of other portions. Since it is formed with a thin thickness, it is possible to secure a sufficient storage capacity even with a small area of overlap.

A second interlayer insulating layer 802 made of silicon nitride or an organic material is formed on the first interlayer insulating layer 801 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 802 has a third contact hole 143 exposing the drain electrode 173, and a second interlayer insulating layer for inducing a surface of the reflective conductive film 192 formed later into an uneven pattern. The surface of layer 802 has an uneven pattern.

A transparent conductive film 191 made of a transparent conductive material such as IZO or ITO is formed on the second interlayer insulating layer 802, and a portion of the transparent conductive film 191 is drain electrode through the third contact hole 143. 175 is connected. An upper portion of the transparent conductive film 191 has an opening T so that the transparent conductive film 191 is exposed in a part of the pixel region PX, and is made of a conductive material having reflectivity such as aluminum or an aluminum alloy or silver or silver alloy. The reflective conductive film 192 is formed.

Next, a method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention described above will be described in detail.

3A, 4A, 5A, 6A, and 7A are layout views illustrating a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention, according to a process sequence thereof, and FIG. 3B is cut along the line IIIb-IIIb 'of FIG. 3A. 4B is a cross-sectional view taken along the line IVb-IVb 'in FIG. 4A, showing the next step in FIG. 3B, and FIG. 4B is shown along the IVb-IVb' line in FIG. 4A. As a cross-sectional view, the next step of FIG. 3B is shown, and FIG. 5B is a cross-sectional view taken along the line Vb-Vb 'in FIG. 5A, and the next step of FIG. 4B is shown, and FIG. 5C is a view of FIG. 5A. 5B is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5B, and FIG. 5D is a cross-sectional view taken along the line Vb-Vb' of FIG. 5A, and is shown in FIG. 5C. FIG. 6B is a cross-sectional view taken along the line VIb-VIb 'of FIG. 6A and shown in FIG. 5D. FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'in FIG. 7A, showing the next step in FIG. 6B, and FIG. 8A showing the line VIIb-VIIb' in FIG. 7A. 7B is a cross-sectional view illustrating the next step of FIG. 7B, and FIG. 8B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A, and illustrates the next step of FIG. 8A.

First, as illustrated in FIGS. 3A and 3B, a barrier layer 111 is formed by stacking a chemical vapor deposition on a transparent insulating substrate 110 and then performing a first surface treatment with ozone water. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa.

In the first surface treatment, first, the ozone water is washed for 1 to 10 minutes while maintaining 0 to 70 ° C at a concentration of 10 to 100 ppm, and then the barrier layer is removed with deionized water to remove the ozone water remaining in the barrier layer. Rinsing.

Subsequently, after forming an amorphous silicon layer on the barrier layer 111 from which impurities are removed through ozone surface treatment, the amorphous silicon layer is subjected to a second surface treatment using ozone water. The amorphous silicon layer 150 is formed by depositing amorphous silicon in a chemical vapor deposition (CVD) method with a thickness of about 500 GPa.

The process of performing the secondary surface treatment is the same as the primary surface treatment.                     

Subsequently, the amorphous silicon layer 150 is crystallized by laser annealing or furnace annealing, and then patterned by photolithography using a mask to form the polycrystalline silicon layer 150.

As shown in FIGS. 4A and 4B, after the silicon oxide or silicon nitride is deposited by chemical vapor deposition on the polycrystalline silicon layer 150 to form the gate insulating layer 140, a conductive material having low resistance is laminated. The gate electrode 123 and the gate line 121 are formed by a photolithography process using a mask, and the storage electrode 133 and the storage electrode line 131 are simultaneously formed.

The gate insulating layer 140 is formed by depositing an insulating material such as silicon nitride or silicon oxide to a thickness of 500 to 3000 kPa by a chemical vapor deposition method.

The gate electrode 123 and the gate line 121 may be formed on the gate insulating layer 140 by a single layer or an aluminum alloy layer of aluminum-containing metal such as aluminum or aluminum neodymium (AlNd), and a chromium (Cr) or molybdenum (Mo) alloy. A multilayer conductive material layer comprising a layer or the like is deposited and patterned by photolithography.

Hereinafter, the gate line 121 and the gate electrode 123 are referred to as gate wirings, and the sustain electrode 131 and the sustain electrode line 133 are referred to as sustain electrode wirings.

Thereafter, a p-type or n-type conductive impurity is implanted into the polysilicon layer 150 using the gate wiring as a mask to form the source region 152, the drain region 154, and the channel region 151. The channel region 151 is a region that is not doped with impurities and is positioned under the gate electrode 123 and separates the source region 152 and the drain region 154. In addition, due to the difference in length and width of the polysilicon layer 150 and the storage electrode line 131, a polysilicon layer 150a exposed outside the storage electrode line 131 is formed, and these regions are also doped and the storage electrode region 156. ) And separated from the drain region 154.

The formation of the gate wirings 121 and 123 and the sustain electrode wirings 131 and 133 and the implantation of p-type and n-type conductive impurities into the polysilicon layer 150 will be described in more detail as follows.

In the photolithography process using a photosensitive film, the gate conductive layer of the p-type thin film transistor region is etched to form a gate wiring (not shown) of the p-type thin film transistor, and then a p-type impurity is injected to inject the source region of the p-type thin film transistor, A drain region and a channel region are formed. At this time, the portion where the n-type thin film transistor is to be formed is covered and protected by the photosensitive film. Subsequently, in the photolithography process using another photoresist film, the gate conductive layer of the n-type thin film transistor region is etched to form the gate wirings 121 and 123 of the n-type thin film transistor, and the n-type gate wirings 121 and 123 are used as masks. The impurity is implanted to form the source region 152, the drain region 154, and the channel region 151 of the n-type thin film transistor. At this time, the portion where the p-type thin film transistor is formed is covered and protected by the photosensitive film. The channel region 151 is a region where impurities are not implanted and is positioned below the gate electrode 123 and separates the source region 152 and the drain region 154. The order of forming the n-type and p-type thin film transistor regions may be changed.

Next, an insulating material is laminated on the entire surface of the substrate 100 on which the source region 152, the drain region 154, and the channel region 151 are formed to form a first interlayer insulating layer 801, and then a photoresist film is formed thereon. Apply. Thereafter, the photosensitive film is irradiated with light through a mask and then developed to form photosensitive film patterns 212 and 214 as shown in FIGS. 5A and 5B.

In this case, the first portion 214 of the photoresist patterns 212 and 214 disposed above the storage electrode 133 may have a smaller thickness than the second portion 212 positioned in the other portion A. All photoresist films at positions corresponding to the contact holes 141 and 142 are removed. At this time, the ratio of the thickness of the first portion 214 and the thickness of the second portion 212 should be different depending on the process conditions in the etching process to be described later, the thickness of the first portion 214 to the second portion It is preferable to set it as 1/2 or less of the thickness of (212), for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 214 and the lower layers thereof, that is, the first interlayer insulating layer 801 and the gate insulating layer 140.

First, as shown in FIG. 5B, the first interlayer insulating layer 801 and the gate insulating layer 140 are etched using the photoresist patterns of the first portion 214 and the second portion 212 as an etching mask. The first contact hole 141 and the second contact hole 142 exposing the region 152 and the drain region 154 are formed.

As shown in FIG. 5C, a portion of the photoresist film is removed by an ashing process to remove the photoresist film of the first portion 214, leaving only the photoresist film of the second portion 212, and then as shown in FIG. 5D, the second portion 212. A portion of the first interlayer insulating layer 801 is removed by using a photoresist film of) as an etching mask to form a trench 811 in the first interlayer insulating layer 801 on the storage electrode 133.                     

6A and 6B, aluminum or an aluminum alloy or molybdenum having a low resistance on the first interlayer insulating layer 801 including the first contact hole 141 and the second contact hole 142. Alternatively, a single film or a multilayer film of molybdenum alloy or the like is formed, and then patterned by a photolithography process using a mask to form the data line 171 and the drain electrode 175. The data line 171 is connected to the source region 152 through the first contact hole 141, the drain electrode 175 is connected to the drain region 175 through the second contact hole 142, and the sustain electrode It extends to the top of 133 to form.

Next, as shown in FIGS. 7A and 7B, an insulating material is stacked on the first interlayer insulating layer 801 on which the data line 171 and the drain electrode 175 are formed to form a second interlayer insulating layer 802. do. Thereafter, a third contact hole 143 exposing the drain electrode is formed on the second interlayer insulating layer 802 by a photolithography method, and an uneven pattern is formed on the surface of the second interlayer insulating layer 802.

Subsequently, as illustrated in FIG. 8A, the transparent conductive material such as ITO or IZO, and the like may be reflected on the second interlayer insulating layer 802 including the inside of the third contact hole 143 and the reflectance such as aluminum or aluminum alloy or silver or silver alloy. After the conductive material is laminated in order to form the transparent conductive film 191 and the reflective conductive film 192 in order, the photosensitive film is coated on the reflective conductive film 192, and then a photo process using a mask is performed. The photoresist patterns 212 and 214 having partially different thicknesses are formed.

Subsequently, as shown in FIG. 8B, the reflective conductive layer 192 and the transparent conductive layer 191 are sequentially patterned using the photosensitive layer patterns 212 and 214 as a mask, and then the first portion having a thin thickness through an ashing process ( The photosensitive film of 214 is removed, and the remaining second portion 212 is patterned with an etching mask to remove a portion of the reflective conductive film 192 in the pixel region PX, as shown in FIGS. An opening T is formed in the film 192 to complete the pixel electrode.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the contact hole is formed, the first interlayer insulating film on the sustain electrode is thinly patterned to minimize the parasitic capacitance and to sufficiently secure the storage capacitance, which is patterned by a photolithography process using one photoresist pattern. By doing so, the manufacturing process can be simplified. In addition, the reflective conductive film and the transparent conductive film forming the pixel electrode having different shapes may be formed by a photolithography process using one photosensitive film pattern, thereby simplifying the manufacturing process and minimizing the manufacturing cost.

Claims (10)

delete delete delete delete delete Forming an amorphous silicon layer on the transparent insulating substrate; Crystallizing the amorphous silicon layer, followed by patterning to form a polycrystalline silicon layer; Forming a gate insulating layer covering the polycrystalline silicon layer; Forming a gate wiring and a sustain electrode wiring on the gate insulating layer; Forming a source region, a drain region, and a channel region not doped with impurities in the polycrystalline silicon layer; Forming a first interlayer insulating layer on the gate wiring and the sustain electrode wiring; Patterning the first interlayer insulating layer to form a photolithography process having a photoresist pattern to form a first contact hole exposing a source region and a second contact hole exposing a drain region; Forming a data line on the first interlayer insulating layer, the data line including a data line connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole; Forming a third contact hole exposing the drain electrode on the data line and a second interlayer insulating layer having irregularities on the surface; Stacking a transparent conductive film made of a transparent conductive material and a reflective conductive film made of a conductive material having a reflectivity on the second interlayer insulating layer including the third contact hole; Forming a photosensitive film pattern on the reflective conductive film, the photosensitive film pattern having a first portion and a second portion having a thickness greater than that of the first portion, Etching the reflective conductive layer and the transparent conductive layer using the photosensitive layer pattern as a mask to form a transparent electrode; Removing the photoresist pattern of the first portion and then removing the reflective conductive layer by using the second portion as a mask to form a reflective electrode having an opening exposing the transparent electrode Method of manufacturing a thin film transistor array substrate comprising a. delete In claim 6, In the first and second contact hole forming step And forming a trench by removing a first interlayer insulating layer on the sustain electrode wiring in a photosensitive film pattern having a first portion and a second portion having a thickness thicker than the first portion. delete In claim 8, And the first portion corresponds to the trench and the second portion corresponds to the remaining portion except for the first and second contact holes.

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