KR20050117302A - Thin film transistor using poly silicon and manufacturing method thereof - Google Patents

Abstract

In the present invention, in forming the LDD region, a mask used for forming a gate electrode is used, and the LDD region is used as one mask by varying the size of PR by adjusting the conditions for forming PR using the mask. In addition, by forming the LDD region under the gate electrode as well, the cost is low, and the reliability of the thin film transistor array panel is improved, thereby enabling a product such as a system on glass (SOG) in the future.

Description

Thin film transistor using polycrystalline silicon and its manufacturing method {THIN FILM TRANSISTOR USING POLY SILICON and MANUFACTURING METHOD THEREOF}

The present invention relates to a thin film transistor using polycrystalline silicon and a method of manufacturing the same.

The thin film transistor array panel is a substrate in which a thin film transistor, which is a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic EL display, is formed in a predetermined arrangement.

In the thin film transistor array panel, a plurality of gate lines and a data line cross each other, and a thin film transistor is formed in each pixel region where the two lines cross each other. The gate line transfers a scan signal and the data line transfers an image signal.

In the scan signal and the image signal, a gate driving circuit and a data driving circuit are applied to each gate line and data line, respectively. These driving circuits may be configured by mounting separate integrated chip (IC) chips, or may be formed together in the process of forming a thin film transistor on a display panel. The latter case is mainly applied to a polysilicon thin film transistor array panel having excellent performance of a thin film transistor.

In general, a thin film transistor uses amorphous silicon or polycrystalline silicon as a semiconductor layer.

Since the amorphous silicon thin film transistor has a mobility of about 0.5 to 1 cm 2 / Vsec, it can be used as a switching element of the liquid crystal display device, but the mobility is small and a direct drive circuit is formed on the upper part of the liquid crystal panel. There is an inadequate disadvantage of forming it.

Therefore, in order to overcome this problem, a polycrystalline silicon thin film transistor liquid crystal display device using polycrystalline silicon having a current mobility of about 20 to 150 cm 2 / Vsec as a semiconductor layer has been developed, and a polysilicon thin film transistor has a relatively high current mobility. Since it has a chip to glass (chip in glass) that embeds the driving circuit in the liquid crystal panel can be implemented.

However, the semiconductor layer of polycrystalline silicon has a disadvantage of low leakage resistance and a large leakage current.A lightly doped domain (LDD) structure having a lightly doped region between the channel portion and the heavily doped source and drain regions is used to minimize this. Use

In forming such a low concentration doping region, in the conventional case, a polycrystalline silicon layer is formed on a substrate, a gate insulating film and a gate line are formed thereon, and then a low concentration doping is used so that the doping energy used in the low concentration doping is large, and after the low concentration doping. The photomask pattern is formed to cover the sidewall of the gate line using a separate mask, and then the doping procedure is performed again. As such, since LDD formation and gate line formation are performed using separate masks, cost increases.

The present invention is to reduce the manufacturing cost of a thin film transistor array panel using polycrystalline silicon.

In order to solve this problem, the present invention uses the following thin film transistor array panel and its manufacturing method.

Specifically, an insulating substrate, a blocking layer formed on the substrate, formed on the blocking layer, and formed between the source region, the channel region, the drain region, the source region and the channel region, and the drain region and the channel region, respectively. A polycrystalline silicon layer having a low concentration doped region, a gate insulating film covering the polycrystalline silicon layer, a gate electrode formed on the gate insulating film, a first interlayer insulating film covering the gate electrode, and the first interlayer insulating film. A data line including a first contact hole and a second contact hole exposing portions of the source region and the drain region formed by being doped with the polycrystalline silicon layer, and a source electrode connected to the source region through the first contact hole, respectively. A drain electrode connected to the drain region through the second contact hole; A second interlayer insulating layer covering a line and a drain electrode and having a third contact hole exposing a portion of the drain electrode, and a pixel electrode connected to the drain electrode through a third contact hole on the second interlayer insulating film, wherein the polycrystalline The lightly doped region of the silicon layer is for a thin film transistor array panel using polycrystalline silicon positioned under the gate electrode,

The thin film transistor array panel may include forming a blocking layer on an insulating substrate, forming a polycrystalline silicon layer on the blocking layer, applying a first photosensitive layer on the polycrystalline silicon layer, and forming a first photosensitive layer pattern using a first mask. And then doping the impurity at low concentration, removing the first photoresist pattern, and sequentially laminating a gate insulating film, a gate conductive film, and a second photoresist film, and exposing and developing the second photoresist film by using the first mask. Forming a second photoresist pattern having a width wider than a width of the first photoresist pattern, patterning the gate conductive layer using the second photoresist pattern as a mask, and including a gate electrode having a width greater than the width of the first photoresist pattern Forming a gate line, wherein the polycrystalline silicon layer is impurity using the gate line as a mask Doping at a high concentration to form a source region and a drain region, forming a first interlayer insulating film covering the gate line and having first and second contact holes, and forming a source through the first contact hole on the first interlayer insulating film. Forming a data line having a source electrode connected to the region and a drain electrode connected to the drain region through the second contact hole, and forming a second interlayer insulating layer covering the data line and the drain electrode and having a third contact hole And forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating layer.

On the other hand, when formed by another embodiment of the present invention is formed by the following method.

Forming a blocking layer on the insulating substrate, forming a polycrystalline silicon layer on the blocking layer, forming a thin gate insulating film on the polycrystalline silicon layer, and using a first mask on the thin gate insulating film to form a first photoresist pattern Forming a layer, doping the polycrystalline silicon layer with a low concentration of impurities using the first photoresist pattern as a mask, and removing the first photoresist pattern, and stacking a gate insulating layer having a remaining thickness on the thin gate insulating layer Forming a gate conductive film and a second photoresist film sequentially on the gate insulating film; Forming a photoresist pattern, using the second photoresist pattern as a mask; Forming a gate line including a gate electrode having a width wider than that of the first photoresist pattern, and doping the polysilicon layer with a high concentration of impurities using the gate line as a mask to form a source region and a drain region Forming a first interlayer insulating film covering the gate line and having first and second contact holes; and a data line having a source electrode connected to the source region through the first contact hole on the first interlayer insulating film; Forming a drain electrode connected to the drain region through the second contact hole, forming a second interlayer insulating film covering the data line and the drain electrode and having a third contact hole, and forming a third contact hole on the second interlayer insulating film And a pixel electrode connected to the drain electrode through the manufacturing method.

On the other hand, the present invention can also be applied to an organic EL structure, and the organic EL has the following structure and method.

A thin film transistor array panel to which the present invention is applied as a TFT used in an organic EL display is formed on an insulating substrate, a blocking layer formed on the substrate, and a blocking layer, and including a source region, a channel region, a drain region, and the source region and a channel. A polysilicon layer having a region and a lightly doped region formed between the drain region and the channel region, a gate insulating film formed over the polycrystalline silicon layer, a gate line formed over the gate insulating film, and a first layer formed over the gate line A first interlayer insulating film, a data line and a power line formed on the first interlayer insulating film, a second interlayer insulating film formed on the data line, and a pixel electrode formed on the second interlayer insulating film,

The lightly doped region of the polycrystalline silicon layer is a thin film transistor array panel using polycrystalline silicon positioned under the gate electrode, and forms an organic emission layer on a predetermined region on the pixel electrode, surrounds the organic emission layer, and is an area of the organic emission layer. An organic EL display device may further include a barrier rib defining a barrier rib, and a common electrode formed on the organic light emitting layer and the barrier rib.

The polysilicon layer has a storage electrode portion connected to the first and second transistor portions and the second transistor portion, and the gate line and the storage electrode portion overlap the first and second transistors, respectively. And a sustain electrode overlapping the sustain electrode portion, wherein the data line includes a first source electrode connected to a source region of the first and second data lines, the first data line, and the first transistor portion, and a drain region of the first transistor portion. And a second source electrode connected to the second gate electrode and a second drain electrode connected to the drain region of the second transistor unit, wherein the pixel electrode is connected to the second drain electrode.

The thin film transistor array panel for the organic light emitting diode display may include forming a blocking layer on an insulating substrate, forming a polysilicon layer on the blocking layer, applying a first photoresist layer on the polysilicon layer, and using a first mask. Forming a first photoresist layer pattern, doping the polycrystalline silicon layer at low concentration using the first photoresist pattern as a mask, removing the first photoresist layer pattern, and then removing a gate insulating film, a gate conductive layer, and a second photoresist layer. Forming a second photoresist pattern having a width wider than that of the first photoresist pattern by exposing and developing the second photoresist layer using the first mask. The gate conductive layer is patterned using a mask to have a gate electrode wider than the width of the first photoresist layer pattern. Forming a gate line including a gate line, forming a source region and a drain region by doping the polycrystalline silicon layer with a high concentration of impurities using the gate line as a mask, and forming a first interlayer insulating layer on the gate line; Forming a data line having a source electrode and a drain electrode respectively connected to the source and drain regions on the first interlayer insulating film, forming a second interlayer insulating film on the data line, and connecting the drain electrode on the second interlayer insulating film Manufactured by a procedure including forming a pixel electrode.

Meanwhile, according to another embodiment, a thin film transistor array panel for an organic light emitting display device may include forming a blocking layer on an insulating substrate, forming a polysilicon layer on the blocking layer, and forming a thin gate insulating layer on the polysilicon layer. Forming a first photoresist pattern on the thin gate insulating layer using a first mask; doping impurities in the polycrystalline silicon layer at low concentration using the first photoresist pattern as a mask; and the first photoresist pattern Removing a second thickness of the gate insulating layer and then forming a gate conductive layer and a second photoresist layer on the gate insulating layer in sequence, and forming the second photoresist layer using the first mask. By exposure and development, the width wider than the width of the first photosensitive film pattern Forming a second photoresist pattern having a second photoresist pattern, and patterning the gate conductive layer using the second photoresist pattern as a mask to form a gate line having a width greater than that of the first photoresist pattern and including a gate electrode; Doping the polycrystalline silicon layer with a high concentration of impurities using a line as a mask to form a source region and a drain region, forming a first interlayer insulating layer on a gate line, a source region and a drain region on the first interlayer insulating layer; Forming a data line having a source electrode and a drain electrode connected to each other; forming a second interlayer insulating film on the data line; and forming a pixel electrode connected to the drain electrode on the second interlayer insulating film. Is manufactured.

The method may further include forming a barrier rib on the pixel electrode, forming an organic emission layer on a predetermined region on the pixel electrode partitioned by the barrier rib, and forming a common electrode on the organic emission layer. The method may further include forming an auxiliary electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Specifically, the present invention relates to a thin film transistor using a polycrystalline silicon having a low concentration doped region formed through the method shown in FIGS. 1A to 1D and 2A to 2D, and a method of manufacturing the same. First, FIGS. 1A to 1D and A method of forming the lightly doped region will be described in detail with reference to FIGS. 2A through 2D.

Hereinafter, the case where a positive photosensitive photosensitive film is used is demonstrated as an example.

1A to 1D illustrate a step of forming a lightly doped region according to an embodiment of the present invention.

As shown in FIG. 1A, the blocking layer 111 is formed on the substrate 110 and the polysilicon layer 150 is formed thereon. The method of forming the polycrystalline silicon layer 150 is not limited, and generally, a method of forming the polycrystalline silicon layer 150 by depositing amorphous silicon and crystallizing it is used.

Then, as shown in Fig. 1B, a photosensitive film is applied, exposed using a predetermined mask, and the exposed photosensitive film is shaped to form PR1. Then, impurities are doped at low concentration using PR1 as a mask. As a result of the low concentration doping, the portion of the polysilicon layer 150 which is not covered by PR1 is doped at low concentration, and the portion covered by PR1 is not doped. Here, the impurities used for low concentration doping may use either N-type impurities or P-type impurities. In addition, the doping energy used in the low concentration doping of Figure 1b uses a lower energy (15KeV or less) than the conventional low concentration doping energy. This is because low concentration doping is directly performed on the polycrystalline silicon layer as shown in FIG.

Thereafter, as shown in FIG. 1C, after the PR1 is removed, the gate insulating layer 140, the gate electrode 124, and the PR2 are formed. Here, the gate electrode 124 and the PR2 are formed using the following method.

The gate conductive film and the photoresist film are sequentially stacked on the gate insulating layer 140, and then the photoresist film is exposed and developed by using the mask used to form the PR1, thereby forming PR2. Thereafter, the gate conductive film is etched using PR2 as a mask to form the gate electrode 124.

The width | variety of PR1 and PR2 formed in FIG. 1B and FIG. 1C is different. That is, as shown, PR2 has a wider width than PR1. However, as described above, PR1 and PR2 are formed using the same mask. Forming using the same mask, but differently patterning the width of the photosensitive film is as follows.

First, after the photoresist film is formed, the exposure is performed using the same mask at a temperature (below 130 ° C.) to which the bake process is applied, but the exposure dose is varied to control the width of the patterned photoresist film. That is, since the photosensitive film used in the present embodiment uses a positive photosensitive film, the larger the exposure dose, the smaller the width of the patterned photosensitive film. Therefore, when the PR1 is formed, the exposure amount is increased, and when the PR2 is formed, the exposure amount is relatively small.

The width of the photoresist film may be reduced by increasing the treatment time in the ashing step or the plasma pretreatment step as well as the method of controlling the exposure amount. In the case of using this method, when forming PR1, the processing time is relatively long to form a patterned photosensitive film. The above-described exposure dose control, ashing treatment time adjustment, and plasma pretreatment treatment time adjustment method may be used, respectively, but may be used together to adjust the width of the patterned photoresist film.

Then, as shown in Fig. 1D, the PR2 is removed and doped with impurities at a high concentration. The high concentration doping is performed by doping at a higher concentration of impurities than the low concentration doping, or by doping by making the doping energy larger than the doping energy of the low concentration doping. The portion of the polysilicon layer that is not covered by the gate electrode 124 is heavily doped by the high concentration doping, and the portion that is covered by the gate electrode 124 is not heavily doped. The lightly doped portion of FIG. 1B of the portion covered by the gate electrode 124 remains as the low concentration doped region LDD to prevent leakage current later. In addition, the portion of the portion covered by the gate electrode 124 except for the low concentration doped region LLD is not doped at all, and serves as a channel.

Although FIG. 1D illustrates a step of doping impurities at a high concentration after removing PR2, even when a high concentration doping is performed without removing PR2, the same effect is obtained. In addition, the impurity used in the high concentration doping uses the same type of impurity as the impurity used in the low concentration doping in FIG. In other words, when a low concentration doping with N-type impurities is carried out with high concentration doping with an N-type impurity, and when a low concentration doping with a P-type impurity is doped with a high concentration dopant.

The width of PR1 and PR2 may be variously formed through the above-described steps of FIGS. 1A to 1D, but is generally formed to have a difference of about 0.5 μm to about 1.0 μm, and through the bottom of the gate electrode 124. The low concentration doped region LDD is preferably formed to have a width of about 0.5 to 1.0 μm.

2A to 2D illustrate a method of forming a lightly doped region according to another embodiment. The difference from FIGS. 1A to 1D is that a thin gate insulating layer 145 is formed on the polysilicon layer 150 at the time of low concentration doping, and then low concentration doping is described in detail.

First, as shown in FIG. 2A, the blocking layer 111 is formed on the substrate 110, and the polysilicon layer 150 is formed thereon. The method of forming the polycrystalline silicon layer 150 is not limited, and generally, a method of forming the polycrystalline silicon layer 150 by depositing amorphous silicon and crystallizing it is used.

Thereafter, as shown in FIG. 2B, a thin gate insulating film 145 is formed on the polycrystalline silicon layer. Then, a photoresist film is applied thereon, exposed using a predetermined mask, and the exposed photoresist film is developed to form PR1. The thin gate insulating layer 145 is preferably formed to have a thickness of about 100 ~ 200Å. The thin gate insulating layer 145 may prevent the polycrystalline silicon layer from directly contacting the PR1 to prevent contamination from the PR1. The thin gate insulating layer 145 may also protect the polycrystalline silicon layer even during ashing or plasma pretreatment.

Then, impurities are doped at low concentration using PR1 as a mask. As a result of the low concentration doping, the portion of the polysilicon layer 150 which is not covered by PR1 is doped at low concentration, and the portion covered by PR1 is not doped. Here, the impurities used for low concentration doping may use either N-type impurities or P-type impurities. In addition, the doping energy used in the low concentration doping of FIG. 2b uses less energy than the general low concentration doping energy, but uses a low concentration doping energy increased by about 30% compared to the low concentration doping energy used in FIG. This is because, unlike FIG. 1B, the thin gate insulating layer 145 is formed on the polysilicon layer in FIG. 2B.

After the PR1 is removed as shown in FIG. 2C, a gate insulating film having a thickness other than the thickness of the thin gate insulating film 145 is laminated on the thin gate insulating film 145. Thereafter, the gate electrode 124 and the PR2 are formed. The thin gate insulating layer 145 and the remaining gate insulating layer need not be an insulating layer having the same component, and thus may have a double layer structure. In general, since the gate insulating layer is laminated using either SiO 2 or SiN x, the gate insulating layer 140 shown in FIG. 2C has a single layer or double layer structure formed of SiO 2 or SiN x.

The gate electrode 124 and PR2 are formed using the following method.

The gate conductive film and the photoresist film are sequentially stacked on the gate insulating layer 140, and then the photoresist film is exposed and developed by using the mask used to form the PR1, thereby forming PR2. Thereafter, the gate conductive film is etched using PR2 as a mask to form the gate electrode 124.

The widths of PR1 and PR2 formed in Figs. 2B and 2C are different. That is, as shown, PR2 has a wider width than PR1. However, as described above, PR1 and PR2 are formed using the same mask. Although formed using the same mask, the method of patterning the width of the photosensitive film differently is as follows.

First, after the photoresist film is formed, the exposure is performed using the same mask at a temperature (below 130 ° C.) to which the bake process is applied, but the exposure dose is varied to control the width of the patterned photoresist film. That is, since the photosensitive film used in the present embodiment uses a positive photosensitive film, the larger the exposure dose, the smaller the width of the patterned photosensitive film. Therefore, when the PR1 is formed, the exposure amount is increased, and when the PR2 is formed, the exposure amount is relatively small.

The width of the photoresist film may be reduced by increasing the treatment time in the ashing step or the plasma pretreatment step as well as the method of controlling the exposure amount. In the case of using this method, when forming PR1, the processing time is relatively long to form a patterned photosensitive film. The above-described exposure dose control, ashing treatment time adjustment, and plasma pretreatment treatment time adjustment method may be used, respectively, but may be used together to adjust the width of the patterned photoresist film.

Then, as shown in FIG. 2D, the PR2 is removed and the impurities are doped at a high concentration. The high concentration doping is performed by doping at a higher concentration of impurities than the low concentration doping, or by doping by making the doping energy larger than the doping energy of the low concentration doping. The portion of the polysilicon layer that is not covered by the gate electrode 124 is heavily doped by the high concentration doping, and the portion that is covered by the gate electrode 124 is not heavily doped. The lightly doped portion of FIG. 2B of the portion covered by the gate electrode 124 remains as the low concentration doped region LDD to prevent leakage current later. In addition, the portion of the portion covered by the gate electrode 124 except for the low concentration doped region LLD is not doped at all, and serves as a channel.

Although FIG. 2D illustrates a step of doping impurities at a high concentration after removing PR2, the same effect may be obtained even when high concentration doping is performed without removing PR2. In addition, the impurity used in the high concentration doping uses the same type of impurity as the impurity used in the low concentration doping in FIG. In other words, when a low concentration doping with N-type impurities is carried out with high concentration doping with an N-type impurity, and when a low concentration doping with a P-type impurity is doped with a high concentration dopant.

Through the steps of FIGS. 2A to 2D described above, the difference between the widths of PR1 and PR2 may be variously formed. The low concentration doped region LDD is preferably formed to have a width of about 0.5 to 1.0 μm.

Hereinafter, a thin film transistor, which is an embodiment to which the concept of the present invention is applied, and a method of manufacturing the same, will be described in detail with reference to the accompanying drawings.

3 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along line IV-IV '.

3 and 4, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the insulating substrate 110, and a source region 153 and a drain region (on the blocking layer 111) are formed. 155, the polycrystalline silicon layer 150 including the channel region 154 and the lightly doped region LDD is formed. The blocking layer 111 may improve adhesion between the insulating substrate 110 and the polycrystalline silicon layer 150, and may prevent diffusion of conductive impurities in the insulating substrate 110 into the polycrystalline silicon layer 150. Play a role.

A gate insulating layer 140 is formed on the substrate 110 including the polysilicon layer 150. The gate line 121 is formed to extend in one direction on the gate insulating layer 140, and a portion of the gate line 121 extends to extend the channel region 154 and the lightly doped region LDD of the polysilicon layer 150. The portion of the overlapping gate line 121 is used as the gate electrode 124 of the thin film transistor. A lightly doped region LDD is formed under the gate electrode 124 between the source region 153 and the channel region 154, and between the drain region 155 and the channel region 154.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and the polycrystalline silicon layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

An interlayer insulating layer 601 is formed on the gate insulating layer 140 on which the gate line 121 and the storage electrode line 131 are formed. The interlayer insulating layer 601 includes first and second contact holes 181 and 182 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 181, and the portion 173 connected to the source region 153 is a source electrode of the thin film transistor. Used as One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit (not shown).

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 182.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 183 exposing the drain electrode 173.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 183.

The polycrystalline silicon thin film transistor forms a polycrystalline silicon layer thereon after forming a blocking layer on the insulating substrate made of glass to prevent diffusion of conductive impurities present in the insulating substrate into the polycrystalline silicon layer. Thereafter, a PR1 pattern is formed on the polycrystalline silicon layer using a mask for forming a gate electrode. Thereafter, the polycrystalline silicon layer is doped with a low concentration of impurities using PR1 as a mask. After removing the PR1 pattern, a gate insulating film, a gate conductive film, and a photosensitive film are sequentially stacked on the polysilicon layer. The photosensitive film is patterned using a mask for a gate electrode, and the gate conductive film is also patterned using the patterned photosensitive film. In this case, the mask for forming PR1 and the mask for forming PR2 have the same width, width of PR2 than the width of PR1 by controlling the same mask, exposure amount, ashing treatment, or plasma pretreatment. Thereafter, the photoresist pattern is removed and impurities are doped with high concentration. The lightly doped region under the gate electrode is left as a lightly doped region because it is not doped by the gate electrode, and the external region of the gate electrode is doped so that the source region and the drain region are doped. do.

Hereinafter, a method of forming an embodiment of the present invention having the above characteristics will be described.

That is, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 3 and 4 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 5 to 18, 3, and 4.

FIG. 5 is a cross-sectional view at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 3 and 4, respectively, according to one embodiment of the present invention, and FIGS. 6, 8, 10, 13, 15 and FIG. 17 is a layout view at an intermediate stage of a method of manufacturing the thin film transistor array panels illustrated in FIGS. 3 and 4, respectively, according to an embodiment of the present invention, and are arranged in order of processing, and FIG. 7 is the thin film transistor of FIG. 6. 9 is a cross-sectional view of the display panel taken along the line VII-VII ', and FIG. 9A is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX', and FIG. 9B is a cross-sectional view of the thin film transistor array panel of FIG. 8. FIG. 11A is a cross-sectional view taken along the line IX 'of FIG. 9A, and FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI', and FIG. 12 is a thin film of FIG. XI-XI 'line of transistor display board 11 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the line XIV-XIV ′, and FIG. 16 is a cross-sectional view of the thin film transistor array panel of FIG. 15. 18 is a cross-sectional view taken along the line XVI ', and FIG. 18 is a cross-sectional view taken along the line XVIII-XVIII' of FIG. 17.

First, as shown in FIG. 5, the blocking layer 111 is formed on the insulating substrate 110. The blocking layer 111 is formed using a SiH 4 gas and an N 2 O gas by a PECVD method in a vacuum deposition chamber (not shown).

6 and 7, a polysilicon layer is stacked and patterned on the blocking layer 111. Various methods exist for the method of laminating the polycrystalline silicon layer. That is, there is a method of manufacturing a polycrystalline silicon by laminating an amorphous silicon layer and crystallizing it, and a chemical vapor deposition method, and the like, and may be laminated by any method.

Thereafter, PR1 is formed on the polysilicon layer 150 as shown in FIGS. 8 and 9A. The PR1 is patterned by a mask used for forming a gate electrode after laminating a photosensitive film, and is generally formed so that the width of the PR is narrower than the patterning used when forming the gate electrode. The method of narrowing the width of the PR has been described in the description of FIGS. 1A to 1D and thus will be omitted.

After PR1 is formed, as shown in FIG. 9B, low concentration doping is performed with impurities. When low concentration doping is performed, impurities are doped at low concentration except for the portion covered by PR1. The impurities may be either n-type impurities or p-type impurities.

10, 11, and 12, after the PR1 shown in FIGS. 8, 9A, and 9B is removed, the gate insulating layer 140, the gate conductive layer, and the photoresist layer are sequentially stacked, and then PR1 is formed. The gate conductive layer and the photosensitive layer are patterned by using the patterned mask to form the gate line 121, the gate electrode 124, the storage electrode line 131, the storage electrode 133, and the PR2 as shown in FIGS. 10 and 11. Form. Here, the PR2, the gate line 121, the gate electrode 124, the storage electrode line 131, and the storage electrode 133 are patterned using the same mask as the PR1, but are patterned to have a wider width than the PR1.

After the PR2 is removed, it is doped at a high concentration as shown in FIG. 12. As the doping impurity used herein, the same kind as the impurity used in the aforementioned low concentration doping is used. On the other hand, not only when the high concentration doping after removing the PR2 can be doped at a high concentration even without removing the PR2. The polycrystalline silicon layer that is not covered by the gate line including the gate electrode and the storage electrode line including the storage electrode through the high concentration doping is heavily doped, so that the undoped channel region 154 and the heavily doped source are doped. The region 153, the drain region 155, and the sustain electrode region 157 are formed. In addition, in the low concentration doping (see FIG. 9B), the region not covered by the PR1 is covered by the gate electrode in the high concentration doping in FIG. 12, and the portion remains doped in a low concentration.

13 and 14, an insulating material is stacked on the entire surface of the substrate to cover the polysilicon layer 150 to form an interlayer insulating film 601. A first contact hole 181 and a second contact hole 182 exposing the source region 153 and the drain region 155 are formed in the interlayer insulating layer 601 by a photolithography method.

15 and 16, a data conductive layer is formed on the first interlayer insulating layer 601 including the first contact hole 181 and the second contact hole 182, and then patterned to form a data line 171. ) And the drain electrode 175 are formed. The data line 171 is connected to the source region 153 through the first contact hole 181, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 182.

The data line 171 forms a data conductive film by depositing a plurality of conductive materials including a single layer of an aluminum-containing metal such as aluminum neodymium (AIND), an aluminum alloy layer, and a chromium (Cr) or molybdenum (Mo) alloy layer. After forming a photo etch.

17 and 18, an insulating material is stacked on the first interlayer insulating film 9601 including the data line 171 and the drain electrode 175 to form a second interlayer insulating film 602. Thereafter, a third contact hole 183 exposing the drain electrode 175 is formed in the second interlayer insulating layer 602 by a photolithography method.

3 and 4, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the inside of the third contact hole 183. Subsequently, this is patterned to form a contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line. The pixel electrode 190 is connected to the drain electrode 175 through the third contact hole 183. The contact auxiliary member may include a fourth contact hole (not shown) formed over the first and second interlayer insulating layers 601 and 602, the first and second interlayer insulating layers 601 and 602, and the gate insulating layer 140. And one end of the data line 171 and the gate line 121, respectively, through a fifth contact hole (not shown) formed over the ().

The above description is an embodiment in which the method described in FIGS. 1A to 1D is applied to one embodiment. Hereinafter, an embodiment to which the method described in FIGS. 2A to 2D is applied will be described.

19 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 20 is a cross-sectional view of the thin film transistor array panel of FIG. 19 taken along line XX-XX '.

19 and 20, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the insulating substrate 110, and a source region 153 and a drain region 155 are formed on the blocking layer 111. ), The channel region 154 and the lightly doped region LDD are formed. The blocking layer 111 may improve adhesion between the insulating substrate 110 and the polycrystalline silicon layer 150, and may prevent diffusion of conductive impurities in the insulating substrate 110 into the polycrystalline silicon layer 150. Play a role.

A gate insulating layer 140 is formed on the substrate 110 including the polysilicon layer 150. The gate line 121 that is elongated in one direction is formed on the gate insulating layer 140. A portion of the gate line 121 extends to overlap the channel region 154 and the lightly doped region LDD of the polysilicon layer 150, and a portion of the overlapping gate line 121 is a gate electrode of the thin film transistor. 124 is used. A lightly doped region LDD is formed under the gate electrode 124 between the source region 153 and the channel region 154, and between the drain region 155 and the channel region 154. Here, the gate insulating layer 140 may be formed in a double layer. In this case, the lower layer is thinner than the upper layer, and the lower layer preferably has a thickness of about 100˜200 μs. The gate insulating layer 140 is laminated with SiO 2, SiN x, or the like.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and the polycrystalline silicon layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

An interlayer insulating layer 601 is formed on the gate insulating layer 140 on which the gate line 121 and the storage electrode line 131 are formed. The interlayer insulating layer 601 includes first and second contact holes 181 and 182 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 181, and the portion 173 connected to the source region 153 is a source electrode of the thin film transistor. Used as One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit (not shown).

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 182.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 183 exposing the drain electrode 173.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 183.

The polycrystalline silicon thin film transistor forms a polycrystalline silicon layer thereon after forming a blocking layer on the insulating substrate made of glass to prevent diffusion of conductive impurities present in the insulating substrate into the polycrystalline silicon layer. Thereafter, a thin gate insulating film is formed over the polycrystalline silicon layer, and then a PR1 pattern is formed over the thin gate insulating film using a mask for forming the gate electrode. Thereafter, the polycrystalline silicon layer is doped with a low concentration of impurities, and after the PR1 pattern is removed, a gate insulating film having the remaining thickness is laminated on the thin gate insulating film. After the gate conductive film and the photosensitive film are laminated thereon, the gate conductive film and the photosensitive film are patterned by using a gate electrode mask. At this time, the mask forming the PR1, the gate conductive film and the mask patterning the photosensitive film are formed to be larger than the width of the PR1 by adjusting the same mask, the exposure amount, the ashing treatment or the plasma pretreatment. Thereafter, the photoresist pattern is removed and doped, and the lightly doped region under the gate electrode is left as a lightly doped region because it is not doped by the gate electrode, and the outer region of the gate electrode is doped to become a source region and a drain region.

Hereinafter, a method of forming an embodiment of the present invention having the above characteristics will be described.

That is, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 19 and 20 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 21 to 34, 19, and 20.

FIG. 21 is a cross-sectional view at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 19 and 20, respectively, according to one embodiment of the present invention, and FIGS. 22, 24, 26, 29, 31 and FIG. 33 is a layout view at an intermediate stage of the method for manufacturing the thin film transistor array panels illustrated in FIGS. 19 and 20, respectively, according to an embodiment of the present invention, and are arranged in the order of the process, and FIG. 23 is the thin film transistor of FIG. 22. 25 is a cross-sectional view of the display panel cut along the line XXIII-XXIII ', and FIG. 25A is a cross-sectional view of the thin film transistor array panel of FIG. 24 taken along the line XXIV-XXIV', and FIG. 25B is a XXIV- view of the thin film transistor array panel of FIG. FIG. 27A is a cross-sectional view taken along the line XXIV 'and is a cross sectional view of the thin film transistor array panel of FIG. 26 taken along the line XXVII-XXVII', and FIG. 28 is a thin film of FIG. Tran FIG. 27 is a cross-sectional view of the master display panel taken along the line XXVII-XXVII ', and is shown in the next step of FIG. 27, and FIG. 30 is a cross-sectional view of the thin film transistor array panel of FIG. 29 taken along the line XXX-XXX', and FIG. 31 is a cross-sectional view of the thin film transistor array panel of FIG. 31 taken along the line XXXII-XXXII ', and FIG. 34 is a cross-sectional view of the thin film transistor array panel of FIG. 33 taken along the line XXXIV-XXXIV'.

First, as shown in FIG. 21, the blocking layer 111 is formed on the insulating substrate 110. The blocking layer 111 is formed using a SiH 4 gas and an N 2 O gas by a PECVD method in a vacuum deposition chamber (not shown).

Subsequently, as shown in FIGS. 22 and 23, a polycrystalline silicon layer is stacked and patterned on the blocking layer 111. Various methods exist for the method of laminating the polycrystalline silicon layer. That is, there is a method of manufacturing a polycrystalline silicon by laminating an amorphous silicon layer and crystallizing it, and a chemical vapor deposition method, and the like, and may be laminated by any method.

Thereafter, as shown in FIGS. 24 and 25A, a thin gate insulating film 145 is laminated on the polysilicon layer 150, and then PR1 is formed thereon. The thin gate insulating layer 145 is preferably about 100-200 Å, and protects the polysilicon layer 150 by preventing the polycrystalline silicon layer 150 from directly contacting the PR. The PR1 is patterned by using a mask used to form a gate electrode after stacking the photoresist film, and is generally formed to have a narrower PR width than the case of patterning to form a gate electrode. The method of narrowing the width of the PR has been described in the description of FIGS. 2A to 2D and thus will be omitted.

After PR1 is formed, impurities are doped at low concentration in the polycrystalline silicon layer as shown in Fig. 25B. As the impurity used herein, both n-type impurities and p-type impurities can be used. When the low concentration doping, except for the portion covered with PR1, the remaining portion is doped at a low concentration, in this case it is preferable to use the energy increased by about 30% than the low-doped energy in Figure 9b. This is because the thin gate insulating film 145 is formed on the polycrystalline silicon layer 150.

26, 27, and 28, the PR1 shown in FIGS. 24, 25A, and 25B is removed, and then the gate insulating film of the remaining thickness is formed on the thin gate insulating film 145 to obtain a full thickness. The gate insulating layer 140 is formed. The gate conductive layer and the photoresist layer were sequentially stacked thereon, and then the gate conductive layer and the photosensitive layer were patterned by using a mask patterned with PR1 to form the gate line 121 and the gate electrode 124 as shown in FIGS. 26 and 27. The storage electrode line 131, the storage electrode 133, and the PR2 are formed. Here, the PR2, the gate line 121, the gate electrode 124, the storage electrode line 131, and the storage electrode 133 are patterned using the same mask as the PR1, but are patterned to have a wider width than the PR1. After removing PR2, doping is carried out at a high concentration as shown in FIG. In this case, the high concentration doping impurity uses an impurity of the same type as the impurity used in the low concentration doping described above. By doping at a high concentration, the polycrystalline silicon layer not covered by the gate line including the gate electrode and the storage electrode line including the storage electrode is heavily doped, and the undoped channel region 154 and the heavily doped source region ( 153, the drain region 155 and the sustain electrode region 157 are formed, as well as the region that is not covered by PR1 in low concentration doping (see FIG. 25B) is covered by the gate electrode or the like in the high concentration doping in FIG. It remains in a lightly doped state, which becomes a lightly doped region (LDD).

The gate insulating layer 140 is divided into a thin gate insulating layer 145 and a later stacked gate insulating layer. The structure of the thin gate insulating layer 145 and the stacked gate insulating layer may be different from each other. It may have a structure of this double layer. The gate insulating film is laminated with SiO 2, SiN x, or the like.

Next, as shown in FIGS. 29 and 30, an insulating material is stacked on the entire surface of the substrate to cover the polycrystalline silicon layer 150 to form an interlayer insulating film 601. A first contact hole 181 and a second contact hole 182 exposing the source region 153 and the drain region 155 are formed in the interlayer insulating layer 601 by a photolithography method.

31 and 32, a data conductive layer is formed on the first interlayer insulating layer 601 including the first contact hole 181 and the second contact hole 182, and then patterned to form a data line 171. ) And the drain electrode 175 are formed. The data line 171 is connected to the source region 153 through the first contact hole 181, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 182.

The data line 171 forms a data conductive film by depositing a plurality of conductive materials including a single layer of an aluminum-containing metal such as aluminum neodymium (AIND), an aluminum alloy layer, and a chromium (Cr) or molybdenum (Mo) alloy layer. After forming a photo etch.

33 and 34, an insulating material is stacked on the first interlayer insulating film 9601 including the data line 171 and the drain electrode 175 to form a second interlayer insulating film 602. Thereafter, a third contact hole 183 exposing the drain electrode 175 is formed in the second interlayer insulating layer 602 by a photolithography method.

As shown in FIGS. 19 and 20, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, which are transparent materials, are deposited on the second interlayer insulating layer 602 including the inside of the third contact hole 183. Subsequently, this is patterned to form a contact auxiliary member (not shown) connected to the pixel electrode 190 and one end of the gate line or the data line. The pixel electrode 190 is connected to the drain electrode 175 through the third contact hole 183. The contact auxiliary member may include a fourth contact hole (not shown) formed over the first and second interlayer insulating layers 601 and 602, the first and second interlayer insulating layers 601 and 602, and the gate insulating layer 140. And one end of the data line 171 and the gate line 121, respectively, through a fifth contact hole (not shown) formed over the ().

By using the thin film transistor as described above, a lightly doped region can be formed under the gate electrode, and a cost reduction effect can be obtained by using a mask for forming the gate electrode.

The present invention can be used in any structure as long as the thin film transistor using the polycrystalline silicon layer is used, and the embodiment of the present invention applied to the organic EL will be described below.

FIG. 35 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to another exemplary embodiment. FIG. 36 is a cross-sectional view taken along the line XXXVI-XXXVI 'of FIG. 35, and FIG. 37 is a XXXVII- Sectional view taken along the line XXXVII '.

35 to 37, a blocking layer 111 made of silicon oxide or the like is formed on the insulating substrate 110, and polycrystalline silicon layers 153a, 154a, 155a, and 153b are formed on the blocking layer 111. , 154b, 155b, and 157 are formed.

The polysilicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157 may include the first transistor portions 153a, 154a, 155a, the second transistor portions 153b, 154b, 155b, and the storage electrode portion 157. Include. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. In this case, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be doped with n-type impurities. .

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157. On the gate insulating layer 140, a gate line 121 made of a metal such as aluminum, chromium, molybdenum, or an alloy thereof, first and second gate electrodes 123a and 123b, and a storage electrode 133 are formed.

The first gate electrode 123a is formed in the shape of a branch of the gate line 121, and overlaps the channel region (first channel region 154a) of the first transistor, and the second gate electrode 123b is a gate line ( 121 and overlap with the channel region (second channel region 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 123b and overlaps the storage electrode portion 157 of the polycrystalline silicon layer.

One end of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal transmitted from an external driving circuit (not shown).

An interlayer insulating film 801 is formed on the gate line 121, the first and second gate electrodes 123a and 123b, and the storage electrode 133, and a data line 171a and a power line are formed on the interlayer insulating film 801. 171b, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed.

The first source electrode 173a is connected to the first source region 153a as a branch of the data line 171a through a contact hole 181 penetrating through the interlayer insulating film 801 and the gate insulating film 140. The second source electrode 173b is connected to the second source region 153b through a contact hole 184 penetrating through the interlayer insulating film 801 and the gate insulating film 140 as a branch of the power line 171b. The first drain electrode 175a is in contact with the first drain region 155a and the second gate electrode 123b through the contact holes 182 and 183 penetrating the interlayer insulating layer 801 and the gate insulating layer 140. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 185 penetrating through the gate insulating layer 140 and the interlayer insulating layer 801. On the other hand, the power supply line 171b overlaps the sustain electrode 133.

An interlayer insulating film 802 having a contact hole 186 exposing the second drain electrode 175 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the interlayer insulating layer 802 through the contact hole 186. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A partition wall 803 made of an organic insulating material is formed on the pixel electrode 190. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled.

The partition wall 803 is formed by exposing and developing a photosensitive agent containing a black pigment to serve as a light shielding film, and at the same time, the forming process can be simplified. The organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 802. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 is formed of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic emission layer 70. . Here, the power supply line 171b is connected to a constant voltage power supply.

The driving of the thin film transistor array panel for the organic light emitting diode display will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage applied through the data line 171a is transferred to the second gate electrode 123b. When the image signal voltage is applied to the second gate electrode 123b, the second transistor is turned on so that current transmitted through the power supply line 171b is transferred to the common electrode 270 through the pixel electrode 190 and the organic emission layer 70. Will flow. The organic light emitting layer 70 emits light in a specific wavelength band when current flows. The amount of light emitted by the organic light emitting layer 70 varies according to the amount of current flowing, thereby changing the brightness. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the image signal voltage transmitted through the first transistor.

A method of manufacturing the thin film transistor array panel for the organic light emitting diode display described above will be described in detail with reference to FIGS. 38A to 48C and 35 to 37.

38A, 39A, 41A, 43A, 45A, 47A, and 48A are layout views of display panels at respective stages of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIG. 38B. And FIG. 38C is a cross-sectional view taken along the lines XXXVIIIb-XXXVIIIb 'and XXXVIIIc-XXXVIIIc' of FIG. 38A, respectively. FIGS. 39B and 39C are cross-sectional views taken along the lines XXXIXb-XXXIXb 'and XXXIXc-XXXIXc', respectively, of FIG. 39A. 40A and 40B are cross-sectional views taken along the lines XXXIXb-XXXIXb 'and XXXIXc-XXXIXc' of FIG. 39A, respectively, illustrating the next steps of FIGS. 39B and 39C, and FIGS. 41B and 41C respectively. 41A and 41C are cross-sectional views taken along lines XLIb-XLIb 'and XLIc-XLIc' of FIG. 41A, and FIGS. 42A and 42B are cross-sectional views taken along lines XLIb-XLIb 'and XLIc-XLIc' of FIG. 41A, respectively. 43B and 43C show the XLIIIb-XLIIIb 'line and XLIIIc-XL of FIG. 43A, respectively. 44A and 44B are cross-sectional views taken along lines XLIIIb-XLIIIb 'and XLIIIc-XLIIIc' of FIG. 43A, respectively, showing the next steps of FIGS. 43B and 43C, and FIG. 45B and 45C are cross-sectional views taken along the lines XLVb-XLVb 'and XLVc-XLVc' of FIG. 45A, respectively, and FIGS. 46A and 46B are cut along the lines XLVb-XLVb 'and XLVc-XLVc' of FIG. 45A, respectively. 45B and 45C are cross-sectional views, and FIGS. 47B and 47C are cross-sectional views taken along lines XLVIIb-XLVIIb 'and XLVIIc-XLVIIc', respectively, of FIG. 47A, and FIGS. 48B and 48C are respectively. Sectional drawing cut along the lines XLVIIIb-XLVIIIb 'and XLVIIIc-XLVIIIc' of FIG. 48A.

First, as shown in FIGS. 38A to 38C, a silicon oxide or the like is deposited on a substrate to form a blocking layer 111, and then a polycrystalline silicon layer is stacked and patterned on the blocking layer 111. Various methods exist for the method of laminating the polycrystalline silicon layer. That is, there is a method of manufacturing a polycrystalline silicon by laminating an amorphous silicon layer and crystallizing it, and a chemical vapor deposition method, and the like, and may be laminated by any method.

Thereafter, as shown in Figs. 39A to 39C, the first-first photosensitive film pattern PR1-1 is formed on the polycrystalline silicon layer. The first-first photoresist pattern PR1-1 is patterned by using a mask used to form the second gate electrode after applying the photoresist, and generally has a width of PR compared with the case where the pattern is formed to form the gate electrode. It is formed to be narrow. The method of narrowing the width of the PR has been described in the description of FIGS. 1A to 1D and thus will be omitted.

After the 1-1st photosensitive film pattern PR1-1 is formed, impurities are doped at low concentration in the polycrystalline silicon layer as shown in FIGS. 40A to 40B. When the low concentration doping is carried out at low concentration except for the portion covered by the first-first photosensitive film pattern (PR1-1). In the case of the low concentration doping, the present embodiment may be lightly doped with p-type impurities, but may be lightly doped with n-type impurities.

Thereafter, after the first-first photosensitive film pattern PR1-1 is removed, the first-second photosensitive film pattern PR1-2 is formed on the polycrystalline silicon layer as shown in FIGS. 41A to 41C. At this time, as shown in FIGS. 39A to 39C, the 1-2 photoresist pattern PR1-2 is patterned by using a mask used to form a second gate electrode after stacking the photoresist, and generally a gate electrode is formed. In order to form, it forms so that the width | variety of PR may be narrow compared with the case of patterning. The method of narrowing the width of the PR has been described in the description of FIGS. 1A to 1D and thus will be omitted.

After the 1-2 photoresist pattern PR1-2 is formed, impurities are doped at low concentration in the polycrystalline silicon layer as shown in FIGS. 42A to 42B. In the low concentration doping, the remaining portions except the portion covered by the 1-2 photoresist pattern PR1-2 are lightly doped, and the low concentration doping is an n-type impurity that is different from the impurities used in FIGS. 40A and 40B. If the dopant is lightly doped with low concentration, but the impurity used in Figs. 40A and 40B is n-type impurity, it is also lightly doped with p-type impurity.

Thereafter, the 1-2 photoresist pattern PR1-2 is removed, a gate insulating layer 140 is deposited on the polysilicon layer, and a gate metal layer 120 is formed thereon. Thereafter, as shown in FIGS. 43A to 43C, the photoresist film is coated on the gate metal film 120, and then exposed and developed using a mask used to form the second gate electrode. PR2-1). The 2-1 photosensitive film pattern PR2-1 is formed to be narrower than the 1-1 photosensitive film pattern PR1-1, and as described above with reference to FIGS. 1A to 1D, it will be omitted.

Next, the gate metal film 120 is etched using the 2-1 photosensitive film pattern PR2-1 as a mask to form the second gate electrode 123b and the storage electrode 133.

44A and 44B, p-type impurity ions are implanted into the polycrystalline silicon layer of the second transistor unit 150b that is not covered by the 2-1 photoresist pattern PR2-1 and is exposed. The second source region 153b, the second drain region 155b, and the second channel region 154b not doped with impurities are formed. The p-type impurity ions used at this time use impurities of the same type as those of the low concentration doping performed in the steps shown in FIGS. 40A and 40B, and the polycrystalline silicon layer of the first transistor section 150a is covered by the gate metal film. Protected. At this time, since the sustain electrode 157 is protected by the sustain electrode 133 as a portion overlapping the power line 171b formed later, impurities are not doped.

Next, as shown in FIGS. 45A to 45C, after the 2-1 photoresist pattern PR2-1 is removed, exposure and development are performed using a mask used to newly apply the photoresist film and form the first gate electrode. To form the second photosensitive film pattern PR2-2.

The gate metal film 120 is etched using the second photosensitive film pattern PR2-2 as a mask to form the first gate electrode 123a and the gate line 121, and are illustrated in FIGS. 46A and 46B. As described above, the first source region 153a and the first drain region are implanted by implanting n-type impurity ions into the polycrystalline silicon layer of the first transistor unit 150a that is not covered by the second photoresist pattern PR2-2. 155a and the first channel region 154a which is not doped with impurities are formed. At this time, the n-type impurity ions to be used use impurities of the same type as those of the low concentration doping performed in the steps shown in FIGS. 42A and 42B, and include the second transistor portions 153b, 154b, and 155b and the sustain electrode portion ( The 155 is covered and protected by the second-2 photoresist pattern PR2-2.

Next, as shown in FIGS. 47A to 47C, the interlayer insulating layer 801 is stacked on the gate lines 121, 123a, 123b, and 133, and the interlayer insulating layer 801 and the gate insulating layer 140 are formed by a photolithography process. The interlayer and the contact holes 181, 182, 184, and 185 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively, by etching. The insulating layer 801 is etched to form a contact hole 183 exposing one end of the second gate electrode 123b.

Next, the data metal film is stacked and the data lines 171a, 171b, 173a and 173b and the drain electrodes 175a and 175b are formed by a photolithography process.

48A to 48C, an interlayer insulating film 802 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and then the interlayer insulating film 802 is formed by a photolithography process. By etching, the contact hole 186 exposing the second drain electrode 175b is formed.

Subsequently, a metal having excellent reflectivity such as aluminum is deposited on the interlayer insulating layer 802 and patterned by a photolithography process to form a pixel electrode 190 connected to the second drain electrode 175b through the contact hole 186.

Next, as shown in FIGS. 35 to 37, an organic film including a black pigment is coated on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b to expose and develop the partition wall 803. The organic light emitting layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 has a multilayer structure. The organic light emitting layer 70 is deposited after masking, or formed by inkjet printing or the like.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. In addition, when the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed using a metal having excellent reflectivity.

In the above-described FIGS. 35 to 48C, a thin film transistor array panel for an organic light emitting display device and a method of manufacturing the same are described using the method used in FIGS. 1A to 1D. An embodiment of a thin film transistor array panel for a light emitting display device will be described.

FIG. 49 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to another exemplary embodiment. FIG. 50 is a cross-sectional view taken along the line L-L 'of FIG. 49, and FIG. 51 is a LI- of FIG. 49. Sectional view taken along the LI 'line.

49 to 51, a blocking layer 111 made of silicon oxide or the like is formed on the insulating substrate 110, and polycrystalline silicon layers 153a, 154a, 155a, and 153b are formed on the blocking layer 111. , 154b, 155b, and 157 are formed.

The polysilicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157 may include the first transistor portions 153a, 154a, 155a, the second transistor portions 153b, 154b, 155b, and the storage electrode portion 157. Include. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. In this case, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be doped with n-type impurities. .

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157. The gate insulating layer 140 includes a thin gate insulating layer 145. After the thin gate insulating layer 145 is stacked, a gate insulating layer having a remaining thickness is stacked later. The thin gate insulating layer 145 has a thickness of about 100 to 200Å, and both the thin gate insulating layer 145 and the remaining gate insulating layer may be formed of SiO 2 and SiNx, and may be formed of different components to form a double layer. Do.

On the gate insulating layer 140, a gate line 121 made of a metal such as aluminum, chromium, molybdenum, or an alloy thereof, first and second gate electrodes 123a and 123b, and a storage electrode 133 are formed.

The first gate electrode 123a is formed in the shape of a branch of the gate line 121, and overlaps the channel region (first channel region 154a) of the first transistor, and the second gate electrode 123b is a gate line ( 121 and overlap with the channel region (second channel region 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 123b and overlaps the storage electrode portion 157 of the polysilicon layer.

One end of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal transmitted from an external driving circuit (not shown).

An interlayer insulating film 801 is formed on the gate line 121, the first and second gate electrodes 123a and 123b, and the storage electrode 133, and a data line 171a and a power line are formed on the interlayer insulating film 801. 171b, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed.

The first source electrode 173a is connected to the first source region 153a as a branch of the data line 171a through a contact hole 181 penetrating through the interlayer insulating film 801 and the gate insulating film 140. The second source electrode 173b is connected to the second source region 153b through a contact hole 184 penetrating through the interlayer insulating film 801 and the gate insulating film 140 as a branch of the power line 171b. The first drain electrode 175a is in contact with the first drain region 155a and the second gate electrode 123b through the contact holes 182 and 183 penetrating the interlayer insulating layer 801 and the gate insulating layer 140. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 185 penetrating through the gate insulating layer 140 and the interlayer insulating layer 801. On the other hand, the power supply line 171b overlaps the sustain electrode 133.

An interlayer insulating film 802 having a contact hole 186 exposing the second drain electrode 175 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the interlayer insulating layer 802 through the contact hole 186. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A partition wall 803 made of an organic insulating material is formed on the pixel electrode 190. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled.

The partition wall 803 is formed by exposing and developing a photosensitive agent containing a black pigment to serve as a light shielding film, and at the same time, the forming process can be simplified. The organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 802. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 is formed of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic emission layer 70. . Here, the power supply line 171b is connected to a constant voltage power supply.

A method of manufacturing the thin film transistor array panel for the organic light emitting diode display described above will be described in detail with reference to FIGS. 52A to 62C and 49 to 51.

52A, 53A, 55A, 57A, 59A, 61A, and 62A are layout views of display panels in each step of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIG. 52B. And FIG. 52C is a cross-sectional view taken along the line LIIb-LIIb 'and LIIc-LIIc' of FIG. 52A, respectively, and FIGS. 53B and 53C are cross-sectional views taken along the line LIIIb-LIIIb 'and LIIIc-LIIIc' of FIG. 53A, respectively. 54A and 54B are cross-sectional views taken along lines LIIIb-LIIIb 'and LIIIc-LIIIc' of FIG. 53A, respectively, showing the next steps of FIGS. 53B and 53C, and FIGS. 55B and 55C, respectively; 55A and 56B are cross-sectional views taken along the lines LVb-LVb 'and LVc-LVc' of FIG. 55A, and FIGS. 56A and 56B are cross-sectional views taken along the lines LVb-LVb 'and LVc-LVc' of FIG. 55A, respectively. 57B and 57C are cross-sectional views taken along lines LVIIb-LVIIb 'and LVIIc-LVIIc', respectively, of FIG. 57A, respectively. 58A and 58B are cross-sectional views taken along lines LVIIb-LVIIb 'and LVIIc-LVIIc' of FIG. 57A, respectively, illustrating the next steps of FIGS. 57B and 57C, and FIGS. 59B and 59C respectively. 59A and 60B are cross-sectional views taken along lines LIXb-LIXb 'and LIXc-LIXc' of FIG. 59A, and FIGS. 60A and 60B are cross-sectional views taken along lines LIXb-LIXb 'and LIXc-LIXc' of FIG. 59A, respectively. 61B and 61C are cross-sectional views taken along lines LXIb-LXIb 'and LXIc-LXIc' of FIG. 61A, respectively, and FIGS. 62B and 62C are LXIIb-LXIIb 'of FIG. 62A, respectively. Sectional drawing along the line and LXIIc-LXIIc 'line.

First, as shown in FIGS. 52A to 52C, a silicon oxide or the like is deposited on a substrate to form a blocking layer 111, and then a polycrystalline silicon layer is stacked and patterned on the blocking layer 111. Various methods exist for the method of laminating the polycrystalline silicon layer. That is, there is a method of manufacturing a polycrystalline silicon by laminating an amorphous silicon layer and crystallizing it, and a chemical vapor deposition method, and the like, and may be laminated by any method.

Thereafter, as shown in Figs. 53A to 53C, a thin gate insulating film 145 is formed on the polysilicon layer, and the first-first photosensitive film pattern PR1-1 is formed thereon. The first-first photoresist layer pattern PR1-1 is patterned by using a mask used to form the second gate electrode after the photoresist layer is stacked, and generally has a width of PR compared to the case where the first-photoresist layer pattern PR1-1 is patterned to form a gate electrode. It is formed to be narrow. The method of narrowing the width of the PR has been described in the description of FIGS. 2A to 2D and thus will be omitted.

After the 1-1st photosensitive film pattern PR1-1 is formed, impurities are doped at low concentration in the polycrystalline silicon layer as shown in FIGS. 54A and 54B. When the low concentration doping is carried out at low concentration except for the portion covered by the first-first photosensitive film pattern (PR1-1). In the present embodiment, it is lightly doped with p-type impurities but may be lightly doped with n-type impurities.

Thereafter, after removing the first-first photoresist layer pattern PR1-1, the first photoresist layer pattern PR1-2 is formed on the thin gate insulating layer 145 as shown in FIGS. 55A to 55C. do. In this case, as shown in FIGS. 53A to 53C, the first photoresist layer pattern PR1-2 is patterned by using a mask used to form a first gate electrode after stacking the photoresist layer, and generally forms a gate electrode. The width of PR is narrower than that of patterning. The method of narrowing the width of the PR has been described in the description of FIGS. 2A to 2D and thus will be omitted.

After the 1-2 photoresist pattern PR1-2 is formed, impurities are doped at low concentration in the polycrystalline silicon layer as shown in FIGS. 56A and 56B. In the low concentration doping, the remaining portions except the portion covered by the 1-2 photoresist pattern PR1-2 are lightly doped. In the case of the low concentration doping, the present embodiment is doped with n-type impurities. That is, the doping is carried out differently from the low concentration doping performed in the steps shown in Figs. 54A and 54B and its components. Unlike the present embodiment, in the case where low concentration doping is performed using n-type impurities in FIGS. 54A and 54B, low concentration doping is performed using p-type impurities.

After that, the gate insulating layer 140 is removed by removing the 1-2 photoresist pattern PR1-2 and stacking the gate insulating layer 140 by the height of the thin gate insulating layer 145 minus the height of the thin gate insulating layer 145. And the gate metal film 120 is formed thereon. The components of the thin gate insulating layer 145 and the components of the gate insulating layer stacked thereon may be different, and thus may be formed as a double layer. Subsequently, as illustrated in FIGS. 57A to 57C, a photosensitive film is coated on the gate metal film 120, and then exposed and developed to form the second photosensitive film pattern PR2-1. Patterning is performed here using the mask used for forming a 2nd gate electrode. The 2-1 photosensitive film pattern PR2-1 is formed to be wider than the 1-1 photosensitive film pattern PR1-1, and as described above with reference to FIGS. 2A to 2D, it will be omitted.

Next, the gate metal film 120 is etched using the 2-1 photosensitive film pattern PR2-1 as a mask to form the second gate electrode 123b and the storage electrode 133.

58A and 58B, p-type impurity ions are implanted into the polycrystalline silicon layer of the second transistor unit 150b that is not covered by the 2-1 photoresist pattern PR2-1 and is exposed. The second source region 153b, the second drain region 155b, and the second channel region 154b not doped with impurities are formed. The impurity ions used at this time should use the same ions as the low concentration doping impurities performed in the steps shown in FIGS. 54A and 54B. Unlike the present embodiment, when the low concentration doping with n-type impurities is performed, the doping with the n-type impurities is performed. do. On the other hand, the polycrystalline silicon layer of the first transistor portion 150a is covered and protected by the gate metal film. At this time, since the sustain electrode 157 is protected by the sustain electrode 133 as a portion overlapping the power line 171b formed later, impurities are not doped.

Next, as shown in FIGS. 59A to 59C, after the 2-1 photoresist pattern PR2-1 is removed, the photoresist is newly coated, exposed and developed to form the second photoresist pattern PR2-2. do. Patterning is performed here using the mask used for forming a 1st gate electrode. The first gate electrode 123a and the gate line 121 are formed by etching the gate metal film 120 using the second photosensitive film pattern PR2-2 as a mask, as shown in FIGS. 60A and 60B. As described above, the n-type impurity ions are implanted into the polycrystalline silicon layer of the first transistor unit 150a that is not covered by the second photosensitive film pattern PR2-2 and is exposed to the first source region 153a and the first drain. The region 155a and the first channel region 154a which are not doped with impurities are formed. At this time, the second transistor portions 153b, 154b, and 155b and the storage electrode portion 155 are covered and protected by the second-second photosensitive film pattern PR2-2.

Next, as shown in FIGS. 61A to 61C, the interlayer insulating layer 801 is stacked on the gate lines 121, 123a, 123b, and 133, and the interlayer insulating layer 801 and the gate insulating layer 140 are formed by a photolithography process. The interlayer and the contact holes 181, 182, 184, and 185 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively, by etching. The insulating layer 801 is etched to form a contact hole 183 exposing one end of the second gate electrode 123b.

Next, the data metal film is stacked and the data lines 171a, 171b, 173a and 173b and the drain electrodes 175a and 175b are formed by a photolithography process.

62A through 62C, an interlayer insulating film 802 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and then the interlayer insulating film 802 is formed by a photolithography process. By etching, the contact hole 186 exposing the second drain electrode 175b is formed.

Subsequently, a metal having excellent reflectivity such as aluminum is deposited on the interlayer insulating layer 802 and patterned by a photolithography process to form a pixel electrode 190 connected to the second drain electrode 175b through the contact hole 186.

Next, as shown in FIGS. 49 to 51, an organic film including a black pigment is coated on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b to expose and develop the partition wall 803. The organic light emitting layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 has a multilayer structure. The organic light emitting layer 70 is deposited after masking, or formed by inkjet printing or the like.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. In addition, when the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed using a metal having excellent reflectivity.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, in forming the LDD region, a mask used to form the gate electrode is used, and the gate electrode and the LDD region are masked by varying the size of the PR by adjusting the conditions for forming the PR. Forming the same may reduce the manufacturing cost, and by forming the LDD region under the gate electrode, it is possible to improve the reliability of the thin film transistor array panel.

1A to 1D illustrate an embodiment of forming an LDD region according to the present invention.

2A to 2D are diagrams illustrating still another embodiment of forming an LDD region according to the present invention;

3 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along line IV-IV '.

5 is a cross-sectional view at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 3 and 4, respectively, according to one embodiment of the present invention;

6, 8, 10, 13, 15, and 17 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in Figs. 3 and 4, respectively, according to one embodiment of the present invention; The drawings are listed in the order of the process.

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along the line VII-VII ′. FIG.

9A is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX ',

FIG. 9B is a cross-sectional view of the thin film transistor array panel of FIG. 8 taken along the line IX-IX ', and is a view at the next step of FIG. 9A, and FIG.

FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI ′.

FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI ′, illustrating the thin film transistor array panel of FIG.

FIG. 14 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the line XIV-XIV ',

FIG. 16 is a cross-sectional view of the thin film transistor array panel of FIG. 15 taken along the line XVI-XVI ',

FIG. 18 is a cross-sectional view of the thin film transistor array panel of FIG. 17 taken along the line XVIII-XVIII ′,

19 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

20 is a cross-sectional view of the thin film transistor array panel of FIG. 19 taken along a line XX-XX ',

21 is a cross-sectional view at an intermediate stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 19 and 20, respectively, according to one embodiment of the present invention;

22, 24, 26, 29, 31 and 33 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 19 and 20, respectively, according to an embodiment of the present invention. The drawings are listed in the order of the process.

FIG. 23 is a cross-sectional view of the thin film transistor array panel of FIG. 22 taken along a line XXIII-XXIII '.

FIG. 25A is a cross-sectional view of the thin film transistor array panel of FIG. 24 taken along a line XXV-XXV ',

FIG. 25B is a cross-sectional view of the thin film transistor array panel of FIG. 24 taken along a line XXV-XXV ', illustrating the next step of FIG. 9A.

FIG. 27 is a cross-sectional view of the thin film transistor array panel of FIG. 26 taken along a line XXVII-XXVII ',

FIG. 28 is a cross-sectional view of the thin film transistor array panel of FIG. 26 taken along the line XXVII-XXVII ', and is a diagram at the next step of FIG. 27,

FIG. 30 is a cross-sectional view of the thin film transistor array panel of FIG. 29 taken along a line XXX-XXX ',

32 is a cross-sectional view of the thin film transistor array panel of FIG. 31 taken along the line XXXII-XXXII ',

FIG. 34 is a cross-sectional view of the thin film transistor array panel of FIG. 33 taken along the line XXXIV-XXXIV ',

35 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to another exemplary embodiment of the present invention.

36 is a cross-sectional view taken along the line XXXVI-XXXVI 'of FIG. 35,

FIG. 37 is a cross-sectional view taken along the line XXXVII-XXXVII ′ of FIG. 35;

38A, 39A, 41A, 43A, 45A, 47A, and 48A are layout views of display panels at each step of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

38B and 38C are cross-sectional views taken along the lines XXXVIIIb-XXXVIIIb 'and XXXVIIIc-XXXVIIIc', respectively, of FIG. 38A;

39B and 39C are cross-sectional views taken along lines XXXIXb-XXXIXb 'and XXXIXc-XXXIXc', respectively, of FIG. 39A;

40A and 40B are sectional views taken along the lines XXXIXb-XXXIXb 'and XXXIXc-XXXIXc' of FIG. 39A, respectively, illustrating the next steps of FIGS. 39B and 39C;

41B and 41C are cross-sectional views taken along lines XLIb-XLIb 'and XLIc-XLIc', respectively, of FIG. 41A;

42A and 42B are cross-sectional views taken along the XLIb-XLIb 'line and the XLIc-XLIc' line of FIG. 41A, respectively, showing the next steps of FIGS. 41B and 41C;

43B and 43C are cross-sectional views taken along lines XLIIIb-XLIIIb 'and XLIIIc-XLIIIc', respectively, of FIG. 43A;

44A and 44B are cross-sectional views taken along lines XLIIIb-XLIIIb 'and XLIIIc-XLIIIc' of FIG. 43A, respectively, showing the next steps of FIGS. 43B and 43C;

45B and 45C are cross-sectional views taken along lines XLVb-XLVb 'and XLVc-XLVc', respectively, of FIG. 45A;

46A and 46B are cross-sectional views taken along lines XLVb-XLVb 'and XLVc-XLVc' of FIG. 45A, respectively, illustrating the next steps of FIGS. 45B and 45C;

47B and 47C are cross-sectional views taken along lines XLVIIb-XLVIIb 'and XLVIIc-XLVIIc', respectively, of FIG. 47A;

48B and 48C are cross-sectional views taken along the lines XLVIIIb-XLVIIIb 'and XLVIIIc-XLVIIIc' of FIG. 48A, respectively;

49 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to another exemplary embodiment of the present invention.

50 is a cross-sectional view taken along line L-L 'of FIG. 49,

FIG. 51 is a cross-sectional view taken along the line LI-LI 'of FIG. 49;

52A, 53A, 55A, 57A, 59A, 61A, and 62A are layout views of display panels at each step of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

52B and 52C are cross-sectional views taken along lines LIIb-LIIb 'and LIIc-LIIc' of FIG. 52A, respectively;

53B and 53C are cross-sectional views taken along lines LIIIb-LIIIb 'and LIIIc-LIIIc', respectively, of FIG. 53A;

54A and 54B are cross-sectional views taken along lines LIIIb-LIIIb 'and LIIIc-LIIIc' of FIG. 53A, respectively, showing the next steps of FIGS. 53B and 53C;

55B and 55C are cross-sectional views taken along lines LVb-LVb 'and LVc-LVc' of FIG. 55A, respectively;

56A and 56B are sectional views taken along the lines LVb-LVb 'and LVc-LVc' of FIG. 55A, respectively, illustrating the next steps of FIGS. 55B and 55C;

57B and 57C are cross-sectional views taken along lines LVIIb-LVIIb 'and LVIIc-LVIIc', respectively, of FIG. 57A;

58A and 58B are cross-sectional views taken along lines LVIIb-LVIIb 'and LVIIc-LVIIc' of FIG. 57A, respectively, illustrating the next steps of FIGS. 57B and 57C;

59B and 59C are cross-sectional views taken along lines LIXb-LIXb 'and LIXc-LIXc', respectively, of FIG. 59A;

60A and 60B are cross-sectional views taken along lines LIXb-LIXb 'and LIXc-LIXc' of FIG. 59A, respectively, illustrating the next steps of FIGS. 59B and 59C;

61B and 61C are cross-sectional views taken along lines LXIb-LXIb 'and LXIc-LXIc', respectively, of FIG. 61A;

62B and 62C are cross-sectional views taken along lines LXIIb-LXIIb 'and LXIIc-LXIIc' of FIG. 62A, respectively.

<Description of the symbols for the main parts of the drawings>

110: substrate 111: blocking layer

121, 123a, 123b: gate line

124: gate electrode 131: sustain electrode line

133: sustain electrode 140: gate insulating film

145: thin gate insulating film

150, 150a, 150b: polycrystalline silicon layer

153: source region 155: drain region

157: sustain electrode regions 171, 171a: data line

171b: power line

173, 173a, and 173b: source electrode

175, 175a, and 175b: drain electrode

181, 182, 183, 184, 185, 186: contact hole

190: pixel electrode 601, 602: interlayer insulating film

70: organic light emitting layer

Claims (22)

Insulation board, A blocking layer formed on the substrate, A polycrystalline silicon layer formed on the blocking layer and having a source region, a channel region, a drain region, a lightly doped region formed between the source region and the channel region and the drain region and the channel region, respectively; A gate insulating film covering the polycrystalline silicon layer, A gate electrode formed on the gate insulating film, A first interlayer insulating film covering the gate electrode, First and second contact holes formed in the first interlayer insulating layer and exposing portions of the source region and the drain region formed by being doped with the polycrystalline silicon layer, respectively; A data line including a source electrode connected to the source region through the first contact hole; A drain electrode connected to the drain region through the second contact hole, A second interlayer insulating layer covering the data line and the drain electrode and having a third contact hole exposing a portion of the drain electrode; A pixel electrode connected to the drain electrode through a third contact hole on the second interlayer insulating film, The light doped region of the polycrystalline silicon layer is a thin film transistor array panel using polycrystalline silicon positioned below the gate electrode. In claim 1, The gate insulating layer is formed of a double layer, and the lower layer of the thin film transistor array panel using polycrystalline silicon having a thickness of 100 ~ 200Å. Forming a blocking layer on the insulating substrate, Forming a polycrystalline silicon layer on the blocking layer, Applying a first photoresist film on the polysilicon layer, forming a first photoresist pattern using a first mask, and then doping impurities at a low concentration; After removing the first photoresist pattern, sequentially stacking a gate insulating film, a gate conductive layer, and a second photoresist layer; Exposing and developing the second photoresist film using the first mask to form a second photoresist pattern having a width wider than the width of the first photoresist pattern; Patterning the gate conductive layer using the second photoresist pattern as a mask to form a gate line having a width wider than the width of the first photoresist pattern and including a gate electrode; Doping the polycrystalline silicon layer with a high concentration of impurities using the gate line as a mask to form a source region and a drain region, Forming a first interlayer insulating film covering the gate line and having first and second contact holes, Forming a data line having a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole on the first interlayer insulating film; Forming a second interlayer insulating film covering the data line and the drain electrode and having a third contact hole; Forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating layer Method of manufacturing a thin film transistor array panel using polycrystalline silicon comprising a. Forming a blocking layer on the insulating substrate, Forming a polycrystalline silicon layer on the blocking layer, Forming a thin gate insulating film on the polycrystalline silicon layer, Forming a first photoresist pattern on the thin gate insulating layer using a first mask; Doping the polycrystalline silicon layer at low concentration using the first photoresist pattern as a mask; After removing the first photoresist pattern, laminating a gate insulating film having a remaining thickness to be stacked on the thin gate insulating film; Sequentially forming a gate conductive film and a second photosensitive film on the gate insulating film, Forming a second photoresist pattern on the gate conductive layer and the second photoresist layer to have a width wider than a width of a first photoresist pattern by using the first mask; Patterning the gate conductive layer using the second photoresist pattern as a mask to form a gate line having a width wider than the width of the first photoresist pattern and including a gate electrode; Doping the polycrystalline silicon layer with a high concentration of impurities using the gate line as a mask to form a source region and a drain region, Forming a first interlayer insulating film covering the gate line and having first and second contact holes, Forming a data line having a source electrode connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole on the first interlayer insulating film; Forming a second interlayer insulating film covering the data line and the drain electrode and having a third contact hole; Forming a pixel electrode connected to the drain electrode through the third contact hole on the second interlayer insulating layer Method of manufacturing a thin film transistor array panel using polycrystalline silicon comprising a. The method of claim 3 or 4, In order to form a wider width of the second photoresist pattern than the width of the first photoresist pattern, a thin film transistor array panel using polycrystalline silicon using at least one of ashing treatment, plasma treatment, and a method of varying an exposure amount is used. Manufacturing method. The method of claim 3 or 4, And wherein the low concentration doping and the high concentration doping use the same impurities, and the low concentration doping uses a lower doping energy than the high concentration doping. In claim 4, The thin gate insulating film is a method of manufacturing a thin film transistor array panel using a polycrystalline silicon having a thickness of 100 ~ 200Å. In claim 4 or 7, And a constituent material of the thin gate insulating film and the remaining gate insulating film stacked thereon is polycrystalline silicon. Insulation board, A blocking layer formed on the substrate, A polycrystalline silicon layer formed on the blocking layer and having a source region, a channel region, a drain region, a lightly doped region formed between the source region and the channel region and between the drain region and the channel region, A gate insulating film formed on the polycrystalline silicon layer, A gate line formed over the gate insulating film, A first interlayer insulating film formed over the gate line, A data line and a power line formed on the first interlayer insulating film, A second interlayer insulating film formed over the data line, Pixel electrodes formed on the second interlayer insulating film Including, The light doped region of the polycrystalline silicon layer is a thin film transistor array panel using polycrystalline silicon positioned below the gate electrode. In claim 9, The gate insulating layer is formed of a double layer, and the lower layer of the thin film transistor array panel using polycrystalline silicon having a thickness of 100 ~ 200Å. The method of claim 9 or 10, An organic light emitting layer formed on a predetermined region on the pixel electrode, A partition wall surrounding the organic light emitting layer and defining an area of the organic light emitting layer, And a common electrode formed on the organic light emitting layer and the barrier rib. The method of claim 9 or 10, The polycrystalline silicon layer has first and second transistor portions and a sustain electrode portion connected to the second transistor portion, The gate line and the storage electrode part include first and second gate electrodes overlapping the first and second transistor parts, and a storage electrode overlapping the storage electrode part, respectively, The data line includes a first source electrode connected to a source region of the first transistor unit, The power supply line includes a second source electrode connected to the source region of the second transistor unit. A first drain electrode connected to the drain region of the first transistor unit and the second gate electrode, and a second drain electrode connected to the drain region of the second transistor unit; The pixel electrode is connected to the second drain electrode. Thin film transistor array panel using polycrystalline silicon. In claim 12, A thin film transistor array panel using polysilicon further comprising a buffer layer formed between the organic light emitting layer and the common electrode. Forming a blocking layer on the insulating substrate, Forming a polycrystalline silicon layer on the blocking layer, Applying a first photoresist film on the polysilicon layer and forming a first photoresist pattern using a first mask, Doping the polycrystalline silicon layer at low concentration using the first photoresist pattern as a mask; Removing the first photoresist layer pattern and sequentially forming a gate insulating layer, a gate conductive layer, and a second photoresist layer, Exposing and developing the second photoresist film using the first mask to form a second photoresist pattern having a width wider than the width of the first photoresist pattern; Patterning the gate conductive layer using the second photoresist pattern as a mask to form a gate line having a width wider than the width of the first photoresist pattern and including a gate electrode; Doping the polycrystalline silicon layer with a high concentration of impurities using the gate line as a mask to form a source region and a drain region, Forming a first interlayer insulating film over the gate line, Forming a data line having a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line, Forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer Method of manufacturing a thin film transistor array panel using polycrystalline silicon comprising a. Forming a blocking layer on the insulating substrate, Forming a polycrystalline silicon layer on the blocking layer, Forming a thin gate insulating film on the polycrystalline silicon layer, Forming a first photoresist pattern on the thin gate insulating layer using a first mask; Doping the polycrystalline silicon layer at low concentration using the first photoresist pattern as a mask; After removing the first photoresist pattern, laminating a gate insulating film having a remaining thickness to be stacked on the thin gate insulating film; Sequentially forming a gate conductive film and a second photosensitive film on the gate insulating film, Exposing and developing the second photoresist film using the first mask to form a second photoresist pattern having a width wider than the width of the first photoresist pattern; Patterning the gate conductive layer using the second photoresist pattern as a mask to form a gate line having a width wider than the width of the first photoresist pattern and including a gate electrode; Doping the polycrystalline silicon layer with a high concentration of impurities using the gate line as a mask to form a source region and a drain region, Forming a first interlayer insulating film over the gate line, Forming a data line having a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line, Forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer Method of manufacturing a thin film transistor array panel using polycrystalline silicon comprising a. The method of claim 14 or 15, In order to form a wider width of the second photoresist pattern than the width of the first photoresist pattern, a thin film transistor array panel using polycrystalline silicon using at least one of ashing treatment, plasma treatment, and a method of varying the exposure amount is used. Manufacturing method. The method of claim 15, The thin gate insulating film is a method of manufacturing a thin film transistor array panel using a polycrystalline silicon having a thickness of 100 ~ 200Å. The method of claim 15 or 17, And the gate insulating layer is formed of a double layer having a thin gate insulating layer and a double layer having different constituent materials of the remaining gate insulating layer stacked thereon. The method of claim 14 or 15, Forming a partition on the pixel electrode; Forming an organic emission layer on a predetermined region on the pixel electrode partitioned by the partition wall, A method of manufacturing a thin film transistor array panel using polycrystalline silicon, further comprising forming a common electrode on the organic light emitting layer. The method of claim 19, A method of manufacturing a thin film transistor array panel using polycrystalline silicon, further comprising forming an auxiliary electrode in contact with the common electrode. In the method of manufacturing a thin film transistor array panel using polycrystalline silicon having a low concentration doped region, a method of forming a low concentration doped region may include Forming a polycrystalline silicon layer on the substrate, Forming a first photoresist pattern on the polysilicon layer and then doping impurities at a low concentration; Removing the first photoresist pattern and sequentially laminating a gate insulating film, a gate conductive film and a photoresist film, Forming a second photoresist pattern wider than a width of the first photoresist pattern, Patterning the gate conductive layer using the second photoresist pattern as a mask to form a gate line including a gate electrode; And forming a source region and a drain region by doping an impurity into the polysilicon layer using the gate line as a mask. In the method of manufacturing a thin film transistor array panel using polycrystalline silicon having a low concentration doped region, a method of forming a low concentration doped region may include Forming a polycrystalline silicon layer on the substrate, Forming a thin gate insulating film on the polycrystalline silicon layer, Doping impurities at low concentration after forming a first photoresist pattern on the thin gate insulating film, After removing the first photoresist pattern, laminating a gate insulating film having a remaining thickness to be stacked on the thin gate insulating film; Sequentially forming a gate conductive film and a photoresist film on the gate insulating film, Forming a second photoresist pattern wider than a width of the first photoresist pattern, Patterning the gate conductive layer using the second photoresist pattern as a mask to form a gate line including a gate electrode; And forming a source region and a drain region by doping an impurity into the polysilicon layer using the gate line as a mask.