KR100864494B1 - a thin film transistor array panel of using poly silicon and a method for manufacturing the same - Google Patents

Abstract

The LDD TFT region and the Non-LDD TFT region on the transparent insulating substrate including the LDD TFT region and the Non-LDD TFT region are located at both the channel region and the channel region, respectively, and n-type or p-type impurities are doped with pain. A semiconductor layer of polycrystalline silicon is formed which includes source and drain regions. The gate electrodes of the LDD TFT region and the Non-LDD TFT region are formed on the gate insulating film covering the semiconductor layer, and the contact holes of the gate insulating film and the first interlayer insulating film are formed on the first interlayer insulating film covering the gate electrode. Source and drain electrodes connected to the source and drain regions are formed through the through. At this time, in one of the LDD TFT region and the Non-LDD TFT region, the semiconductor layer has a lightly doped region between the channel region and the source and drain regions.

Thin Film Transistors, Polycrystalline Silicon, LDD

Description

A thin film transistor array panel of using poly silicon and a method for manufacturing the same

1 is a cross-sectional view showing the structure of a thin film transistor array substrate according to an embodiment of the present invention;

2 is a cross-sectional view of a first step illustrating a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention;

3A is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention and showing a next step of FIG. 2.

3B is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention and showing a next step of FIG. 3A.

3C is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention and showing a next step of FIG. 3B.

3D is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate in accordance with an embodiment of the present invention, showing the next step of FIG. 3C.

3E is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate in accordance with an embodiment of the present invention, showing the next step of FIG. 3D.                 

4 is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention and showing a next step of FIG. 3E.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate in accordance with an embodiment of the present invention.

6 is a cross-sectional view illustrating a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention and showing a next step of FIG. 5.

The present invention relates to a thin film transistor substrate using polycrystalline silicon and a method of manufacturing the same.

As one of the flat panel display devices which are widely used at present, a liquid crystal display device has two substrates on which a plurality of electrodes for generating an electric field are formed, a liquid crystal layer injected between the two substrates, and is attached to the outer surface of each substrate to emit light. 2. A display device including two polarizing plates for polarizing and controlling the amount of light transmitted by rearranging liquid crystal molecules of a liquid crystal layer by applying a voltage to an electrode. This is because the arrangement of molecules changes when a voltage is applied among various properties of the liquid crystal. In a liquid crystal display device using light transmission or reflection, the liquid crystal does not emit light and thus requires a light source on its own or externally.

In this case, a thin firm transistor array panel is used as a circuit board for driving each pixel independently in a liquid crystal display. The thin film transistor array substrate includes a scan signal wiring or a gate wiring for transmitting a scan signal and an image signal line or data wiring for transmitting an image signal, and a thin film transistor and a thin film transistor connected to the gate wiring and the data wiring. It includes a pixel electrode connected to and used to display an image.

In this case, amorphous silicon or polycrystalline silicon is mainly used as a semiconductor layer of the thin film transistor. When polycrystalline silicon is used, the field effect mobility is greater than that when amorphous silicon is used, so that a better display image quality can be obtained, and the inside of the substrate is driven. The circuit can be integrated simultaneously with the formation of a thin film transistor, thereby reducing the material cost of the integrated circuit (IC) or the associated process equipment.

However, the semiconductor layer of polycrystalline silicon has a disadvantage of low leakage resistance and a large leakage current.A lightly doped domain (LDD) structure having a lightly doped region between the channel portion and the heavily doped source and drain regions is used to minimize this. In this case, a problem of reducing the ON current occurs. Therefore, it is preferable to design a thin film transistor having an LDD structure and a thin film transistor not having an LDD structure together on the same substrate.

However, when manufacturing the substrate on which the thin film transistor is formed, it is preferable to reduce the number of masks in order to reduce the production cost in manufacturing through a photolithography process using a mask, which includes a thin film transistor having an LDD structure and a thin film transistor having no thin film transistor. In order to manufacture the thin film transistor substrate, the photolithography process using two masks needs to be additionally performed, resulting in a complicated manufacturing process and a rise in manufacturing cost.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, to provide a thin film transistor array substrate having a thin film transistor having an LDD structure and a thin film transistor not having an LDD structure, and simplifying the manufacturing process thereof.

In the present invention for solving this problem, after forming a photosensitive film pattern having a partly different thickness in one photolithography process, a portion thicker than another part to protect the lower layer from being etched when etching a certain film Doping masks having different sizes are formed in different regions of the substrate.

More specifically, in the thin film transistor array substrate according to the present invention, the first region and the second region above the transparent insulating substrate including the first region and the second region are located in both the channel region and the channel region, respectively, and are n-type or A semiconductor layer of polycrystalline silicon is formed including a source and a drain region in which p-type impurities are painfully doped. Gate electrodes in the first and second regions are formed on the gate insulating film covering the semiconductor layer, and a source is formed on the top of the first interlayer insulating film covering the gate electrode through contact holes of the gate insulating film and the first interlayer insulating film. And source and drain electrodes connected to the drain region. In this case, in one of the first and second regions, the semiconductor layer has a lightly doped region between the channel region and the source and drain regions.

In the method for manufacturing a thin film transistor array substrate according to the present invention, first, first and second semiconductor layers are formed in each of the first and second regions on the transparent insulating substrate. Subsequently, a gate insulating layer covering the first and second semiconductor layers is formed, and first and second gate electrodes including an upper layer and a lower layer are formed in the first and second regions, respectively. Subsequently, the upper layer is removed from the second gate electrode in the second region, and n-type or p-type impurities are implanted at high concentration into the first and second semiconductor layers using the first and second gate electrodes as masks, thereby providing a source and A drain region is formed. Subsequently, the upper layer is removed from the first gate electrode in the first region, and then n-type or p-type impurities are ion-implanted at low concentration into the first and second semiconductor layers using the first and second gate electrodes as masks. A lightly doped region is formed inside the source and drain regions of the semiconductor layer. Next, source and drain electrodes electrically connected to the source and drain regions of the first and second semiconductor layers are formed, respectively.

Here, forming the first and second gate electrodes, removing the upper layer of the second gate electrode, and removing the upper layer of the first gate electrode may be performed by a photolithography process using one photoresist pattern. It is preferred to include a first portion corresponding to the first gate electrode and a second portion corresponding to the second gate electrode and having a thickness thinner than the first portion.

In forming the first and second gate electrodes, removing the upper layer of the second gate electrode, and removing the upper layer of the first gate electrode, first, a lower layer and an upper layer are sequentially stacked on the gate insulating layer, and then the upper layer of the upper layer A photosensitive film pattern including first and second portions is formed on the substrate. Subsequently, the upper layer and the lower layer are etched using the photoresist pattern as an etching mask, and then the second portion of the photoresist layer is removed, and the exposed upper layer is first removed. Then, the first portion is removed and then the top film is removed secondly.

At this time, the photoresist pattern is preferably formed using one mask having a partly different transmittance.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A method of manufacturing a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a thin film transistor array substrate according to an exemplary embodiment of the present invention includes a LDD TFT region in which a thin film transistor having a low doping domain (LDD) structure, which is a low concentration doping region, is formed, and a thin film transistor having no LDD structure. It includes a non-LDD region is formed.

In this case, polycrystalline silicon layers 151 and 152 are formed on the transparent insulating substrate 110, and silicon dioxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the substrate 110 on which the polycrystalline silicon layers 151 and 152 are formed. The gate insulating film 1400 is formed over the entire surface with a thickness of 500 to 3,000 Å. Here, the semiconductor layers 151 and 152 of both regions are located at both the channel regions 1516 and 1526 and the channel regions 1516 and 1526 which are not doped with impurities in the center, and the n-type or p-type impurities are highly concentrated. Source regions 1513 and 1523 and drain regions 1515 and 1525 which are doped. However, unlike the semiconductor layer 152 of the non-LDD TFT region, the semiconductor layer 151 of the LDD TFT region is located between the channel region 1516 and the source and drain regions 1513 and 1515, and is n-type or p. Type doped regions 1512 and 1514 which are lightly doped.

The gate insulating layer 140 is connected to a gate line (not shown), receives a scan signal or a gate signal from the gate line, and overlaps the channel regions 1516 and 1526 of the semiconductor layers 151 and 152. Gate electrodes 1231 and 1232 are formed. On the other hand, a storage wiring for forming a storage capacitor may be formed on the same layer as the gate electrodes 1231 and 1232 so as to overlap the pixel electrode formed later.

A first interlayer insulating layer 810 is formed on the gate wiring including the gate electrodes 1231 and 1232, and the gate insulating layer 140 and the first interlayer insulating layer 810 are formed of an LDD TFT region and a non-LDD-TFT region. Have contact holes 813, 815, 823, 825 exposing source and drain regions 1513, 1523, 1515, and 1525, respectively. In this case, the first interlayer insulating film 810 may have an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD film) or low dielectric constant deposited by plasma enhanced chemical vapor deposition (PECVD). The branch may be made of an organic insulating material. Here, the a-Si: C: O film and the a-Si: O: F film (low dielectric constant CVD film) deposited by such a PECVD method have a dielectric constant of 4 or less (dielectric constant of 2 to 4). ), The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by PECVD method have a 4 to 10 times faster process time than the silicon nitride film. It is also very advantageous in terms of.

The first interlayer insulating layer 810 of the LDD TFT region and the non-LDD-TFT region is connected to a data line (not shown) that crosses the gate line to define a pixel region, and is connected to the source through the contact holes 813 and 823. Source electrodes 1731 and 1732 connected to the regions 1513 and 1523 are formed, respectively, and are formed on the opposite side of the source electrodes 1731 and 1732 around the gate electrodes 1231 and 1232 in a metal pattern for data wiring. Drain electrodes 1751 and 1752 are formed, and the drain electrodes 1751 and 1752 are connected to the drain regions 1515 and 1525 through the contact holes 815 and 825.                     

The second interlayer insulating film 820 is covered with a second interlayer insulating film 820 on the first interlayer insulating film 810 on which data wirings including the source and drain electrodes 1731, 1732, 1751, and 1752 are formed. The passage holes 821 and 822 exposing the drain electrodes 1751 and 1752 are drilled through the hole.

A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or the like is formed on the second interlayer insulating film 820 of the pixel area defined by the intersection of the data line (not shown) and the gate line (not shown), or Pixel electrodes 191 and 192 are formed of a conductive material having reflectivity such as silver or silver alloy or aluminum or aluminum alloy, and the pixel electrodes 191 and 192 are formed in the LDD TFT region and the Non-LDD-TFT region. The via electrodes 821 and 822 are connected to the drain electrodes 1751 and 1752, respectively.

In the thin film transistor array substrate for a liquid crystal display according to the exemplary embodiment of the present invention, both the LDD TFT region and the non-LDD-TFT region thin film transistor are illustrated as being connected to the pixel electrode.

Next, a method of manufacturing the TFT array substrate for a liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 6.

First, as shown in FIG. 2, the amorphous silicon layer is laminated on the transparent insulating substrate 110 and irradiated with a laser to crystallize the amorphous silicon layer into a polycrystalline silicon layer, and then patterned by a photolithography process using a mask to form an LDD TFT region. And semiconductor layers 151 and 152 in the non-LDD-TFT region. In this case, heat treatment or laser annealing may be performed to increase the crystallinity of the polycrystalline silicon layers 151 and 152.

Next, as shown in FIG. 3A, a gate insulating layer 140 made of silicon nitride is deposited by chemical vapor deposition, and then a lower layer 120 of aluminum or an aluminum alloy, which is a conductive material for gate wiring having low resistance, The upper layer 130 made of chromium is deposited by a method such as sputtering, and then a photosensitive film is applied thereon to a thickness of 1 μm to 2 μm. Thereafter, the photoresist film is irradiated with light through a mask and then developed to form photoresist patterns 212 and 214, as shown in FIG. 3A. At this time, among the photoresist patterns 212 and 214, the first portion 214 positioned at the channel portion A of the LDD TFT region, that is, the portion corresponding to the gate electrodes 1231 and 1331 formed later, is a non-LDD TFT. The thickness of the region C is greater than that of the second portion 212 in the portion corresponding to the channel portion C of the region, that is, the gate electrodes 1232 and 1332 which are formed later, and all the photoresist of the other portion B is removed. In this case, the ratio of the thicknesses of the photosensitive films 212 and 214 having different thicknesses should be different according to the process conditions in the etching process which will be described later.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.                     

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin second portion 212 is exposed to light using a photoresist film made of a reflowable material, and is exposed using a conventional mask that is divided into a portion that can completely transmit light and a portion that cannot fully transmit light. And a portion of the photoresist film flows down to a portion where the photoresist film does not remain.

Subsequently, as shown in FIG. 3B, the photoresist patterns 212 and 214 are used as etch masks to sequentially etch the lower layers, that is, the upper layer 130 and the lower layer 120, to sequentially align the LDD TFT region and the non- Gate electrodes 1231, 1331, 1232, and 1332 are formed in the LDD-TFT region, respectively. In this case, the lower layers 1231 and 1232 are etched into the upper layers 1331 and 1332 and patterned into an undercut structure.

Subsequently, as illustrated in FIG. 3C, an etch back process of removing a portion of the photoresist layer through ashing is performed to remove the second portion remaining on the gate electrodes 1232 and 1332 in the non-LDD TFT region. The photosensitive film 212 is removed to expose the top film 1332 of the gate electrode made of chromium in the non-LDD TFT region.

Subsequently, as shown in FIG. 3D, chromium exposed through chromium front etching is removed to expose the lower layer 1232 of the gate electrode including aluminum, which is a low-resistance conductive material, in the non-LDD TFT region. The first portion 214 is removed to expose the top layer 1331 of the gate electrode made of chromium in the LDD-TFT region. Next, source and drain regions defining the channel regions 1516 and 1526 are ion-implanted with high concentrations of N-type or P-type impurities into the semiconductor layers 151 and 152 using the gate electrodes 1232 and 1331 as doping masks. (1513, 1515, 1523, 1525). In this case, the doping mask is the upper layer 1331 in the LDD TFT region, and the lower layer 1232 is in the non-LDD TFT region.

Next, as shown in FIG. 3E, a second chromium front etching is performed to remove the top layer 1331 of chromium exposed from the LDD TFT region, and to implant N-type or P-type impurities at low concentration. At this time, since the source and drain regions 1513, 1515, 1523, and 1525 are already heavily doped in the non-LDD TFT region and the LDD TFT region, low concentration doped regions are not formed in these regions, and only in the LDD TFT region. Lightly doped regions 1512 and 1514 are formed in the semiconductor layer 151 that is covered by the film 1331.

Next, as shown in FIG. 4, the first interlayer insulating film 810 is formed thereon to insulate the gate wiring including the gate electrodes 1231 and 1232 from the data wiring including the data line and drain electrode to be formed later. Let's do it. In this case, the first interlayer insulating film 810 may be formed by growing an a-Si: C: O film or an a-Si: O: F film by chemical vapor deposition (CVD) and applying an organic insulating material. It may be formed by. For example, the contact holes 813, 815, which expose the source and drain regions 1513, 1523, 1515, and 1525 of the semiconductor layer by patterning the first interlayer insulating layer 810 and the gate insulating layer 140 by a photolithography process using a mask. 825, 823.

Subsequently, as shown in FIG. 5, metals for data wiring such as chromium (Cr) or molybdenum (Mo) are deposited and patterned to form source electrodes 1731 and 1732 and drain electrodes 1175 and 1752. In this case, the source and drain regions 1513, 1523, 1515, and 1525 may be formed through the contact holes 813, 823, 815, and 825.

Subsequently, as shown in Fig. 6, the second interlayer insulating film 820 is coated on the upper portion thereof, and then the upper portions of the drain electrodes 1751 and 1752 are etched to form the transit holes 821 and 822. At this time, the second interlayer insulating layer 820 is formed. The insulating film 820 may be formed by growing an a-Si: C: O film or an a-Si: O: F film by chemical vapor deposition (CVD), or may be formed by applying an organic insulating material.

Finally, as shown in FIG. 1, the pixel electrodes 191 and 192 are formed by depositing and patterning a transparent conductive material such as ITO. In this step, the pixel electrodes 191 and 192 are connected to the drain electrodes 1715 and 1725 through the way holes 821 and 822, respectively.

In the method of manufacturing a thin film transistor array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention, the photosensitive film is patterned into two parts having different thicknesses, and thus, as an etch mask, a different film can be used as an ion implantation mask. A thin film transistor having an LDD structure and a thin film transistor not having an LDD structure may be formed on a substrate of a single photolithography process.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the method of manufacturing a thin film transistor substrate according to the present invention, a photo-etching film having a different thickness is used to have an LDD region in a single photolithography process on the same substrate by changing an ion implantation mask according to a region. By forming the semiconductor layer and the semiconductor layer having no LDD region, the manufacturing process may be simplified, and thus manufacturing cost may be minimized.

Claims (13)

delete delete delete Forming first and second semiconductor layers in each of the first and second regions formed on the transparent insulating substrate, Forming a gate insulating film covering the first and second semiconductor layers, Forming first and second gate electrodes including an upper layer and a lower layer, respectively, in the first and second regions; Removing an upper layer from the second gate electrode in the second region, Forming a source and a drain region by ion implanting n-type or p-type impurities into the first and second semiconductor layers at high concentration using the first and second gate electrodes as masks; Removing an upper layer from the first gate electrode in the first region, Low concentration doping regions inside the source and drain regions of the first semiconductor layer by ion implantation of low concentrations of n-type or p-type impurities into the first and second semiconductor layers using the first and second gate electrodes as masks. Forming a, and Forming source and drain electrodes electrically connected to the source and drain regions of the first and second semiconductor layers, respectively. Including; And the gate insulating layer is formed to be continuous to the first and second regions. In claim 4, Forming the first and second gate electrodes, removing the upper layer of the second gate electrode, and removing the upper layer of the first gate electrode by a photolithography process using a photoresist pattern Method of manufacturing a substrate. In claim 5, The photoresist pattern may include a first portion corresponding to the first gate electrode and a second portion corresponding to the second gate electrode and having a thickness thinner than that of the first portion. In claim 6, Forming the first and second gate electrodes, removing the upper layer of the second gate electrode and removing the upper layer of the first gate electrode, Sequentially stacking the lower layer and the upper layer on the gate insulating layer; Forming a photoresist pattern including the first and second portions on the upper layer; Etching the upper layer and the lower layer using the photoresist pattern as an etching mask; Removing the second portion, Firstly removing the top film; Removing the first portion, Removing the upper layer in a second manner. In claim 7, And the photosensitive film pattern uses one mask having a partially different transmittance. In claim 4, The method of claim 1, wherein the upper layer and the lower layer are formed in an undercut structure in the first and second gate electrode forming steps. In claim 4, A method of manufacturing a thin film transistor array substrate, wherein in the step of ion implanting impurities at a high concentration to form source and drain regions, and in the step of ion implanting impurities at a low concentration to form a low concentration doped region, the same impurities are doped. In claim 4, And the first and second semiconductor layers are polycrystalline silicon layers. In claim 7, The removing of the second portion may include an etch back process using an ashing process. delete

Images