KR101277220B1 - Tft substrate and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and a method of manufacturing the same. According to an aspect of the present invention, there is provided a method of fabricating a thin film transistor substrate, the method comprising: forming a semiconductor layer divided into a high concentration impurity region, a low concentration impurity region, and a channel region according to an amount of doping of an impurity on an insulating substrate; Forming a gate insulating film to cover the semiconductor layer; Forming a gate electrode on the gate insulating film; Forming a protective film to cover the gate electrode; A first gate contact hole and a second gate contact hole for simultaneously patterning the passivation film and the gate insulating film to expose a portion of the high concentration impurity region in the gate insulating film, and a first passivation film corresponding to the first gate contact hole and the second gate contact hole in the protective film. Forming a contact hole and a second passivation layer contact hole; Forming a barrier layer in contact with the high concentration impurity region in the first gate contact hole and the second gate contact hole; Sequentially forming a transparent electrode layer, a data wiring layer, and a photosensitive film on the passivation film; Exposing and developing the photoresist so that the photoresist has different heights and exposes a portion of the data wiring layer; Patterning the data line layer exposed to the outside by the photosensitive film to form a data line and a source electrode; Removing the transparent electrode layer exposed to the outside by the remaining photoresist to form a pixel electrode and a data lower layer; Applying an additional photoresist film on the remaining photoresist film; Uniformly ashing the photoresist film and the additional photoresist film to leave the photoresist film covering both sides of the data line; And patterning the data wiring layer exposed to the outside by ashing the photosensitive film and the additional photosensitive film to expose the pixel electrode to the outside, and forming a drain electrode and a storage capacitor line. Accordingly, the number of masks can be reduced, and the signal delay of the data line can be minimized by preventing the phenomenon that the line width of the data line is reduced during the patterning process of the data wiring layer.

Description

Thin film transistor substrate and its manufacturing method {TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a conventional thin film transistor substrate,

FIG. 2 is a cross-sectional view taken along II-II 'of FIG. 1;

3A to 3I are views for sequentially explaining a method of manufacturing a conventional thin film transistor substrate;

4A and 4B are a layout view and a cross-sectional view of a thin film transistor according to the present invention;

5A to 5N are cross-sectional views taken along line IVb-IVb 'of FIG. 4A to sequentially illustrate a method of manufacturing a thin film transistor substrate;

6A to 6H are cross-sectional views taken along the line VI-VI ′ of FIG. 4A to sequentially illustrate a method of manufacturing a thin film transistor substrate.

7 is a view for explaining the problem to be solved by the present invention.

Description of Reference Numerals of Major Parts of the Drawings [

100: thin film transistor substrate 110: insulating substrate

111 buffer layer 120 semiconductor layer

130: gate insulating film 131: first insulating film contact hole

132: second insulating film contact hole 140: gate wiring layer

141: gate line 142: gate electrode

143: storage line 150: barrier layer

160: protective film 161: first protective film contact hole

162: second passivation layer contact hole 170: transparent electrode layer

171: pixel electrode 172: data lower layer

180: data wiring layer 181: data line

182: source electrode 183: drain electrode

184: storage capacity line

The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate provided with a thin film transistor including a semiconductor layer made of polysilicon and a method of manufacturing the same.

2. Description of the Related Art In recent years, a flat display device having advantages of small size and light weight among display devices has been spotlighted. Examples of such flat panel displays include liquid crystal displays, organic light emitting diodes, plasma display panels, and the like.

Such display devices commonly include a thin film transistor substrate provided with a thin film transistor. The thin film transistor provided on the thin film transistor substrate may be classified into a poly TFT, an amorphous TFT, an organic TFT, and the like according to the material of the semiconductor layer.

Here, the structure of the thin film transistor substrate 1 having the poly TFT is formed as shown in FIGS. 1 and 2. In the following description, an n-type thin film transistor and a p-type thin film transistor, which are formed by doping n-type impurities and p-type impurities, respectively, in the display area will be described as an example.

As shown in Figs. 1 and 2, a buffer layer 3 is formed on the entire surface of the insulating substrate 2, and a semiconductor layer 4 is formed on the buffer layer 3, respectively. The semiconductor layer 4 is divided into a plurality of regions 4a, 4b, 4c, and 4d according to the amount and type of the doped impurities.

On the semiconductor layer 4, a gate insulating film 5 having an opening for exposing one region 4c of the semiconductor layer is formed.

Gate wirings 6a, 6b, 6c are provided on the gate insulating film 5 in parallel with each other. Gate lines 6a, 6b, and 6c are parallel to the gate line 3a between the gate line 6a extending in one direction, the gate electrode 6b branched from the gate line 6a, and the gate line 3a. And a storage line 6c provided.

The interlayer insulating film 7 is formed on the gate wirings 6a, 6b, 6c. An opening corresponding to the opening formed in the gate insulating film 5 is formed in the interlayer insulating film 7.

On the interlayer insulating film 7, data wirings 8a, 8b, 8c, and 8d are formed. The data lines 8a, 8b, 8c, and 8d are insulated from and intersected with the gate line 6a to define a pixel region from the data line 8a so as to partially overlap the gate electrode 6b. A storage capacitor line formed to overlap the source electrode 8b branched off, the drain electrode 8c separated from the source electrode 8b with the gate electrode 6b interposed therebetween, and the storage line 6c. 8d is formed.

On the data wires 8a, 8b, 8c, and 8d, a protective film 9a having a drain contact hole for exposing a part of the drain electrode 8c is formed, and on the protective film 9a through a drain contact hole, the drain electrode 8c is formed. Is connected to the pixel electrode 9b.

A method of manufacturing the thin film transistor substrate 1 having such a structure will be described with reference to FIGS. 3A to 3I.

First, as shown in FIG. 3A, a buffer layer 3 made of an inorganic material such as SiO ₂ is formed on the entire surface of the insulating substrate 2. Then, a semiconductor material layer including amorphous silicon is formed on the buffer layer 3. Subsequently, heat is applied to the semiconductor material layer using a laser or the like to crystallize the amorphous silicon into poly Si. The semiconductor layer 4 is formed by patterning the semiconductor material layer into a desired shape through a photolithography process using a first mask.

Subsequently, as shown in FIG. 3B, after the photoresist film PR is formed on the semiconductor layer 4, an opening for exposing a part of the semiconductor layer 4 to the photoresist film PR is formed using the second mask. do. Then, n-type impurities are implanted into the semiconductor layer 4d exposed through the opening.

After the remaining photoresist film PR of FIG. 3B is removed, as shown in FIG. 3C, the gate insulating film 5 and the gate wiring layer 6 covering the semiconductor layer 4 are sequentially formed. After the photoresist film PR is formed on the gate wiring layer 6, the photoresist film PR is left only in a desired region through an exposure and development process using a third mask.

The gate wiring layer 6 is patterned using the remaining photoresist film PR of FIG. 3B to form the gate electrode 6b, the storage line 6c, and the gate line (not shown) of FIG. 3D. Although not shown, the photoresist film PR is formed to cover the gate electrode 6b, the storage line 6c, and the gate line (not shown). Then, the fourth mask is used to form the photoresist film PR having an opening that covers all of the semiconductor layers 4 constituting the n-type thin film transistor and exposes only the semiconductor layers constituting the P-type thin film transistor. . Then, p-type impurities are implanted into the semiconductor layer constituting the P-type thin film transistor on the driving circuit side.

Next, as shown in FIG. 3E, after the remaining photoresist film PR is removed, the photoresist film PR is again formed on the gate electrode 6b, the storage line 6c, and the gate line (not shown). Then, the photosensitive film PR is exposed and developed to expose the portion 4c to be formed of the high concentration impurity region of the semiconductor layer 4 using the fifth mask. Then, a high concentration of n-type implants impurities.

Although not shown, after removing the photoresist film PR, a low concentration of n-type impurities is implanted into the semiconductor layer 4 to form a low concentration of impurity regions (Lightly Doped Domain).

3F, after forming the interlayer insulating film 7 on the gate electrode 6b, the storage line 6c, and the gate line (not shown), a high concentration impurity region is formed using the sixth mask. An opening for exposing the gap is formed in the interlayer insulating film 7.

Next, as shown in FIG. 3G, the source electrode 8b, the drain electrode 8c, and the data line (not shown) connected to the semiconductor layer 4 through the opening of the interlayer insulating film 7 using the seventh mask. ) And the storage capacitance line 8d.

As shown in Fig. 3H, a protective film 9a having an opening for exposing a part of the drain electrode 8c is formed using an eighth mask.

Finally, as shown in FIG. 3I, after forming the pixel electrode connected to the drain electrode 8c through the opening of the protective film 9a, patterning the pixel electrode 9b into a desired shape using a ninth mask. do. As a result, a thin film transistor substrate having p-type and n-type thin film transistors is completed.

However, all the above-described methods should use nine masks. The process using a single mask requires a series of processes such as cleaning, coating of the photoresist film PR, mask alignment, exposure, development cleaning, etc., which is complicated and requires a large manufacturing cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor substrate which can reduce the number of masks and prevent a phenomenon in which the line width of the data line is reduced during the patterning of the data line layer, thereby minimizing signal delay of the data line.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate, which can reduce the number of masks and prevent the signal line width of the data line from being reduced in the process of patterning the data line layer.

According to the present invention, the first object is an insulating substrate; A semiconductor layer formed on the insulating substrate and divided into a high concentration impurity region, a low concentration impurity region, and a channel region according to the doping amount of the impurity; A gate insulating film covering the semiconductor layer and having a first gate contact hole and a second gate contact hole exposing a portion of the high concentration impurity region; A barrier layer formed in the first gate contact hole and the second gate contact hole to be in contact with the high concentration impurity region; A gate electrode provided in a region corresponding to the channel region on the gate insulating film; A protective film covering the gate electrode and having a first protective film contact hole and a second protective film contact hole corresponding to the first and gate contact holes and the second gate contact hole; A pixel electrode and a data lower layer formed on the passivation layer and contacting the barrier layer through the first and second passivation layer contact holes; It is achieved by a thin film transistor substrate comprising a data line, a source electrode, a drain electrode and a storage capacitor line formed on the data lower layer.

The semiconductor layer may include a storage region, and the semiconductor layer may be formed on each side of the channel region in order with low concentration impurity regions and high concentration impurity regions, and the storage region may be located on one side of any one of the high concentration impurity regions. Can be.

The storage line may be formed to partially overlap the storage capacitor line in the gate insulating layer on the storage area.

In addition, the pixel electrode and the data lower layer may be simultaneously formed, and may include indium tin oxide (ITO) or indium zinc oxide (IZO).

The data lower layer may be positioned below the data line, the source electrode, the drain electrode, and the storage capacitor line, and may be electrically connected to each other.

The source electrode and the drain electrode may be electrically connected to the barrier layer through the data lower layer.

The source electrode may be branched from the data line, the drain electrode may be spaced apart from the source electrode with respect to the gate electrode, and the storage capacitor line may be formed to overlap the storage area.

Here, a buffer layer may be interposed between the insulating substrate and the semiconductor layer.

The barrier layer may include molybdenum (Mo).

Another object of the present invention is to form a semiconductor layer, which is divided into a high concentration impurity region, a low concentration impurity region and a channel region according to the doping amount of impurities on an insulating substrate; Forming a gate insulating film to cover the semiconductor layer; Forming a gate electrode on the gate insulating film; Forming a protective film to cover the gate electrode; A first gate contact hole and a second gate contact hole for simultaneously patterning the passivation film and the gate insulating film to expose a portion of the high concentration impurity region in the gate insulating film, and a first gate contact hole and the second gate contact hole corresponding to the protective film. Forming a protective contact and a second protective contact; Forming a barrier layer in contact with the high concentration impurity region in the first gate contact hole and the second gate contact hole; Sequentially forming a transparent electrode layer, a data wiring layer, and a photosensitive film on the passivation film; Exposing and developing the photoresist so that the photoresist has different heights and exposes a portion of the data wiring layer; Patterning the data line layer exposed to the outside by the photosensitive film to form a data line and a source electrode; Removing the transparent electrode layer exposed to the outside by the remaining photoresist to form a pixel electrode and a data lower layer; Applying an additional photoresist film on the remaining photoresist film; Uniformly ashing the photoresist film and the additional photoresist film to leave the photoresist film covering both sides of the data line; Patterning a data wiring layer exposed to the outside by ashing of the photosensitive film and the additional photoresist to expose the pixel electrode to the outside, and forming a drain electrode and a storage capacitor line. Is achieved.

Here, the forming of the barrier layer may include: sequentially forming a barrier layer and a photosensitive film on the protective film; Uniformly ashing the photosensitive film as a whole to leave the photosensitive film only in the first and second protective film contact holes; Patterning the barrier layer to leave the barrier layer only in the first and second gate contacts.

The barrier layer may include molybdenum (Mo).

The exposing and developing of the photosensitive film may include: arranging a mask including an opening through which light is transmitted, a blocking part through which light is blocked, and a slit part having a light transmittance lower than the opening; Exposing the photosensitive film using a mask; And developing the photoresist to leave the photoresist only in regions corresponding to the pixel electrode and the data underlayer.

The photoresist of the region corresponding to the data lower layer may be made thicker than the photoresist of the region corresponding to the pixel electrode, and the photoresist of the region corresponding to the pixel electrode and the data lower layer may be removed.

In addition, the data lower layer may be provided under the data line, the source electrode, the drain electrode, and the storage capacitor line.

In this case, the exposed portion of the photoresist film is a positive type removed during development, and the mask corresponds to a region where the blocking portion is to be formed of a data line, a source electrode, a drain electrode, and a storage capacitor line, and an opening is formed in the region between the pixel electrode and the data lower layer. Correspondingly, the slit portion may be disposed to correspond to the region to be formed as the pixel electrode.

In addition, the portion exposed by the photosensitive film is removed, and the data wiring layer is patterned into a data line, a source electrode, and other regions, and the other regions are drain electrodes in the process of patterning the data wiring layer to expose the pixel electrodes to the outside. And may be patterned into storage lines.

Further, in the step of applying the additional photoresist film, the additional photoresist film may be formed thicker than the upper surface of the pixel electrode and the data underlayer on the side of the pixel electrode and the data underlayer.

Here, the data wiring layer may be patterned by wet etching.

The photoresist may be removed to a uniform thickness as a whole.

In addition, the additional photoresist film may be applied thinner than the photoresist film applied on the data wiring layer.

In the step of uniformly ashing the photoresist film and the additional photoresist film as a whole, the photoresist film remains only on the region to be formed of the data line, the source electrode, the drain electrode and the storage capacitor line by the ashing, and the additional photoresist film is the data line. It may be formed to cover both side surfaces of the source electrode and other regions.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the following description, the fact that a film (layer) is formed (located) on another film (layer) means that not only the two films (layers) are in contact but also another film (layer) exists between the two films (layers). It also includes the case.

4A is a layout view of a thin film transistor substrate 100 according to the present invention, and FIG. 4B is a cross-sectional view taken along line IVb-IVb 'of FIG. 4A.

As shown in FIGS. 4A and 4B, the buffer layer 111 is formed on the entire surface of the insulating substrate 110, and the semiconductor layer 120 is formed on the buffer layer 111.

The buffer layer 111 is mainly made of silicon oxide, and prevents alkali metal or the like in the insulating substrate 110 from entering the semiconductor layer 120.

The semiconductor layer 120 is divided into a plurality of regions 120a, 120b, 120c, and 120d according to the amount and type of the doped impurities. The semiconductor layer 120 includes a low concentration impurity region 120b in which low concentrations of ions are implanted on both sides of the channel region 120a where no ions are implanted, and a high concentration impurity region 120c in which high concentrations of ions are implanted. It is arranged. The storage region 120d doped with n-type impurities is located at one side of any one of the highly concentrated impurity regions 120c. The low concentration impurity region 120b is doped with a low concentration of impurity ions (eg, n−) and is formed to disperse hot carriers. On the other hand, the high concentration impurity region 120c is doped with a high concentration of impurity ions (eg, n +) and is in contact with at least a portion of the source electrode 182 and the drain electrode 183, which will be described later. The reason for doping impurities in the storage area 120d is to lower the resistance of the storage area 120d.

A gate insulating layer 130 having first and second gate contact holes 131 and 132 exposing the high concentration impurity region 120c is formed on the semiconductor layer 120. The gate insulating layer 130 may be made of silicon oxide or silicon nitride.

Gate wirings 141, 142, and 143 arranged in parallel to each other are provided on the gate insulating film 130. The gate lines 141, 142, and 143 may be parallel to the gate line 141 between the gate line 141 extending in one direction, the gate electrode 142 branched from the gate line 141, and the gate line 141. The storage line 143 is provided. The gate wirings 141, 142, and 143 may be a metal single layer or multiple layers, and may include molybdenum, manganese, tungsten, nickel, aluminum, chromium, gold, silver, alloys thereof, and the like.

The barrier layer 150 is formed in the first insulating film contact hole 131 and the second insulating film contact hole 132. The barrier layer 150 may include molybdenum. The barrier layer 150 removes an oxide film generated when the transparent electrode layer 170 made of indium tin oxide (ITO) or indium zinc oxide (IZO) and the semiconductor layer 120 to be described later are removed. To lower the contact resistance between the layers 120.

The passivation layer 160 is formed on the gate lines 141, 142, and 143, the barrier layer 150, and the gate insulating layer 130. First and second passivation layer contact holes 161 and 162 exposing the barrier layer 150 are formed in the passivation layer 160. The passivation layer 160 may be made of an organic insulating material. The organic insulating material may include an acrylic polymer.

The transparent electrode layer 170 is formed on the passivation layer 160. The transparent electrode layer 170 includes a pixel electrode 171 formed in the pixel region and a data lower layer 172 formed under the data lines 181, 182, 183, and 184. here. The pixel area is an area where an image is implemented as a space formed by crossing the gate lines 141 and the data lines 181. A portion of the transparent electrode layer 170 formed in the pixel region constitutes the data lower layer 172. That is, some of the transparent electrode layers 170 formed in the pixel region are the data underlayer 172, and some are the pixel electrodes 171. In detail, the data lower layer 172 is a transparent electrode layer 170 positioned below the data line 181, below the source electrode 182, below the drain electrode 183, and below the storage capacitor line 184. . The pixel electrode 171 is charged with a pixel voltage applied through the thin film transistor T, and a part of the data lower layer 172 is connected to the barrier layer 150 through the first and second passivation layer contact holes 161 and 162. It is connected. The transparent electrode layer 170 includes indium tin oxide (ITO) or indium zinc oxide (IZO).

Data lines 181, 182, 183, and 184 are formed on the transparent electrode layer 170. The data lines 181, 182, 183, and 184 cross the gate line 141 to define a pixel area, a source electrode 182 and a gate electrode 142 branched from the data line 181. ) And a drain electrode 183 separated from the source electrode 182 and a storage capacitor line 184 overlapping the storage line 143 to form a storage capacitor. The data lines 181, 182, 183, and 184 may be metal single layers or multiple layers, and may include molybdenum, manganese, tungsten, nickel, aluminum, chromium, gold, silver, alloys thereof, and the like. The data lines 181, 182, 183, and 184 are electrically connected to the lower data layer 172. That is, the source electrode 182 and the drain electrode 183 are connected to the semiconductor layer 120 through the data lower layer 172 and the barrier layer 150. In particular, the data wirings 181 and 182 have a multilayer structure in which the data lower layer 172 made of indium tin oxide (ITO) or indium zinc oxide (IZO) and the data wirings 181, 182, 183, and 184 are electrically connected. Since the cross-sectional area of 183 and 184 is increased, the resistance of the data lines 181, 182, 183, and 184 is reduced, thereby facilitating the transmission of control and data signals input from the outside.

Hereinafter, a method of manufacturing a polysilicon thin film transistor according to the present invention will be described with reference to FIGS. 5A to 5M and 6A to 6H. 5A to 5M are cross-sectional views taken along line IVb-IVb 'of FIG. 4A to sequentially explain a method of manufacturing a thin film transistor substrate. 5A to 5M are cross-sectional views illustrating a manufacturing process of a p-type thin film transistor formed on a driving circuit unit side. 6A through 6H are cross-sectional views taken along the line VI-VI ′ of FIG. 4A to sequentially illustrate a method of manufacturing a thin film transistor substrate.

Meanwhile, prior to the description, the photoresist film used in the following description may be an organic material, and may be a positive photosensitive material from which an exposed part is removed or a negative photosensitive material from which an unexposed part is removed. .

First, as shown in FIG. 5A, an insulating material such as SiOx is deposited on the insulating substrate 110 by a plasma enhanced chemical vapor deposition (PECVD) method to form a buffer layer 111. Subsequently, an amorphous semiconductor layer such as amorphous silicon is formed on the buffer layer 111 by PECVD, and then the amorphous semiconductor layer is crystallized and a semiconductor material layer is formed into a desired shape through a photolithography process using a first mask. Is patterned to form semiconductor layers 120 and 125. In this case, the crystallization method may be a well-known high-temperature crystallization method and a low-temperature crystallization method, but when using the insulating substrate 110 of glass, a low-temperature crystallization method of sequentially irradiating a laser having a high energy to the amorphous semiconductor It is preferable to use.

Subsequently, as shown in FIG. 5B, after the photoresist layer 200 is formed on the semiconductor layers 120 and 125, the opening h exposing a part of the semiconductor layer 120 is exposed using the second mask. It forms in 200. The opening h is provided to correspond to the region where the storage capacitor is to be formed. Then, n + impurities are injected into the semiconductor layer 120 exposed through the opening h. As a result, the storage region 120d is formed in the semiconductor layer 120. The reason for injecting the impurities is to lower the resistance in the storage area 120d.

Next, as shown in FIG. 5C, after the silicon oxide or silicon nitride is deposited to form the gate insulating layer 130, the gate wiring layer is formed by using any one of sputtering, evaporation, and electroless plating. 140 is formed.

After the photoresist film 200 is coated on the gate wiring layer 140, as shown in FIG. 5D, a third mask is used to expose a region of the semiconductor layer 125 that will constitute the p-type thin film transistor. The photosensitive film 200 is exposed and developed. As a result, the gate wiring layer 140 on the semiconductor layer 120 to form the n-type thin film transistor is entirely covered by the photosensitive film 200. The photosensitive film 200 is covered on the gate wiring layer 140 corresponding to the gate electrode 145 of the p-type thin film transistor (see FIG. 5E).

Subsequently, as shown in FIG. 5E, the exposed gate line layer 140 is patterned using a photolithography process to form a gate electrode 145 constituting the p-type thin film transistor. Subsequently, the semiconductor layer 125 to form the p-type thin film transistor by doping the p + impurity into the undoped region 125a where the impurities are not implanted and the doped region 125b positioned on both sides of the undoped region 125a. Form. Here, the undoped region 125a becomes a channel. On the other hand, unlike the illustrated, after removing the remaining photosensitive film 200 may be doped with p + impurities.

Next, after the remaining photoresist film 200 is removed, the photoresist film 200 is applied to the entire surface, and the photoresist film 200 is exposed and developed using a fourth mask to form a desired shape. That is, as shown in FIG. 5F, the photosensitive film 200 includes an upper portion of the gate wiring layer 140 corresponding to the portion to be formed as the gate electrode of the n-type thin film transistor and a gate wiring layer corresponding to the portion to be formed as the storage line ( An upper portion of the 140 and a p-type thin film transistor are formed to cover a region to be formed.

When the photoresist film 200 having the desired shape is completed, as shown in FIG. 5G, the gate wiring layer 140 is etched to form the gate electrode 142 and the storage line 143 to form the n-type thin film transistor. At the same time, a gate line (not shown) is also formed. Here, the etching method is a wet etch (wet etch) is used. Since the wet etching method is applied, the gate electrode 142 and the storage line 143 formed are smaller than the width of the photosensitive film 200 positioned on the gate electrode 142 and the storage line 143. That is, the gate electrode 142 and the storage line 143 are etched inwardly than the pattern of the photoresist layer 200 by wet etching. The reason for the wet etching is to form the low concentration impurity region 120b in the semiconductor layer 120 without using an additional mask. Subsequently, the semiconductor layer 120 to form the n-type thin film transistor by doping n + impurity is formed into the channel region 120a where the impurities are not injected and the high concentration impurity region 120c located at both sides of the channel region 120a. do. On the other hand, the storage region 120d previously prepared is provided at one side of the high concentration impurity region 120c.

Thereafter, as shown in Fig. 5H, the remaining photoresist film 200 is removed and doped with a low concentration of n- impurity. As a result, the semiconductor layer 120 includes a low concentration impurity region 120b in which low concentrations of ions are implanted on both sides of the channel region 120a where no ions are implanted, and a high concentration impurity region in which high concentrations of ions are implanted ( 120c) is formed. The low concentration impurity region 120b can be formed because the gate electrode 142 (see FIG. 5G) is etched inwardly from the photoresist layer 200 (see FIG. 5G) pattern by the above-described wet etching.

Next, the passivation layer 160 is formed to cover the gate electrodes 141 and 145 and the storage line 143. As shown in FIG. 5I, first and second insulating film contact holes 131 and 132 exposing a part of the high concentration impurity region 120c and a part of the doping region 125b are exposed using a fifth mask. The first and second protective film contact holes 161 and 162 are formed at the same time.

Next, as shown in FIG. 5J, the barrier layer 150 and the photoresist layer 200 are sequentially stacked on the passivation layer 160. The barrier layer 150 is a conductive metal layer containing molybdenum (Mo) or the like. On the other hand, it is a thick organic material of the photosensitive film 200 formed on the barrier layer 150. Therefore, the photoresist film 200 is applied on the barrier layer 150 as the contact holes 131, 132, 161, and 162 are filled. Accordingly, the thickness d2 of the photosensitive film 200 positioned on the contact holes 131, 132, 161, and 162 is formed to be thicker, and the thickness d1 of the other photosensitive film 200 is formed to be relatively thin. do.

Thereafter, as shown in FIG. 5K, a strip or ashing process is performed on the photosensitive film 200 as a whole. Since the photoresist film 200 having a thickness of d1 is uniformly removed by a strip or ashing process, the photoresist film 200 remains on the contact holes 131, 132, 161, and 162. The photosensitive film 200 is removed in regions other than 131, 132, 161, and 162.

Next, the barrier layer 150 is etched. The barrier layer 150 exposed to the outside is removed by removing the photoresist film 200 by etching the barrier layer 150 (see FIG. 5K). As the remaining photoresist layer 200 is removed along with the etching of the barrier layer 150, a part of the barrier layer 150 covered by the photoresist layer 200 is also removed. Accordingly, as shown in FIG. 5L, the barrier layer 150 remains only at the lower side of the contact holes 131, 132, 161, and 162, so that the barrier layer 150 may have a high concentration impurity region 120c or a doped region 125b. Contact with As such, the reason for forming the barrier layer 150 is to remove the oxide film generated when the transparent electrode layer 170 made of indium tin oxide (ITO) or indium zinc oxide (IZO) and the semiconductor layer 120 will be described later. In order to reduce contact resistance between the transparent electrode layer 170 and the semiconductor layer 120.

Thereafter, as shown in FIG. 5M, the transparent electrode layer 170 and the data wiring layer 180 are sequentially stacked on the passivation layer 160. The transparent electrode layer 170 may include indium tin oxide (ITO) or indium zinc oxide (IZO). The data wiring layer 180 may be a metal single layer or multiple layers, and may include molybdenum, manganese, tungsten, nickel, aluminum, chromium, gold, silver, alloys thereof, and the like. The data line layer 180 is electrically connected to the lower transparent electrode layer 170.

Subsequently, as illustrated in FIG. 5N, the photosensitive film 200 is coated on the data wiring layer 180.

The following process will be described based on the cross-sectional view taken along VI-VI 'of FIG. 4A.

6A is a cross-sectional view taken along the line VI-VI ′ of FIG. 4A when the process to FIG. 5N is performed. As shown in FIG. 6, the VI-VI ′ region of FIG. 4A includes an insulating substrate 110, a buffer layer 111, a gate insulating layer 130, a passivation layer 160, a transparent electrode layer 170, and a data wiring layer 180. And the photosensitive film 200 are sequentially stacked.

In this state, as shown in FIG. 6B, the sixth mask 300 is disposed on the photosensitive film 200. Here, the sixth mask 300 may be a half tone mask or a slit mask. For example, when the slit mask and the positive photosensitive film 200 are applied, as shown in FIG. 6B, the sixth mask 300 includes a slit part 310 formed of a slit and an opening through which light is transmitted. 320 and the blocking unit 330 is blocked light. The slit portion 310 is a region where the light transmittance is lower than the opening 320. 6B, the exposure of the photosensitive film 200 is different depending on the area. Here, the arrangement of the slit part 310, the opening part 320, and the blocking part 330 may include a data line 181 to be formed, a source electrode 182 (see FIGS. 4A and 4B), and a drain electrode 183, 4A and 4B. And storage capacity lines 184 (see FIGS. 4A and 4B). Although not shown, portions corresponding to the blocking unit 330 may include a data line 181, a source electrode 182 (see FIGS. 4A and 4B), a drain electrode 183, and FIGS. 4A and 4B. 4. Referring to FIG. 4A and FIG. 4B, a portion corresponding to the slit part 310 may be a region in which pixel electrodes 171 (see FIGS. 4A and 4B) will be described later. The portion corresponding to the opening 320 includes an area between the pixel electrode 171 (see FIGS. 4A and 4B) and the data line 181 and the source electrode 182 (see FIGS. 4A and 4B), and the pixel electrode 171. 4A and 4B) and the gate line 141 (see FIGS. 4A and 4B) and the gate electrodes 142 and 4A and 4B. Here, the intersection of the data line 181 and the gate line 142 (FIGS. 4A and 4B) may be designed to correspond to the blocking unit 330.

Subsequently, when the exposed photosensitive film 200 is developed, as shown in FIG. 6C, all of the photosensitive film 200 exposed by the opening 320 is removed, and the photosensitive film 200 not exposed by the blocking unit 330 is removed. ) Is hardly removed, and only a part of the photosensitive film 200 which is relatively exposed by the slit part 310 is removed. That is, the photoresist layer 200 positioned in the region corresponding to the data lower layer 172 is made thicker than the photoresist layer 200 positioned in the region corresponding to the pixel electrode 171, and the pixel electrode 171 and the data lower layer 172. ), The photosensitive film 200 in the region corresponding to) is removed.

Thereafter, the data wiring layer 180 (see FIG. 6C) is patterned based on the remaining photosensitive film 200 to remove the data wiring layer 180 (see FIG. 6C) which is not covered by the photosensitive film 200. As a result, the data wiring layer 180 (see FIG. 6C) is separated into the data line 181 and the source electrode 182 (see FIGS. 4A and 4B) and other regions 185 as shown in FIG. 6D. . Although not shown, the data line 181, the source electrode 182, and other regions 185 are separated on both sides of the gate line 141 (FIGS. 4A and 4B). In addition, during the patterning process, the height of the photosensitive film 200 is lowered.

Next, the transparent electrode layer 170 (refer to FIG. 6D) is patterned based on the remaining photoresist film 200. As a result, the transparent electrode layer 170 (refer to FIG. 6D) exposed to the outside is removed. As shown in FIG. 6E, the data lower layer 172 and the pixel electrode 171 positioned below the data line 181 are removed. Is formed. A thin photosensitive film 200 remains on the data line 181, the source electrode 182, and the other regions 185.

In such a situation, the data line 181, the source electrode 182, and other regions 185 are patterned to form the data line 181, the source electrode 182 (see FIGS. 4A and 4B), and the drain electrode 183. 4A, 4B) and storage capacity lines Storage capacity lines 184 (see FIGS. 4A, 4B) should be formed.

To this end, the remaining photoresist film 200 is uniformly ashed to remove the low photoresist film 200, and the data line 181, the source electrode 182 (see FIGS. 4A and 4B), and the drain electrode ( 183, see FIGS. 4A, 4B) and the photoresist film 200 only on regions to be formed by storage capacitor lines 184, see FIGS. 4A, 4B. In order to expose the pixel electrode 171 to the outside, a portion of the region 185 other than the data line 181 and the source electrode 182 which is not covered by the photoresist layer 200 is wet-etched. Remove However, in this process, the data line 181 is etched twice. That is, the data line 181 is etched twice in the patterning process of the data wiring layer 180 (refer to FIG. 6C) and the patterning process for exposing the pixel electrode 171 to the outside.

By etching twice, a phenomenon in which the line width of the data line 181 decreases occurs as shown in FIG. That is, a problem arises in that the resistance is increased due to the decrease in the line width of the data line 181, which is initially designed, and thus the delay of the data signal. In addition, the process margin (process margin) is reduced, there is a problem that the process stability is reduced.

In order to solve this problem, in the present invention, as shown in FIG. 6F, an additional photosensitive film 250 is further formed in the state of FIG. 6E. Since the additional photoresist 250 includes an organic material having a predetermined viscosity, more photoresist 250 is applied to the recessed area than the surroundings when the photoresist 250 is applied. That is, the additional photoresist film 250 is formed thicker on the upper surface of the pixel electrode 171 and the data lower layer 172 on the side of the pixel electrode 171 and the data lower layer 172. Accordingly, the photoresist film 250 is applied to the remaining photoresist film 200 with a thickness of d3, but the photoresist film 250 is applied with a thickness of d4 thicker than d3 at the edge of the recessed area.

In this state, as shown in FIG. 6G, when the photoresist film and the additional photoresist films 200 and 250 are uniformly ashed as a whole, the photoresist film and the additional photoresist films 200 and 250 remain only in a thick region. In the other regions, both the photoresist film and the additional photoresist films 200 and 250 are removed. That is, the photoresist film 250 remains on the edge of the recessed region, and the photoresist film 200 remains on the data line 180. The photoresist layer 200 remaining at the edge of the recessed area covers both side surfaces of the data line 181 and the data lower layer 172. More specifically, although not shown, the photoresist film 200 remains only on the region to be formed of the data line 181, the source electrode 182, the drain electrode 183, and the storage capacitor line 184 by ashing. The additional photoresist film 250 is formed to cover both sides of the data line 181, the source electrode 182, and the other region 185.

Subsequently, as illustrated in FIG. 6H, a region not covered by the photoresist layer 200 is removed from the regions 185 other than the data line 181 and the source electrode 182 by wet etching. 171) to the outside. At the same time, a drain electrode 183 (see FIGS. 4A and 4B) and a storage capacitor line 184 (see FIGS. 4A and 4B) are formed. In the above-described process, since the photoresist film 200 covers both sides of the data line 181 and the data lower layer 172 at the edge of the recessed region s, the data line 181 is different from the process of FIG. As a result, it is etched only once. Accordingly, the phenomenon in which the line width of the data line 181 is reduced is minimized, so that the data signal is not delayed. In addition, the process margin is improved, making the process stable.

In particular, in the present invention, since only six masks are required in manufacturing the poly-type thin film transistor substrate, the manufacturing cost is reduced and productivity is improved.

As described above, according to the present invention, there is provided a thin film transistor substrate which can reduce the number of masks and prevent a phenomenon in which the line width of the data line is reduced in the process of patterning the data line layer, thereby minimizing signal delay of the data line.

In addition, a method of manufacturing a thin film transistor substrate which can reduce the number of masks and prevent a phenomenon in which the line width of the data line is reduced in the process of patterning the data line layer can be minimized.

Claims (22)

An insulating substrate; A semiconductor layer formed on the insulating substrate and divided into a high concentration impurity region, a low concentration impurity region, and a channel region according to the doping amount of the impurity; A gate insulating film covering the semiconductor layer and having a first gate contact hole and a second gate contact hole exposing a portion of the high concentration impurity region; A barrier layer formed in the first gate contact hole and the second gate contact hole to contact the high concentration impurity region; A gate electrode provided in a region corresponding to the channel region on the gate insulating layer; A passivation layer covering the gate electrode and having a first passivation layer contact hole and a second passivation layer contact hole corresponding to the first and gate contact holes and the second gate contact hole; A pixel electrode and a data lower layer formed on the passivation layer and contacting the barrier layer through the first and second passivation layer contact holes; A thin film transistor substrate comprising: a data line, a source electrode, a drain electrode, and a storage capacitor line formed on the data lower layer. The method of claim 1, The semiconductor layer includes a storage area, In the semiconductor layer, the low concentration impurity regions and the high concentration impurity regions are sequentially formed on both sides of the channel region, respectively. The storage region is a thin film transistor substrate, characterized in that located on one side of any one of the high concentration impurity region. 3. The method of claim 2, And a storage line is formed in the gate insulating layer on the storage area to partially overlap the storage capacitor line. The method of claim 1, The pixel electrode and the data lower layer are formed at the same time, the thin film transistor substrate comprising an indium tin oxide (ITO) or indium zinc oxide (IZO). 3. The method of claim 2, The data lower layer is positioned below the data line, the source electrode, the drain electrode, and the storage capacitor line, and is electrically connected to each other. 6. The method of claim 5, And the source electrode and the drain electrode are electrically connected to the barrier layer through the data lower layer. 6. The method of claim 5, The source electrode is branched from the data line, the drain electrode is spaced apart from the source electrode around the gate electrode, and the storage capacitor line is formed to overlap the storage area. Board. The method of claim 1, The thin film transistor substrate of claim 1, wherein a buffer layer is interposed between the insulating substrate and the semiconductor layer. The method of claim 1, The barrier layer includes molybdenum (Mo). Forming a semiconductor layer on the insulating substrate, the semiconductor layer being divided into a high concentration impurity region, a low concentration impurity region, and a channel region according to an amount of doping of an impurity; Forming a gate insulating film to cover the semiconductor layer; Forming a gate electrode on the gate insulating film; Forming a protective film to cover the gate electrode; A first gate contact hole and a second gate contact hole for simultaneously patterning the passivation layer and the gate insulating layer to expose a portion of the high concentration impurity region in the gate insulating layer; Forming a first passivation layer contact hole and a second passivation layer contact hole corresponding to the sphere; Forming a barrier layer in contact with the heavily doped impurity region in the first gate contact hole and the second gate contact hole; Sequentially forming a transparent electrode layer, a data wiring layer, and a photosensitive film on the passivation layer; Exposing and developing the photoresist so that the photoresist has different heights and exposes a portion of the data wiring layer; Patterning the data line layer exposed to the outside by the photosensitive film to form a data line and a source electrode; Removing the transparent electrode layer exposed to the outside by the remaining photoresist to form a pixel electrode and a data lower layer; Applying an additional photoresist film on the remaining photoresist film; Uniformly ashing the photoresist film and the additional photoresist film to leave the photoresist film covering both sides of the data line; And patterning the data wiring layer exposed to the outside by the ashing of the photosensitive film and the additional photoresist to expose the pixel electrode to the outside, and forming a drain electrode and a storage capacitor line. Manufacturing method. The method of claim 10, Forming the barrier layer, Sequentially forming the barrier layer and the photosensitive film on the protective film; Uniformly ashing the photoresist to leave the photoresist only in the first and second passivation layers; And patterning the barrier layer to leave the barrier layer only in the first and second gate contact openings. The method of claim 10, The barrier layer comprises molybdenum (Mo) method of manufacturing a thin film transistor substrate. The method of claim 10, Exposing and developing the photosensitive film, Arranging a mask including an opening through which light is transmitted, a blocking unit from which light is blocked, and a slit portion having a light transmission lower than that of the opening; Exposing the photosensitive film using the mask; And developing the photoresist to leave the photoresist only in an area corresponding to the pixel electrode and the data lower layer. 14. The method of claim 13, The photoresist film of the region corresponding to the data lower layer is made thicker than the photoresist of the region corresponding to the pixel electrode. And the photosensitive film in a region corresponding to the pixel electrode and the data lower layer is removed. 15. The method of claim 14, And the data lower layer is disposed under the data line, the source electrode, the drain electrode, and the storage capacitor line. 15. The method of claim 14, The portion exposed to the photosensitive film is a positive type that is removed during development, The mask may include a region where the blocking portion is to be formed of the data line, the source electrode, the drain electrode, and the storage capacitor line, the opening portion corresponds to a region between the pixel electrode and the data lower layer, and the slit portion may A thin film transistor substrate manufacturing method, characterized in that disposed to correspond to the region to be formed as a pixel electrode. 15. The method of claim 14, The data wiring layer is patterned into the data line, the source electrode, and other regions by removing portions exposed by the photosensitive film. And the other areas are patterned into the drain electrode and the storage capacitor line in the process of patterning the data wiring layer to expose the pixel electrode to the outside. 15. The method of claim 14, In applying the additional photoresist film, And the additional photoresist film is formed thicker on an upper surface of the pixel electrode and the data lower layer on the side of the pixel electrode and the data lower layer. The method of claim 10, The data wiring layer is a method of manufacturing a thin film transistor substrate, characterized in that patterned by wet etching. The method of claim 10, The method of manufacturing a thin film transistor substrate, characterized in that by removing the photosensitive film to a uniform thickness as a whole. The method of claim 10, And wherein said additional photoresist film is applied thinner than said photoresist film applied on said data wiring layer. The method of claim 10, In the step of uniformly ashing the photoresist and the additional photoresist. By ashing, the photoresist film remains only on an area to be formed of the data line, the source electrode, the drain electrode, and the storage capacitor line, and the additional photoresist film is formed on the data line, the source electrode, and other regions. Method for manufacturing a thin film transistor substrate, characterized in that formed to cover both sides.

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