JP2000349297A - Thin film transistor, panel and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen TFTs, pixels on a substrate, a reflecting plate or the other elements in the number of fabricating processes by a method wherein impurity ions are implanted into a semiconductor laser using a gate electrode of multilayered structure as a mask for the formation of an LDD region. SOLUTION: An a-Si layer is deposited on a glass substrate 10 and then crystallized into a polycrystalline silicon layer. The polycrystalline silicon layer is patterned, and an SiO2 layer 2 is formed on the glass substrate 10 so as to cover the patterned polycrystalline silicon layer. Furthermore, an aluminum layer is formed on the substrate 10 and patterned into a lower gate electrode 42. A channel region 170 is positioned under the gate electrode 42, a region out of lateral regions is covered with an upper gate electrode 43 excluding the region 170, an LDD region 152 is formed between a source region 150 and a channel region 170, and an LDD region 162 is formed between the drain region 160 and the channel region 170.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to an LDD type thin film transistor used for a pixel switching element of a liquid crystal display device and a driving circuit thereof, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a thin film transistor ("TFT", Thin Film Transistor) is provided for each pixel electrode.
Liquid crystal display devices, EL displays, and the like using an active matrix type display substrate provided with (or, abbreviated as or) have been actively studied because higher image quality can be obtained as compared with a simple matrix type display device. Further, it is noted that the electron mobility of a polysilicon (also referred to as “p-Si”) TFT is higher by one to two or more digits than that of an amorphous silicon (also referred to as “a-Si”) TFT. A so-called drive circuit built-in type liquid crystal display device in which a TFT as a pixel switching element and a drive circuit are formed on the same glass substrate has been proposed and studied.

[0003] In this case, the technical properties and performance of the TFT as a semiconductor element itself used in the driving circuit and the properties and performance of the TFT in terms of application to a liquid crystal display device and the like are some technical factors. There are issues.

[0004] First, although it is rather a problem from the former aspect, in terms of the performance of a semiconductor device, p-S
Since an iTFT has a larger OFF current than an a-Si TFT or a MOS type field effect transistor, in order to reduce the OFF current, a low concentration impurity region (hereinafter referred to as “LD”) is provided adjacent to at least one of a source region and a drain region of the TFT.
D ", an abbreviation for Lightly Doped Drain,
Japanese Patent Application Laid-Open No. 5-136417 discloses and proposes a thin film transistor having a structure provided with the above.

[0005] However, simply having a LDD structure T
With FT, it is possible to reduce the OFF current, but
In the ON state in which the channel below the gate electrode of the TFT is inverted, the ON current is reduced by inserting a low-concentration impurity region, which is a relatively high-resistance layer, in series with the channel region.

Therefore, various L values that suppress the decrease in the ON current are considered.
A TFT having a DD structure has been proposed. [SID96 D
IGEST pp25: Samsung electron (hereinafter, referred to as a first conventional example), Euro Display '9
6 pp555, ASIA Display '95 pp
335: Philips (hereinafter, referred to as a second conventional example)].

FIG. 1 shows a configuration of a first conventional example. In this figure, reference numeral 10 denotes a glass substrate. 150 is p-Si
Is a source region (n ⁺ layer) of a semiconductor layer composed of 16
0 is the drain region (n ⁺ layer). 170
Is also a channel region.

In FIG. 1, a sub-gate electrode 41 is provided so as to cover a gate electrode 4, and an LDD region (low-concentration impurity region: n)
^- it has a form a layer) 151 and 161 structures. With such a structure, at the time of OFF, the semiconductor layers 151 and 161 in the LDD region below the sub-gate electrode 41 are formed.
Becomes a high resistance layer in which carriers are depleted, so that the OFF current can be suppressed low.
In No. 1,161, electrons serving as carriers are accumulated to form a low-resistance region, so that the ON current does not decrease.

[0009] Actually, on the substrate, at a position corresponding to each pixel and a driving circuit around the pixel portion, the number of rows and columns are increased in the vertical and horizontal directions in accordance with the pixel standard and the like. TFT
Are formed. For this reason, the gate electrode, the source electrode, and the drain electrode have a multilayer wiring structure via an interlayer insulating film. However, since these are self-evident matters, the illustration of the operation is omitted, and the description of each of them in the description and drawings of the following embodiments is also minimized.

Next, FIG. 2 shows a second conventional example. In this figure, reference numeral 10 denotes a glass substrate. 150 is p-Si
The source region (n ⁺ layer) 160 of the semiconductor layer made of
Similarly, a drain region (n ⁺ layer) 170 is a channel region. This figure shows the so-called GOLD (gate-
drain oerlapped lightly-d
The gate electrode 4 is composed of LDDs on both sides of the channel region 170, that is, LDDs on the source side and the drain side.
The structure covers regions (n ⁻ layers) 152 and 162. Also in this structure, similarly to the first conventional example, at the time of OFF, the low concentration impurity regions 152 and 162 below the gate electrode 4 are formed.
Becomes a high resistance layer in which carriers are depleted, so that the OFF current can be suppressed low. On the other hand, at the time of ON, the low-concentration impurity regions 152 and 162 may be below the gate electrode,
Since electrons serving as carriers are accumulated and become a low resistance region,
No reduction in ON current occurs.

However, in order to suppress the decrease in the ON current in the process of realizing such a TFT structure, the LDD region formed in the polycrystalline silicon semiconductor layer region is formed by implanting a specific impurity by using an ion doping method. At this time, specific impurities (in contrast to “impurities” in other technical fields) are implanted into polycrystalline silicon to exert the function of a semiconductor element, ie, not “contaminants”. Substances other than impurities necessary at the time of "doping" and "implantation", such as hydrogen atoms, are simultaneously doped. In particular, when hydrogen is doped into the channel portion of polycrystalline silicon immediately below the gate electrode, hydrogen intervenes between the polycrystalline silicon atoms bonded to each other, and electrons are trapped, so that the threshold of the TFT is reduced. The value voltage is increased, and the reliability is significantly reduced.

Therefore, in the p-Si type TFT, a minute LDD region (Lightly Doped Drain) is provided adjacent to at least one of the source region and the drain region of the TFT in order to solve the problem of electrical characteristics.
It is essential to provide n). However, on the other hand, the following difficulties arise in forming these low-concentration impurity regions.

1) In order to realize high definition of a liquid crystal display device or the like, it is necessary to increase the display density by making the pixel transistor fine. However, in general, an exposure apparatus used for manufacturing a liquid crystal display device is of the same-size exposure type, and the miniaturization of pixel transistors naturally has a limit. Therefore, it is extremely difficult to form a low-concentration impurity region as a minute region which is equal to or less than the channel width (approximately 1 to several μm) of the pixel transistor (approximately 0.1 to 2, 3 μm).

2) Since the sub-gate electrode and the low-concentration impurity region are superimposed by mask alignment, the superposition is performed in a self-aligned manner (inevitably with high accuracy when viewed from the direction of impurity implantation). ) Cannot be formed, and the size of the low-concentration impurity region fluctuates due to deviation of mask alignment accuracy. In addition, a margin is required for mask alignment in order to control processes such as manufacturing in a short time, so that there is a limit to miniaturization of the pixel TFT. As a result, the area occupied by the pixel TFT is increased by the amount of securing the margin.

3) The area occupied by the pixel TFT increases,
Accordingly, the parasitic capacitance between the source region and the drain region increases, and as a result, the operation waveform is delayed, and the display characteristics of the liquid crystal display device deteriorate.

4) When forming a sub-gate electrode, a step of forming a metal film which is an electrode, a photolithography step, an etching step, and the like are required separately from the gate electrode, and a photomask for performing photolithography is required. Become. That is, the GOLD structure requires not only two ion implantations but also a complicated manufacturing process such as oblique rotation ion implantation. Accordingly, the TFT manufacturing process becomes diversified, and the cost of the liquid crystal display device becomes extremely high due to a prolonged process, an increase in manufacturing cost, and a decrease in suspension.

Next, the problem in terms of application to use in a liquid crystal display device is somewhat as follows, though there are some overlaps with the above problem.

In a TFT used in a liquid crystal display device, if the resistance of the gate line is high, the electric resistance of the gate line first becomes a problem as the screen becomes larger, such as 15 inches or 20 inches.

That is, the delay of the gate signal cannot be ignored and the response delay of the pixel becomes conspicuous. Also,
Flicker and uneven display on the screen also occur.

Second, TFT characteristics become a problem.

In the TFT characteristics, it is important to improve the mobility and the on-current, and to lower and stabilize the threshold voltage. In order to improve these characteristics, control of the interface is most important. In particular, the interface between the semiconductor layer and the gate insulating film has a significant effect. Therefore, if this interface is improved, the characteristics will be improved.

One of the means for improving the interface is a heat treatment. By performing this heat treatment, interface defects are reduced, charges accumulated in each layer are removed, and the interface is improved. Incidentally, the temperature of the heat treatment is preferably close to 800 to 900 ° C. at which silicon forming the semiconductor layer is recrystallized.

However, since a glass substrate is used for the display device from the viewpoint of economy, there is a limitation from this viewpoint. That is, the temperature can be raised only up to about 600 ° C. due to the heat resistance of the glass determined by heat shrinkage or the like.

Further, it is more inconvenient to use A as a means for reducing the resistance of the gate electrode in order to solve the first problem.
When low resistance metal such as l or Al alloy is used,
That is, hillocks, disconnections, short circuits, etc. may occur even at undesired temperatures. However, when high melting point metals such as W, Mo, and Ta are used, the above-mentioned disadvantages increase because these high melting point metals have high resistance.

Third, leakage current is a problem.

That is, in a thin film transistor,
When the leak current in the off region increases, the retention characteristics of the pixel deteriorate. For this reason, in order to obtain a high-definition and excellent pixel, it is extremely important to reduce the off-state leak current. By the way, in the conventional thin film transistor, an off-state leak current occurs due to the electric field intensity near the drain region. For this reason, when the gate voltage is increased toward the off side, the electric field intensity increases, and the off-leak current also increases. As a countermeasure, L
A DD (Lightly Doped Drain) structure and an offset structure are employed. However, it is difficult to form an appropriate LDD region just in terms of dimensions.

Fourth, portions having different roles such as a pixel portion and a drive circuit portion are formed on one substrate, but the TFT characteristics required for these portions are different. Well, in this case,
Although the shape of the element and the dimensions of the channel region, the drain region, and the source region can be determined by designing a mask by photolithography, it is difficult to form a fine LDD portion.

Fifth, pixels and TFs for pixels are formed on one substrate.
Forming portions having different roles, such as T, TFTs for driving circuits, and other reflectors, inevitably increases the number of steps. However, if these components are not formed as much as possible, costs may increase.

[0029]

As can be seen from the above description, a gate electrode material having low electric resistance and excellent heat resistance is used, and as a result, TFT characteristics are excellent, leakage current is small, and furthermore, an LDD structure is used. Despite having
Practical use of a semiconductor element that is easy to manufacture and does not increase the cost has been desired.

Further, there has been a demand for the development of a thin film transistor in which the LDD structure is formed finely and with high precision and which has a small parasitic capacitance and an extremely simple and easy manufacturing thereof.

There has been a demand for development of an LDD type TFT which satisfies such demands regardless of whether it is a top gate type or a bottom gate type.

Further, development of a substrate in which an LDD type TFT having characteristics required for the portion is formed in each portion on one substrate, and as a result, in the case of a liquid crystal display device, the response of the pixel is quick and the flicker etc. The development of a large-screen liquid crystal display device without the need has been desired.

Also, even if the LDD type is not used, the T-
In the FT, hydrogen used for dilution at the time of impurity implantation penetrates a channel region below the gate electrode,
Since the silicon crystal is damaged, which greatly impairs the characteristics of the p-Si TFT, a solution has been desired.

In addition, an LDD type TFT having different characteristics is formed in each part on one substrate, and at this time, a technology of forming a TFT and other elements such as a pixel and a reflection plate on the substrate can be reduced as much as possible. LDD type TF that meets development or its requirements
The development of T was desired.

[0035]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above-mentioned problems, and therefore, the material and structure of the gate electrode can be reduced from various aspects such as electric resistance and implantation of impurities. The device is elaborate.
In addition, the production and structure of the source and drain electrodes are also devised. In addition, the panel is also devised.

Specifically, the following idea is provided.

{First Invention Group} The present invention group has a weaker masking capability than the central portion when impurities are implanted into the ends on the source electrode side and the drain electrode side for improving the gate electrode and forming the LDD region. In addition, silicide is used to form minute portions having a short length in the channel direction.

In one aspect of the present invention, a semiconductor layer having a source region, a drain region, and a gate region formed on a substrate, a gate insulating film, a source electrode and a drain formed on the gate insulating film are provided. It has an electrode and a gate electrode. In addition, it also has other parts such as an interlayer insulating film necessary for exhibiting the function as a transistor (element). In a semiconductor device, the gate electrode is composed of a top and bottom made of a silicide thin film and a metal thin film. The upper layer is formed so as to completely cover the lower layer when viewed from the direction of the impurity ions to be implanted, and the semiconductor layer is formed by using the gate electrode of the multilayer structure as an implantation mask. It has an LDD region formed by implanting impurity ions.

With the above configuration, the following operation is performed.

One layer of the gate electrode of the semiconductor element is a silicide thin film (it may contain some other material such as raw material silicon for some reason such as unreacted) and the other layer is a metal thin film. The upper layer is composed of upper and lower layers, and the upper layer completely covers the lower layer (the gate insulating film side) when viewed from the direction in which the impurities fly (in principle, the upper surface of the substrate), and in many cases, 1 to 4 suitable for forming the LDD structure to at least one of the drain electrode side and the source electrode side
It is formed to protrude by about μm (determined on a case-by-case basis depending on conditions such as the size of the element).

The semiconductor layer is naturally exposed to the drain electrode side or by implanting impurity ions from above using the gate electrode having a trapezoidal structure or the like in which the upper layer protrudes or the entire cross section of the semiconductor layer widens. At least one of the L at the source electrode side has a smaller amount of implanted impurities than the channel region.
It has a DD region.

For this reason, the source region, the drain region, and the narrow LDD region are naturally formed in a region determined by the positions of the silicide thin film and the metal thin film in the semiconductor layer and the direction of impurity ion implantation.

It should be noted that the impurity may diffuse due to the subsequent heat treatment, and the boundary may be slightly unclear in some cases. Further, the direction of impurity ion implantation may be slightly oblique. However, they are also included in the present invention.

Then, an LDD region is formed downstream of the protruding portion of the second layer on the upper side with respect to the ion flight direction. In this case, the stray capacitance becomes smaller if it protrudes only in one direction.

In another invention, the upper and lower layers of a silicide thin film and a metal thin film are replaced with a silicon thin film and a metal thin film, regardless of whether they have the same thickness or not. And two upper and lower layers composed of a silicide thin film (including some unreacted layer portions).

With the above configuration, the same operation as that of the above-described invention is performed for forming the LDD region. (Note that polycrystalline silicon formed by laser annealing forms silicide in a short time, even at temperatures that glass substrates can withstand, unlike crystalline silicon, which is much larger in particle size, so to speak. )) In other inventions,
The gate electrode is composed of a multilayer having an amorphous silicon thin film that easily reacts with at least the silicide thin film and the metal thin film. Further, as a mask for impurity implantation, the center is the thickest, the ends are the thinnest, and the middle is the middle. Is a multi-stage LDD formation mask / gate electrode which has an intermediate thickness or gradually increases from both sides toward the center.

With the above configuration, a multi-stage LDD region is provided.

In another invention, the gate electrode is made of molybdenum, tungsten, tantalum, niobium, TZM, T
A layer made of a refractory metal (including alloy) thin film such as ZC;
An intermediate aluminum-containing gate electrode having a layer made of a silicide thin film and a layer made of an aluminum thin film surrounded by a refractory metal thin film layer and a silicide thin film layer, and the semiconductor layer is made of an intermediate aluminum-containing gate electrode. Is an LDD semiconductor device having a single-stage or multi-stage LDD region formed by implanting impurity ions from above using an as an implantation mask.

With the above configuration, the following operation is performed.

The gate electrode is a gate electrode containing an intermediate aluminum layer. Therefore, it is hardly reacted with aluminum at the heat treatment temperature of the substrate, and a silicide layer having the same properties as a layer made of a high melting point metal thin film that does not deform. It has a layer composed of a thin film and a layer composed of an aluminum thin film having a low electric resistance surrounded by the refractory metal thin film layer and the silicide thin film layer and protected from both layers during the heat treatment of the substrate. Low resistance and good heat resistance.

In another embodiment, the silicide layer is a specific material silicide layer selected from the group consisting of titanium silicide, cobalt silicide, nickel silicide, zirconium silicide, molybdenum silicide, palladium silicide, and platinum silicide.

With the above structure, the silicide layer is made of titanium silicide (TiSi ₂ , TiSi, TSi) having a low electric resistance.
i ₅ Si ₃ ), cobalt silicide (CoSi ₂ , Co
_{2 Si, CoSi, CoSi 3)} , nickel silicide _{(NI 2 Si, NiSi, NiSi} 2), zirconium silicide _{(ZrSi 2, ZrSi, Zr 2} Si), molybdenum silicide _{(MoSi 2, Mo 3 Si,} Mo 5
Si ₃ ), palladium silicide (Pd ₂ Si, PdS
i), platinum silicide (Pt ₂ Si, PtSi).

The molecular formula of each metal silicide is listed as an example.

In another invention, at least one metal thin film is a metal thin film of the same material whose constituent metal element is the same as the metal element forming silicide.

According to the above structure, if the silicide of the first layer is palladium silicide, the first layer is a palladium thin film.
Since the same metal element as that of the layer is used as the material, formation of the silicide layer and arrangement of the material are convenient.

In another invention, the above-mentioned LDD type TF
This is a manufacturing method of T.

{Second Invention Group} The present invention group is an LDD type T
In order to form a gate electrode whose thickness changes in a plurality of steps to serve as a mask at the time of impurity implantation for FT production, a gate electrode component material layer already formed on a gate insulating film is used as a base. Processing such as plating, oxidation, and anodic oxidation, and Photsonography and etching are used.

In the first invention of the present invention group, similarly to the first invention of the first invention group, the lower electrode is used because the gate electrode also serves as a mask at the time of impurity implantation and has an LDD structure. In this case, at least one side of the source electrode side or the drain electrode side protrudes slightly from one side of the upper electrode or the lower electrode and the other protrudes from the other side. The masking ability of the section is not perfect.

With the above configuration, the following operation is performed.

The semiconductor layer has a channel region immediately below the central portion of the gate electrode, an LDD region immediately below at least one protruding portion thereof, and a source region and a drain region respectively in the other regions. An area is formed.

In another invention, the upper gate electrode is formed by plating a thin metal film made of a material having a low density on the lower gate electrode made of a material having a high density already formed. (Of course, the density is not always the same depending on the thickness of the lower gate electrode or the thickness of the shielding and masking ability and the plating thickness and other materials.) With the above configuration, the following operation is performed.

Since the plating is performed, the upper gate electrode is formed to be very thin, to have a high thickness accuracy, and to be accurately positioned with respect to the lower gate electrode.

In another embodiment, the plating is electrolytic plating or electroless plating.

As a result, the range of material selection and the like can be expanded, which is convenient for waste disposal.

When the upper gate electrode is formed by plating, the protruding portions to the lower electrode side are formed on both the source electrode side and the drain electrode side unless some processing is performed in advance. Of course, the upper surface of the lower electrode is also plated.

In another invention, an LDD forming mask is formed by anodizing the upper gate electrode material.

In another invention, a lower gate electrode made of Mo, Fe, or the like is reacted with a predetermined object, for example, a gas such as oxygen, and an oxide is formed on the upper surface and side surfaces thereof by utilizing a chemical reaction. Is formed.

With the above configuration, the following operation is performed.

Also in this case, the temperature and the fluid pressure at the start of the reaction are controlled to form the upper gate electrode whose positioning, thickness and the like are accurate.

In this case, depending on the combination of the lower gate electrode material and the reactant, since the electric resistance is high, the lower gate electrode does not actually function as the upper gate electrode, but may simply have the function of a mask. At this time, after the impurity is implanted, the upper gate electrode as a reaction product is basically removed by etching or the like or plays a role of an insulating film.

In another aspect of the invention, a lower gate electrode having a firm mask function is formed first, lightly doped with impurities, and then, at least on one of the source electrode side and the drain electrode side above the lower gate electrode. The exposed upper gate electrode having a firm mask function is formed by plating or the like, and impurities are implanted under the upper portion in earnest.

With the above configuration, the following operation is performed.

As a result, although it is necessary to perform impurity implantation twice, the LDD is formed under the exposed upper gate electrode.
A TFT having a region is manufactured.

In another aspect of the invention, the protrusion of the end of the upper gate electrode on the side of the lower gate electrode is formed at least by using Photsonography and etching.

With the above configuration, the following operation is performed.

A gate electrode which also serves as a mask for forming an LDD structure with a small displacement between the lower gate electrode and the upper gate electrode is formed.

Incidentally, depending on the case, other means such as anodic oxidation may be employed in addition to these. Further, the resist may constitute a part of the mask.

In another invention, the protruding portion of the mask / gate electrode having the structure in which the upper and lower portions and the upper portion protrude from the lower portion is removed after impurity implantation.

With the above configuration, the following operation is performed.

An LDD-TFT having different characteristics can be formed on one substrate. In particular, by forming this LDD type TFT only in a partial region corresponding to the role of the element and the required performance on the same substrate, a substrate optimal for various uses can be obtained.

In addition to the above, in the first invention group and the second invention group, some inventions are used as upper and lower gate electrode materials.
Density is 8 or more, preferably 10 or more, more preferably 1
3 or more, specifically, metals and the like having high density of hydrogen such as Ta or W (especially, silicide) such as Ti and alloys mainly containing the same, and alloys or mixtures thereof (for example, , W and Ti), a material that makes it difficult for hydrogen to penetrate during the implantation of impurities and a material that has a low electric resistance are used.

{Third Invention Group} The present invention group includes, in addition to the first invention group and the second invention group, a gate in a region other than immediately below the mask / gate electrode prior to the impurity implantation. The insulating film is once removed, and the gate insulating film in the region is formed again after the impurity implantation.

With the above configuration, the following operation is performed.

Since the gate insulating film does not exist, the accelerating voltage at the time of impurity implantation can be reduced by that much, and hydrogen used for diluting impurities can be supplied at high speed regardless of the channel region, source region, drain region and LDD region. The damage of the polycrystalline semiconductor due to the implantation is reduced accordingly.

It is needless to say that heat treatment for limiting the damage of the polycrystalline semiconductor accompanying the removal of the gate insulating film and for recovery is performed as necessary.

{Fourth Invention Group} The present invention group, in addition to the third invention group, further prevents hydrogen for diluting impurities from entering the polycrystalline semiconductor as much as possible when implanting impurities. In addition, a film of Ti or Zi having excellent hydrogen absorbing ability is formed on the surface of the polycrystalline semiconductor from which the gate insulating film has been once removed.

With the above configuration, the following operations are performed.

The hydrogen absorbed by Ti or the like, or even the Ti or the like, physically and chemically adsorbs the hydrogen implanted in conjunction with the impurities, decelerates, and the hydrogen enters the polycrystalline semiconductor at a high speed. To prevent Incidentally, these metals are particularly Ti
Of course, does not hinder the implantation of impurities due to its low density.

Therefore, the performance of the LDD-TFT is further improved.

In another embodiment, Ti or the like as a hydrogen stopper at the time of impurity implantation is left in the source electrode and drain electrode formation portions, and is reacted with polycrystalline silicon by a subsequent heat treatment to form a silicide film.

With the above configuration, the following operation is performed.

The electrical contact between the source and drain electrodes and the polysilicon is greatly improved through the silicide layer.

Further, when a contact hole is formed for forming a source electrode and a drain electrode, a silicide film or a layer of unreacted Ti or the like remaining on the upper surface thereof serves as an etching stopper.

{Fifth invention group} The present invention group is the first invention group described above.
While the fourth invention group is of a top gate type,
The difference is that it is a bottom gate type, and the others are almost the same.

However, in order to form a mask at a position exactly corresponding to the gate electrode, there is also a specific configuration such as exposing the resin by irradiating light or X-rays from the substrate side.

{Sixth Invention Group} The present invention group is the first invention group described above.
To the fourth invention group are of the LDD type, whereas the non-LD
D type is different. An object of the present invention is to obtain a gate electrode having a low resistance while preventing intrusion of hydrogen into a lower portion of a channel region.

For this reason, in the first invention, the gate electrode is connected to 2
The layers are made of a material having a small electric resistance, and the multilayer is made of a high-density metal, a hydrogen-adsorbing metal, or the like.

In another invention, the gate insulating film is temporarily removed at the time of impurity implantation.

In another invention, a Ti film is formed after the gate insulating film is once removed to prevent hydrogen from entering.
Note that this film is removed in principle after the impurity is implanted.

{Seventh Invention Group} The present invention group relates to a substrate using the above-described invention group, particularly to LDD type TFTs.

According to the first aspect of the invention, an LDD type TFT having characteristics according to the role of the part is formed on each part of one substrate.

In other inventions, various parts, films, and layers are formed on each part of a single substrate according to the role of the parts. The formation of these parts and the formation of the LDD TFTs of the above-described invention groups are performed. Is as common as possible.

[Detailed Description of the Invention] The present invention will be described below based on its embodiments.

<< First Invention Group >> (1-1st Embodiment, Structural Aspect) (Note that the 1-1st embodiment is particularly the first embodiment of the first invention group.) For this reason, there is a case where a configuration of another invention group is included.) In this embodiment, silicide is used.

FIG. 3 is a sectional view of a TFT as a first embodiment of the first invention group.

As shown in this figure, in this TFT, a semiconductor layer 1 is formed on an insulating substrate 10, a gate electrode 4 is formed on a gate insulating film 2, and the TFT is formed on the semiconductor layer using the gate electrode as an implantation mask. By implanting impurity ions, a source region 150 and a drain region 160 are formed in the semiconductor layer in the lower left and right portions in the figure.

Further, an interlayer insulating film 3 is formed, and a source electrode 5 and a drain electrode 6 are formed using a connection portion in a contact hole formed in the interlayer insulating film above the source region and the drain region. I have. For this reason, the basic configuration is the same as the conventional one shown in FIG.

However, the gate electrode is formed of the lower silicon layer 413 including the silicide layer formed on the gate insulating film.
And a metal layer 414 formed so as to cover the layer from above
It has a multi-layered (substantially two-layered) structure. Further, the structure of the end portion 4141 on the source electrode and drain electrode side is devised, and the semiconductor layer in the lower channel region in the drawing has an LDD structure. Are different. Hereinafter, these differences will be mainly described.

First, the silicide of the gate electrode portion silicon layer is formed using titanium silicide, cobalt silicide, nickel silicide, zirconium silicide, palladium silicide, platinum silicide, or the like.
By using these silicide layers, the resistance of the gate electrode can be reduced.

For example, when titanium silicide is used, the sheet resistance of the electrode is 13 μΩ / □, that of cobalt silicide is 20 μΩ / □, and that of nickel silicide is 40 μΩ / □.
μΩ / □, 35 μΩ / □ for zirconium silicide, 35 μΩ / □ for palladium silicide, and 30 μΩ / □ for platinum silicide can reduce the resistance as compared with the case of using a conventional high melting point metal.

Next, a metal layer 414 is formed so as to completely cover this silicon layer. Further, on the gate insulating film 2, the metal layer 414 is several μm on one side to the source electrode side and the drain electrode side than the silicide layer. Extrusion structure 4141
It has become.

The metal layer is preferably made of aluminum or an alloy thereof from the viewpoint of low electrical resistance, and is preferably a high melting point metal such as tungsten or molybdenum from the viewpoint of heat resistance during heat treatment. However, it is not necessarily limited to these metals. Basically, any metal can be used as long as it properly functions as a gate electrode also serving as a mask and satisfies other requirements such as height. Good.

The thickness varies depending on the kind of metal, particularly the density and the atomic weight which affect the shielding effect at the time of impurity ion implantation, but is about several hundreds to several thousand degrees. For example, when Ti (titanium) is used, its thickness varies depending on the acceleration voltage and the type of ion to be implanted.
About 0 ° is appropriate.

The gate electrode having such a structure can be used as an implantation mask (shield) to implant impurity ions such as P and B from above.

Therefore, the semiconductor layer below the electrode naturally forms the LD.
The D structure is also different from the conventional one. Hereinafter, this will be described in some detail.

The conditions for the ion implantation in this case are as follows: the acceleration voltage is 50 to 70 KeV, and the implantation amount is 1.0E15.
(10 to the 15th power) to 8.0E15 / cm ² is appropriate. At this time, the thickness of the gate insulating film 2 is 800 to 1200.
About Å.

As a result of this implantation, for example, in the case of an n-channel transistor, P ions are implanted. Then, P ions are sufficiently implanted into a region where there is no gate electrode in the direction in which the impurity ions fly (in principle, upward) to form an n + layer, thereby forming a source region 150 and a drain region 160.

On the other hand, in the portion where the silicide layer and the metal layer are stacked, these layers serve as a P ion shielding film, so that no P ions are implanted at all. Therefore, this region becomes the original channel region 170.

In the region immediately below the portion 4141 in which only the metal layer is formed by protruding the silicon layer on the gate insulating film 2, the thickness of the metal layer completely blocks the implanted ions. Therefore, impurity ions are slightly implanted. For example, using the above-mentioned Ti film as a metal layer,
When implantation is performed under the above-described ion implantation conditions, 1.0E14 to
Ions of about 5.0E14 / cm ² are implanted.

As a result of the above, this portion becomes the n ⁻ layer 151, 1
52 will be formed. As a result, it is possible to easily form a high-precision LDD structure as a whole with a single implantation.

As a modification of the present embodiment, the silicide thin film may be formed again so as to slightly protrude in the channel direction of the lower silicide thin film in place of the upper metal thin film. It is.

(1-1st Embodiment, Manufacturing Method) Next, referring to FIGS. 4 and 5, the LDD having the structure shown in FIG. 3 will be described.
The method for manufacturing the type TFT will be described.

First, a description will be given with reference to FIG. FIG.
FIG. 5 and FIG. 5 should be originally one drawing (drawing number), but have two leaves (drawing) for convenience of writing space on paper.

(A) A SiO ₂ film is formed as a base (undercoat) film 12 on a non-alkali glass substrate 10.

(B) Amorphous silicon (a-Si) 100 is formed on the entire surface of the SiO ₂ film, and this amorphous silicon is annealed (melted and recrystallized) by irradiation with excimer laser to form polycrystalline (poly) silicon (mono). (Silicon composed of one or more large particles). Thereafter, the polysilicon film 100 is left only in a region for forming a transistor (element) determined by the arrangement of the pixel portion on the substrate and the peripheral drive circuit portion, and the other portions are removed. That is, so-called isolation and patterning are performed. For the above-described reason, FIGS. 4 and 5 show the isolated polysilicon film, and furthermore, each part of one semiconductor element and the like.

(C) A gate insulating film 2 is formed on the entire surface.
In this case, the thickness of the gate insulating film depends on the film quality and the size of the transistor.
800 to 120 formed by OS plasma CVD
SiO ₂ of about 0 ° was used.

(D) A silicide film for forming a gate electrode is formed on the entire surface of each patterned gate insulating film, and the formed silicide film is left only at a position corresponding to the gate electrode 413, and the other portions of the silicide film are Remove. In this embodiment, the titanium silicide film is used.
Of course, other silicides may be used. In addition, a sputtering method was used as a forming method.

(E) In order to form a gate electrode having the shape shown in FIG. 4, a metal film 414 is formed on the entire surface of the patterned silicide film, and the ends on the source electrode side and the drain electrode side are formed of the silicide film. It protrudes about 1-4 μm. That is, patterning is performed.

As a result, the lower silicide layer is completely covered with the upper metal layer. In this case, a Ti film was used as the metal film. And the thickness is about 500 ~
It was about 1000 °.

Next, the description moves to FIG.

(F) In this state, P ions are implanted from the upper surface of the substrate to form an n-channel thin film transistor. The injection conditions are an acceleration voltage of 60 to 70 KeV and an injection amount of 1.0E15 to 5.0E15 / cm ² . At this time, the above-mentioned amount of p is implanted into the polycrystalline silicon in the region where the gate electrode of the two-layer structure is not formed to form an n ⁺ layer, and the source region 150 and the drain region 160 are formed.

On the other hand, in the region where only the metal layer is formed on the gate insulating film under the gate electrode, that is, at the end 4141 on the drain electrode side and the source electrode side of the metal layer, some of the implanted P ions are Shielded at the edge of the metal layer, the remainder is implanted into the underlying polysilicon layer.
Thus, n ⁻ layers 152 and 162 are formed in this region. As a result, a naturally high-precision LDD structure is easily formed by one ion implantation.

(G) Next, an interlayer insulating film 3 is formed on the entire surface of the substrate. This film uses, for example, an SiO ₂ film formed by APCVD or TEOS plasma CVD, and has a thickness of about 6,000 to 6,000.
It was about 9000 °.

(H) Finally, a contact hole is formed in a portion corresponding to the source region and the drain region, a metal film is formed and a metal is buried, and unnecessary portions are removed to remove the source electrode 5 and the drain. The electrode 6 was further formed with necessary connection wiring (not shown) and the like. Thus, a thin film transistor was completed.

(Embodiment 1-2) Next, a second embodiment (manufacturing method) of the present invention will be described with reference to FIG.

The thin film transistor of this embodiment is the same as that of the first embodiment up to the first embodiment of forming the gate insulating film (FIG. 4C). This is different from the formation of the gate electrode. Therefore, this part will be described with reference to FIG.

(A) First, for use in forming a gate electrode, an amorphous silicon layer is formed on the entire surface of the substrate 10 and unnecessary portions are removed, so that the center is aligned with the original position of the gate electrode. Is formed in a patterned amorphous silicon layer 4130.

(B) A metal film 414 is formed on the entire surface of the substrate on which the amorphous silicon layer is formed, and then about 1 to 1 m from the upper surface of the patterned amorphous silicon layer and the ends of the layer on the source electrode side and the drain electrode side. The remaining portion is removed while leaving only the portion 4141 that protrudes by about 4 μm (otherwise, strictly, a portion necessary for electrical connection of the semiconductor element outside the upper portion of the patterned polysilicon). That is, so-called patterning is performed.

As a result, the amorphous silicon layer 4130
A structure in which the metal layer 414 is completely stacked thereon is obtained. In this case, for example, the amorphous silicon layer
It is formed by a VD method or a sputtering method, and has a thickness of about 500 to 20
00 °. A Ti film is used as the metal film. And, the thickness is about 2000-5000 °.

(C) In this state, a heat treatment for forming a silicide film 415 in the middle by reacting the amorphous silicon layer with the metal film Ti is performed. This heat treatment is performed at 550 to 650 ° C. for about 30 minutes.

It is needless to say that another metal may be used for the formation of the metal silicide.

Although the unreacted portion of the metal exists in the figure, it is needless to say that all of the metal may be reacted.

Further, the amorphous silicon and the metal may all react while maintaining the shape in which the upper layer protrudes about 1 to 4 μm from the end portions of the lower layer on the source electrode side and the drain electrode side. Of course.

Thereafter, the process of forming the transistor element continues, and thereafter, the same processing as that of the first embodiment (shown in FIG. 5F and thereafter) is performed.

As described above, a thin film transistor having a high-precision LDD structure was formed as in the first embodiment.

(Embodiment 1-3) FIG. 7 shows a third embodiment of the present invention.

This embodiment is a modification of the first embodiment shown in FIG. 3, in which the LDD structure 162 is provided only on the drain electrode side to reduce stray capacitance.

(Embodiment 1-4) FIG. 8 shows a fourth embodiment of the present invention.

This embodiment is a development of the 1-2 embodiment described with reference to FIG.

In this embodiment, as shown in FIG. 8C, a metal film, a silicide film, and an amorphous silicon film are formed on the gate insulating film in this order from the bottom.
A layer is formed, and an impurity is implanted from above to form an LDD having a two-stage structure.

Hereinafter, a method of manufacturing the semiconductor device will be described with reference to this drawing.

(A) A patterned metal thin film 416 is formed on the gate insulating film 2 of the substrate 10.

(B) The amorphous silicon film 4130 is formed by patterning so as to completely cover the metal thin film. In this case, the amorphous silicon film is formed so as to slightly protrude toward the source electrode side and the drain electrode side of the metal thin film. Therefore, up to this point, it is the same as the 1-2 embodiment except that the materials of the upper and lower film layers are reversed.

(C) The metal thin film and the amorphous silicon are reacted by heating to form a silicide layer 415 in the middle of both layers as in the case of the 1-2 embodiment. By the way, at this time, the heating temperature and time are adjusted so that the metal thin film remains in the channel region direction by a predetermined length and, of course, a constant thickness.

Also, at least a portion of the amorphous silicon that has protruded is also set to an unreacted state.

As a result, the gate electrode above the channel region has a thin portion 41301 made of only amorphous silicon at both ends of the gate electrode, an unreacted metal thin film 416 in the upper and lower layers at the center of the gate electrode, and a silicide layer 41 above it.
5 or further in between the thick portion made of the unreacted amorphous silicon layer 4130 of the upper layer and the intermediate portion made of the silicide layer or the unreacted amorphous silicon layer of the upper layer in addition thereto Is formed.

In general, the density of silicide is an intermediate value (however, not necessarily the center value) between the densities of the metal and silicon constituting the silicide. For this reason, in this intermediate portion, even if the thickness itself is equal to the thick portion at the center of the channel region (of course, sometimes the thickness is not equal), the ability as a mask (interruption) at the time of impurity ion implantation is inferior. .

Therefore, if impurities are implanted from above the substrate in this state, an LDD having a two-stage structure is naturally formed as shown by 161 and 162 in FIG.

Now, when forming a film thickness on a flat plate (substrate), its thickness and plane dimensions can be easily controlled. In addition, the rate of the chemical reaction between the metal and silicon is also easy because only the temperature and the time need to be considered. As a result, it is possible to extremely easily perform a process that originally requires extremely fine dimensional control, such as an LDD having a two-stage structure of a small number of small semiconductor elements arranged on a substrate.

(Embodiment 1-5) This embodiment is also a development of the embodiment 1-2 shown in FIG.

In this embodiment, as shown in FIG. 9C, the gate electrode has a three-layer structure, and the gate electrode is used as a mask to inject impurities to form a two-stage LDD.
It is assumed that.

Hereinafter, the present embodiment will be described with reference to FIG.

(A) A patterned silicide layer 413 is formed on the gate insulating film 2 of the substrate 10.

(B) completely cover the silicide layer 413 in a shape slightly protruding toward the source electrode and the drain electrode.
Then, a patterned aluminum thin film layer 417 is formed.

(C) The aluminum thin film layer 417 is completely covered, and a tungsten or molybdenum thin film 414 is formed in a shape slightly protruding toward the source electrode and the drain electrode.

Based on the above, impurities are implanted from above. For this reason, as shown in FIG.
1,162 LDDs are formed.

Next, heat treatment of p-Si is performed. The aluminum film 417 at the center is formed of a film 414 of a high melting point metal such as tungsten at the upper part thereof and a silicide 413 of a high temperature stable compound at the lower part thereof. Is deformed even if the temperature rises to a temperature close to its melting point.
No inconvenience such as generation of hillocks occurs. Even if it occurs, the conductive layers are present above and below the portion, and the length of the inconvenience portion itself is short, so that this portion has less adverse effect on the overall electric resistance.

Therefore, since the semiconductor element is made of aluminum having a low electric resistance as well as silicide, the electric resistance of the gate electrode is greatly reduced.

(Embodiment 1-6) This embodiment is a further development of the above-described Embodiment 1-4.

As shown in FIG. 10A, in the present embodiment, a lower metal film 416 and an amorphous silicon film 413 patterned on the gate insulating film in this order from below.
0, an upper metal film 414 is formed, and at this time, the upper film is formed so as to not only completely cover the lower film but also slightly protrude in the direction of the source electrode and the drain electrode. Under this condition, each substrate is exposed to a temperature of 550 ° C. to 660 ° C. for 10 to 20 minutes. As a result, the gate electrode becomes unreacted first metal layer 4160, first metal silicide layer, unreacted amorphous silicon layer 4130, and second metal silicide layer from below, as shown in FIG. And five unreacted second metal layers 4140. Eventually, when impurities are implanted using this gate electrode as a mask, the change in geometrical thickness and density results in L
The impurity concentration of the DD structure is multi-stage 156 so to speak, and excellent performance is exhibited.

{Second Invention Group} (2-1st Embodiment) In the present embodiment, the mask 2
Plating or the like is used as a gate electrode having a stepped structure.

FIG. 11 shows a cross section of the thin film transistor of this embodiment. In this figure, reference numeral 10 denotes a glass substrate. 150, 152, 170, 162, 160 are LD
It is a polycrystalline silicon layer having a D structure. 2 is a gate insulating film. 42 is a lower gate electrode. 43
Is an upper gate electrode. 3 is an interlayer insulating film. 5 is a source electrode. 6 is a drain electrode.

On a glass substrate 10 serving as a TFT substrate, a polycrystalline silicon layer 1 having a thickness of 500 to 1000 ° is formed.
Is formed, and a few hundreds to 1000 ° of S is formed thereon.
A gate insulating film 2 made of iO ₂ (silicon dioxide) is formed, and a two-stage gate electrodes 42 and 43 made of a metal material such as aluminum and an interlayer insulating film 3 made of SiO ₂ are sequentially laminated. Have been.

The gate electrode comprises a lower gate electrode 42 and an upper gate electrode 43 formed so as to cover the upper surface of the gate electrode. Further, the upper gate electrode 43 has its source electrode side and drain electrode side ends slightly protruding from the lower gate electrode 42.

Next, regarding the material of the two-stage gate electrode, the material of the upper gate electrode 42 having a higher density than the lower gate electrode 43 is the height of the gate electrode. Problems such as an increase in the required thickness of the film may occur.) And a mask effect. Specifically, for example, the lower gate electrode 42 is made of Al, Al / T
i, Al / Zr / Ti, etc., and the upper gate electrode 43
Is Ta, Cr, Mo or the like.

By implanting impurities using this gate electrode as a mask, the polycrystalline silicon layer has a channel region 170 located immediately below the lower gate electrode 42 and a source electrode side and a drain electrode side thereof, as shown in FIG. LDD regions 152 and 162 having a low impurity concentration immediately below portions 435 and 436 where the upper gate electrode protrudes from the lower gate electrode, and furthermore, there is no gate electrode on the source and drain electrode sides and on the upper side. Regions 150 and 160 having high impurity concentrations are formed.

Furthermore, the junction surface between the LDD region on the source electrode side and the source region 150 substantially coincides with the end surface of the upper gate electrode 43, and the junction surface between the LDD region 152 and the channel region 170 is the lower surface. It almost coincides with the end face of the gate electrode 42. Also, the LDD region 1 on the drain electrode side
The junction surface between the drain region 160 and the drain region 160 substantially coincides with the end surface of the upper gate electrode 43, and the junction surface between the LDD region 162 and the channel region 170 is
2 almost coincides with the end face. (Note: Actually, some mismatch may occur due to scattering by the gate insulating film at the time of impurity implantation and diffusion at the time of heat treatment.) In addition to the above, for example, the upper portion of the TFT is made of aluminum, and the lower portion is made of titanium. Source electrodes 51 and 52 and drain electrodes 61 and 62 are provided. The source electrode 5 is connected to a semiconductor source region 150 via a contact hole 95 formed in the gate insulating layer 2 and the interlayer insulating layer 3, and the drain electrode 6 is also connected to the drain via a contact hole 96. It is connected to the area 160.

Next, a method of manufacturing the TFT will be described with reference to FIGS. Although both figures should be originally one figure, they are two figures for reasons of space.

First, description will be made with reference to FIG.

(A) Plasma CVD on glass substrate 10
The a-Si layer 1 having a thickness of 500 to 1000 ° is deposited by the CVD method or the low pressure CVD method, and ablation occurs in the a-Si film 100 due to release of internal hydrogen during polycrystallization by laser irradiation. To prevent
A dehydrogenation treatment is performed at 400 ° C.

(B) The a-Si layer 1 is once melted by laser annealing using an excimer laser having a wavelength of 308 nm, and is crystallized (p-Si) as it is to form the polycrystalline silicon layer 1.

(C) The polycrystalline silicon layer is formed into a shape according to the arrangement of the semiconductor elements on the substrate by so-called photolithography. This is so-called isolation and patterning.

(D) Thickness of 100 on a glass substrate so as to completely cover patterned polysilicon 1
A 0 ° SiO ₂ (silicon dioxide) layer 2 is formed. In addition,
This layer becomes the gate insulating layer of the semiconductor element.

(E) An aluminum layer 420 is formed on the entire surface of the substrate.
To form a film. This layer becomes a gate electrode below the semiconductor element.

(F) The lower layer gate electrode 42 is formed by patterning the aluminum layer 420 into a predetermined shape by photolithography.

(G) Using this gate electrode 42 as a mask, first impurity ions diluted with H ₂ gas are accelerated and implanted with a voltage from above, that is, so-called doping is performed. At this time, phosphorus is used as an impurity, and the implantation concentration is set to a low concentration. As a result, the channel region 170 located immediately below the lower gate electrode 42 becomes a region in which impurities are not doped at all, and the left and right regions 175 and 176 excluding that region become n ⁻ layers lightly doped with impurities.

(H) A Mo layer 430 is formed so as to completely cover the lower gate electrode 42. This layer becomes the upper gate electrode of the semiconductor element.

At this time, as described above, the material used for the upper gate electrode has a higher density than the material used for the lower gate electrode. This takes into account the need for complete masking capability during the second doping.

Next, description will be made with reference to FIG.

(I) The upper metal layer is patterned to form the upper gate electrode 43.

(J) A second impurity implantation is performed mainly using the upper gate electrode 43 as a mask. On this occasion,
Phosphorus ions were used as impurities. The doping amount in this case is, of course, much larger than in the first time.

As a result, ions are heavily doped into a region of the polycrystalline silicon layer except for a region located immediately below the upper gate electrode 43. As a result, the region 175 in which the impurity is lightly doped by the previous doping,
Of the 176, the portion not covered by the upper gate electrode 43 is further doped with impurities, and becomes a high impurity concentration region (n ⁺ layer), that is, a source region 150 and a drain region 160.

On the other hand, among the regions 175 and 176, the region covered with the upper gate electrode 43 is not doped with impurities by the second ion doping, but is implanted at a low concentration. As a result, an LDD region (n ⁻ layer) results.

Thus, between the source region 150 (n ⁺ layer) and the channel region 170, the LDD region 152 (n
^- forming a layer) The drain region 160 (n ⁺ layer)
An LDD region (n ⁻ layer) is formed between the semiconductor device and the channel region 170. Moreover, at this time, the first ion doping is performed using the lower gate electrode 42 as a mask.
Since the second ion doping is performed using the second gate electrode 43 formed thereon as a mask, the source region, the drain region, and the two low-concentration impurity regions are self-aligned (necessarily to improve the positional accuracy). Good) can be formed. Moreover, the overlapping portion between the upper gate electrode 43 and the source region 150 and the overlapping portion between the upper gate electrode 43 and the drain region 160 can be reduced. As a result, the parasitic capacitance is reduced, the OFF current is reduced, and the decrease in the ON current is suppressed as much as possible.

(K) An interlayer insulating layer (SiOx) 3 is formed.

(L) Contact holes 95 and 96 are formed in the interlayer insulating layer 3 and the gate insulating layer 2 at positions where the source electrode and the drain electrode are to be formed.

(E) A metal layer of Al or the like is formed by a sputtering method, and an upper portion of the formed metal layer is patterned into a predetermined shape to form a source electrode 5 and a drain electrode 6. Further, a protective film (not shown) such as SiN is finally formed to manufacture a TFT.

Although the above is the case of the n-channel TFT, it is needless to say that the p-channel TFT can be manufactured by the same process.

(2-2nd Embodiment) Hereinafter, a second embodiment of the present invention will be described. In this embodiment mode, a lower gate electrode is plated to form an upper gate electrode.

FIG. 14 shows a method for manufacturing a thin film transistor according to the present embodiment. Hereinafter, this manufacturing method will be described with reference to FIG.

The procedures and processing from (a) to (e) are shown in FIG.
This is the same as (a) to (g) of No. 2. Therefore, description of specific contents is omitted.

(H) The entire glass substrate is immersed in an Au plating solution (not shown), and an electric field is applied so that the lower gate electrode 42 becomes a negative electrode.
The u layer 43 is formed by plating. Accordingly, the Au film 43 is formed on the side surface of the lower gate electrode 42 according to the plating conditions. At this time, a gate electrode wire (not shown) is used as an electric wire to which a voltage is applied for plating.

Incidentally, the Au film thickness can be formed to an accurate thickness by controlling the applied voltage and current, the plating time, the concentration of the plating solution, and the like. Moreover, it is easy to control the voltage, current, plating time, plating solution concentration, and the like. For this reason, the Au film thickness is extremely accurate in both the formation position and the thickness. The state of this plating (h ')
Shown in

(J) A second impurity implantation is performed using the lower gate electrode 42 and the Au film plated on the gate electrode as a mask. At this time, the impurity to be doped is phosphorus ions, and the doping concentration is the first concentration.
Higher concentration than the second time. Thus, as in the previous embodiment, the polycrystalline silicon layer includes the channel region 170 immediately below the lower gate electrode 42 and the impurity-doped region 1 immediately below the Au film plated on the side surface of the lower gate electrode.
A source region 150 and a drain region 160 doped with a high concentration of impurities are formed in regions 52 and 162 and regions other than those two regions.

Thereafter, the processing of (k) to (m) in FIG. 13 is performed.

In this embodiment, the plating material for the upper gate electrode is not limited to Au plating. In other words, it is only necessary that the electroplating can be performed with high accuracy and that it has an ion shielding effect against impurity doping. Further, the plating is not limited to the electroplating method at all, and it goes without saying that the electroless plating method may be used by selecting a plating solution and a plating material.

(Embodiment 2-3) This embodiment is directed to the GOLD (gate-dr) of the second embodiment.
ainoerlapped lightly-dope
The metal film plated on the lower gate electrode of the thin film transistor having the d drain structure is removed.

Hereinafter, the LDD (Light) of the present embodiment will be described.
A method of manufacturing a thin film transistor having a (ly Doped Drain) structure will be described with reference to FIG.

(J) of this figure is the same as (j) of FIG. However, the lower gate electrode is made of Au and the upper part is made of W.

(J ′) After the implantation of impurities, the W43 plated on the upper and side surfaces of the lower gate electrode 42 is removed.

Thereafter, the steps shown in FIGS. 13 (k) to 13 (m) are separated, and the LDD (Lightly Doped) is removed.
(Drain) is manufactured.

In this thin film transistor, only the remaining lower electrode 42 serves as a gate electrode, and the polycrystalline silicon layer immediately below the lower electrode 42 is only the channel region 170, and the low concentration impurity region (n ⁻ layer) 151 A source region 150 and a drain region 160 are formed on both sides thereof.

(Embodiment 2-4) The present embodiment relates to a pixel electrode using the thin film transistor of the above three embodiments.

FIG. 16 shows a pixel of the liquid crystal display device of the present embodiment. (A) of this figure is a plan view, and (b) is an AA cross section of (a). In both figures, reference numeral 10 denotes a glass substrate. 2 is a gate insulating film. 421 is a first lower gate electrode. 422 is a second lower gate electrode. 3 is an interlayer insulating film. 5 is a source electrode. 6 is a drain electrode. 11 is a pixel electrode.

The lower gate electrode is formed over a plurality of regions on the polycrystalline silicon layer.
21 and 422 are all covered with the upper gate electrode 43.

With this gate electrode structure, the polycrystalline silicon layer includes two channel regions 170 located immediately below two lower gate electrodes 421 and 422 in the figure and a source region 150 (n ⁺ layer) having a high impurity concentration. And a drain region (n ⁺ layer) 160, and a region with a low impurity concentration (LDD region: n <b> 4) immediately below the side portion of the two lower gate electrodes and the portion 435 where the upper gate electrode 43 protrudes. ^- layer) 152,162,1562 is formed.

With the above structure, the parasitic capacitance of the pixel TFT 11 is kept small, the OFF current is reduced, and the ON
The reduction of the current is suppressed as much as possible.

FIG. 17 shows a pixel TFT having another structure.

[0219] Also in this figure, (a) is a plan view of a pixel TFT, and (b) is a cross-sectional view taken along the line AA.

In this pixel TFT, the upper gate electrode 4
Reference numerals 31 and 432 are formed so as to individually cover the upper surfaces of the two lower gate electrodes 42 crossing a plurality of regions of the polycrystalline silicon layer.

With such a structure, the parasitic capacitance of the pixel TFT can be similarly reduced, the OFF current can be reduced, and the decrease in ON current can be suppressed as much as possible.

(Embodiment 2-5) In this embodiment, the length of the lower gate electrode in the channel direction is larger than that of the upper gate electrode.

FIG. 18 schematically shows a plane (a) and a cross section (b) of the thin film transistor of this embodiment. (B) is a cross section taken along line AA of (a).

The basic structure of this TFT is the same as that of the TFT of the above-described embodiment 2-1 shown in FIG. 13 and the like. However, the gate electrode 4 is different in that the length of the lower electrode 42 in the channel direction is longer than that of the upper electrode. Therefore, the lower gate electrode 42 has protrusions 425 and 426 on both ends of the upper gate electrode 41 on the source electrode 5 side and the drain electrode 6 side. Since the gate electrode is used as a mask and impurities are implanted from the upper surface of the substrate, a p-
An Si film is formed.

In this drawing, reference numeral 170 denotes a channel region which is located below the upper and lower electrodes and has no impurities implanted therein. 152 and 162 are LDD regions into which impurities are implanted a little because only the protruding portions 425 and 426 of the lower gate electrode serve as a mask. 150 and 160
Are a source region and a drain region where many impurities are implanted because there is no mask.

Hereinafter, a method of manufacturing the thin film transistor will be described with reference to FIG.

(A) On the glass substrate 10, an undercoat SiO ₂ film 12 for preventing a substance in the glass substrate from diffusing into the semiconductor layer during annealing of a-Si or the like.
Was deposited to a thickness of about 4000 °. On top of this, a film thickness of 500
An amorphous silicon film 1 was deposited.

Next, the a-Si film was melted and recrystallized (polycrystallized) by laser annealing using an excimer laser having a wavelength of 308 nm to obtain a polysilicon film.

Then, to form a TFT, the p-Si
A predetermined region of the film was processed into an island shape. This is so-called patterning.

A gate insulating film 2 was formed so as to cover the patterned p-Si film over the entire surface of the substrate. Specifically, T
By plasma CVD using EOS as a source gas, S
An iO2 film having a thickness of about 1000 DEG was used. Therefore, the operation up to this point is the same as that of the previous embodiment.

(B) An upper gate electrode film 420 was deposited on the SiO ₂ film. In this embodiment, an ITO film formed by a sputtering method is used, and the film thickness is set to about 500 mm. A film or a conductive oxide film such as ITO may be used. However, in these cases, the doping of the LDD region is performed in a later step using the lower electrode as a mask, so that the optimum film thickness is determined individually in consideration of this. In addition, since the stopping power of ions doped by the film material (the ability to prevent the passage of accelerated ions) is different, the optimum film thickness naturally depends on the material composition of the film.

(C) On the lower gate electrode film 420,
As the upper electrode film 410, a tantalum film having a thickness of 2000 ° was formed by a sputtering method.

The material of the upper electrode film must be selected in consideration of the fact that the lower electrode film can be selectively etched in a later step.

(D) Tantalum film 410 of upper gate electrode
Is patterned into a predetermined shape, and the upper gate electrode 41 is patterned.
Was formed. The patterning is performed using a photosensitive resin, and the resist 13 is formed only on the portion where the tantalum film is left.
And unnecessary portions of the tantalum film were removed by dry etching.

(E) In order to form the lower gate electrode 42, the ITO film was patterned into a predetermined shape to form the lower gate electrode 42.

(F) Using the gate electrode 4 having the upper and lower steps as a mask, phosphorus ions were doped as an impurity from above. Thereby, the LD having the structure as shown in FIG.
DTFT was obtained.

Since the subsequent steps are the same as those of the embodiment 2-1 and the like, the description thereof is omitted.

In the above-described example, the n-channel TFT is used. However, a p-channel TFT can be manufactured in the same manner.

FIG. 20 shows the voltage / current characteristics of the TFT manufactured by the above method. In this figure, line L1 shows the characteristics of the TFT having the conventional structure (not the LDD structure), and line L2 shows the characteristics of the conventional LDD structure. Line L3
Shows the voltage / current characteristics of the TFT manufactured in this embodiment. As is clear from the lines L1 and L2, in the TFT having the conventional structure, the off current can be reduced by using the LDD structure. However, LD
With the D structure, the on-current is reduced.
On the other hand, in this embodiment, it can be seen that the off-state current can be reduced and the on-state current is not reduced. That is, in the TFT of the present embodiment, since the LDD region having high resistance is located below the gate electrode,
In the saturated region and the unsaturated region, electrons serving as carriers are accumulated in both the LDD region and the channel region.
ON current does not decrease.

(Twenty-sixth Embodiment) (Configuration of TFT Array) FIG. 21 shows a TF of this embodiment.
A cross section of a pixel electrode area using a T array as a pixel switching TFT of a liquid crystal display device is schematically shown. In fact, these are arranged on a glass substrate in rows and columns,
They are arranged in a so-called matrix. In this drawing, the switching TFT is manufactured in an n-channel type.

The basic structure of the switching TFT is the same as that shown in FIGS. 16 and 17, and a polycrystalline semiconductor film 1 made of polysilicon is formed on a glass substrate 10.
Gate insulating film 2 made of SiO ₂ , gate electrode 4 and S
An interlayer insulating film 3 made of iO ₂ is sequentially stacked.

Here, the gate electrode 4 comprises a lower electrode 42 made of a transparent conductive film and an upper electrode 41 made of a metal having a narrower width and fixed to the upper surface of the electrode 42. The polycrystalline semiconductor film 1 under the interlayer insulating film 2 has a channel region 170 located immediately below the upper gate electrode 41 and an impurity under the gate electrode protrusions 425 and 426 below both sides thereof. LDD regions (N ⁻ layers) 152 and 162 having a low concentration, a source region (N ⁺ layer) 150 and a drain region (N ⁺ layer) 16 having a high impurity concentration
It consists of 0.

Further, a pixel electrode 11 made of a transparent conductive film patterned in a predetermined shape is provided in the pixel area, and is connected to the drain electrode 6 via a contact hole.

Incidentally, the lower electrode 42 and the pixel electrode 11
Are made of the same transparent conductive film. That is, the transparent conductive film of the same layer is patterned, and a part thereof is used as a lower gate electrode and a part is used as a pixel electrode 11. For this reason, the number of processes is reduced by one compared with the case where both films are formed individually.

Hereinafter, a method of manufacturing the thin film transistor will be described with reference to FIG.

This drawing is a diagram schematically showing the manufacturing process of this TFT array, and is basically the same as FIG. The right side is a pixel portion.

Hereinafter, portions different from FIG. 19 will be described.

(C ′) A lower electrode film and a pixel electrode film are simultaneously formed.

A transparent conductive film 420 for forming a lower gate electrode and a pixel electrode film was deposited on the gate insulating film 2. This was formed by a sputtering method. The ITO film has a thickness of about 500 °. Note that a conductive oxide film other than ITO may be used as the transparent conductive film. Further, an upper gate electrode film 410 was formed thereon.

(D ′) The upper gate electrode 41 was formed by patterning.

(E ′) The lower gate electrode 42 and the pixel electrode 11 were formed by patterning.

Hereinafter, the same steps as those of the other embodiments are performed.
A D-type TFT was manufactured.

In this embodiment, the pixel switching TFT is formed on a glass substrate.
And a liquid crystal panel drive circuit can be manufactured on a glass substrate. At that time, in order to manufacture a p-channel TFT,
For example, boron ions may be implanted as impurities.

(2-7th Embodiment) The thin film transistor itself of this embodiment is basically the same as those shown in FIGS. 18A and 18B.

FIG. 23 schematically shows a method of manufacturing a thin film transistor according to the present embodiment. Hereinafter, the method of manufacturing the TFT according to the present embodiment will be described with reference to FIG.

(A) First, an undercoat SiO ₂ film 12 for preventing impurities from being eluted from glass on a glass substrate 10
Was deposited to a thickness of about 3000-7000 °. An amorphous silicon film was formed thereon and processed into an island shape to form a thin film transistor.

Further, the polysilicon film 1 was obtained by polycrystallizing the amorphous silicon film by annealing treatment by excimer laser irradiation. Further, by a plasma CVD method using TEOS as a source gas, S
An iO ₂ film was formed to a thickness of about 1000 °. FIG. 7A shows this state. Therefore, the operation up to this point is the same as in the conventional embodiment.

(B) Tantalum was formed to a thickness of 200 nm as the lower gate electrode forming film 420, and an aluminum alloy was formed to a thickness of 150 nm as the upper gate electrode forming film 410.

(C) A resist film 13 of a photo-curable resin for forming an upper gate electrode was formed on the aluminum alloy film 410 and irradiated with ultraviolet rays (UV) through a mask 14.

(D) The resist film 13 is left only on the upper surface of the upper gate electrode 41.

(E) An unnecessary portion of the upper gate electrode film was etched to form an upper gate electrode 41. Note that this etching was performed by dry etching using a chlorine-based gas that has higher precision than wet etching.

(F) On the upper surface of the upper gate electrode 41, only the side surface of the aluminum alloy of the upper gate electrode film is anodized while the resist 13 is left.
4106 was formed. As the anodizing solution, a 0.1 M oxalic acid aqueous solution or the like was used. An oxidation film having a width of about 500 nm is formed at both ends of the gate at an oxidation voltage of 15 V for about 30 minutes. Also, an oxide film of 30 to 50 nm was formed on the surface of the lower gate electrode film.

(G) After removing the resist, unnecessary portions of the lower gate electrode film and the anodic oxide film on the upper surface thereof were removed by chemical dry etching in a self-aligned manner using the anodic oxide film as a mask. Subsequently, only the anodic oxide film covering the side surface of the upper gate electrode was removed with a hydrofluoric nitric acid solution containing ethylene glycol. As a result, a two-stage gate electrode was formed in which the lower portion slightly protruded toward the source electrode and the drain electrode.

(H) Using the upper gate electrode 41 and the lower gate electrode 42 as a mask, phosphorus ions were implanted as impurities from the upper portion by ion doping.
As a result, the region 15 covered by the lower gate electrode 42
In Nos. 2 and 162, most of the phosphorus ions are captured by the lower gate electrode, so that only a low concentration is implanted into the phosphorus ions, thereby forming an LDD region (N ⁻ layer). The regions 150 and 160 that are not covered by the lower gate electrode 42 become N ⁺ layers in which phosphorus ions are implanted at a high concentration. In addition, the region 170 covered with the upper gate electrode 41 and the lower gate electrode is not implanted with phosphorus ions at all and becomes a channel region. As a result, an LDD type TFT was naturally formed.

Thereafter, an SiO ₂ film 2 having a thickness of 400 nm was deposited as an interlayer insulating film. Subsequently, contact holes were opened in the interlayer insulating film and the gate insulating film. Subsequently, an Al film was deposited by sputtering with good coverage of the contact hole region, and then patterned into a predetermined shape to form a source electrode and a drain electrode. However, these are the same as in the previous embodiment, so illustrations and the like are omitted.

(Embodiment 2-8) This embodiment is a further simplification of the method for forming a gate electrode of the above embodiment.

Hereinafter, the present embodiment will be described with reference to FIG.

(D ') Deposition of a semiconductor layer gate insulating film and upper and lower gate electrode films 410 and 420 on a substrate, application of a resist 13 thereon, and further patterning by exposure of the resist. This is the same as the embodiment. The lower gate electrode forming film 420 is 200 n
m of tantalum, and the upper gate electrode forming film is 15
It is an aluminum alloy of 0 nm.

(E ′) The upper and lower gate electrode films are etched by using a fluorine-based gas to form the upper gate electrode 41.
And a lower gate electrode 42 were formed. In this state, there is no protrusion between the upper and lower gate electrodes.

(F) With the resist 13 left, only the side surfaces of the upper gate electrode and the lower gate electrode were anodized to form anodic oxide films 4105 and 4106. As an anodizing solution, a 0.1 M oxalic acid aqueous solution or the like was used. The voltage was 15 V, and in about one hour, a 30 nm oxide film was formed on the side surface of the lower gate electrode, and an oxide film of about 1 μm was formed on the side surface of the upper gate electrode.

(G) Only the side surface of the upper gate electrode is 0.1
M with ethylene glycol tartrate solution, etc.
Oxidized for about a minute to adjust the gate electrode width.

Thereafter, the LD is produced in the same manner as in the previous embodiment.
A D-TFT was formed.

FIG. 25 shows the voltage / current characteristics of the TFT manufactured by the above method. In the figure, a line L1 shows the characteristics of the conventional LDD TFT, and a line L2 shows the characteristics of the conventional structure (nonLDD structure). Line L3 is the voltage / current characteristic of the TFT of the present embodiment. As is clear from the lines L1 and L2, in the TFT having the conventional structure, the off current can be reduced by using the LDD structure. However, with the LDD structure, the on-current is reduced.

On the other hand, in the case of this embodiment, the off current can be reduced and the on current is not reduced.
That is, in the TFT of the present embodiment, a high-resistance LDD
Since the region is immediately below the gate electrode, in the saturated region and the unsaturated region, electrons serving as carriers are accumulated in both the LDD region and the channel region, so that the on-state current does not decrease.

(2-9th Embodiment) FIG. 26 shows a liquid crystal display device using the TFT of this embodiment. Cross section of the pixel switching TFT and the pixel electrode area,
The switching TFTs and pixels of this embodiment are basically the same as those shown in FIG.

However, the lower portions 52 and 62 of the source electrode and the drain electrode are made of Ti which forms the silicide with silicon and the electric resistance at the interface is reduced.
The pixel electrode 11 is made of aluminum because it is made of aluminum having a small electric resistance and is a reflective display device. Further, in an actual use state, an alignment film serving both as insulation of the source electrode 5, the drain electrode 6, and the pixel electrode 11 and for aligning the liquid crystal is formed thereon.

A method for manufacturing this liquid crystal display device will be described with reference to FIG. Note that, since it is basically the same as that shown in FIG. 23 and the like, only the main part will be described.

The steps up to (c) forming the lower gate electrode film 420 and the upper gate electrode film 410 are the same.

(D-1) The upper gate electrode 41 is formed by patterning using the resist 13.

(D-2) The side of the upper gate electrode 41 is
Anodizing is also performed using the resist 13.

(D-3) Anodizing portions 4105 and 4106
Using the upper gate electrode 41 having the pattern 13 and the resist 13 as an etching stopper, the lower gate electrode 42 having a protruding portion is formed.

(E) Impurities are implanted using the upper and lower gate electrodes as an implantation mask.

Also in the present embodiment, a liquid crystal panel drive circuit may be manufactured on a glass substrate by manufacturing a C-MOS inverter circuit or the like constituted by similar TFTs. At this time, a p-channel TFT needs to be manufactured. However, a p-channel TFT can be manufactured by implanting boron ions in the same process as the above manufacturing method.

(Embodiment 2-10) In this embodiment, only one of the source region side and the drain region side has the L level.
It has a DD structure.

Now, in some cases, the semiconductor element in the pixel portion of the liquid crystal display device does not need to have the LDD structure on both sides. In addition, if only one of the LDDs is used, the stray capacitance of the semiconductor element is reduced, so that it may be preferable in some applications. Therefore, in the present embodiment, FIG.
As shown in (a) of FIG.
The gate electrode 43 of about 1 to 2 μm protrudes only toward the source electrode side of the second gate electrode. And
As shown in FIG. 28B, impurity ions are implanted from below the substrate from below. Thereby, an LDD semiconductor element is obtained on only one side.

(Embodiment 2-11) This embodiment utilizes the oxidation of the gate electrode metal.

Many metals such as iron oxidize at a constant rate under a constant temperature, pressure and the like, except for magnesium and passive metals which explosively burn depending on the case (for example, disposable). Cairo and others make use of this phenomenon or law). In general, when a metal is oxidized, its density decreases, and its volume further increases.

For this reason, the portion where the gate electrode expands in the channel direction due to metal oxidation is less effective as a mask for implanted impurity ions. The present embodiment utilizes this.

Hereinafter, the present embodiment will be described with reference to FIG.

(A) The gate electrode 4 is formed using iron or the like as a material.

(B) The entire substrate is heated to a constant temperature under vacuum.

(C) Supply low-pressure air containing oxygen determined from the oxidation amount of iron used as the gate electrode. The low pressure is used here to prevent local oxidation, and may be oxygen diluted with argon or the like.

(D) The upper and side surfaces of the gate electrode are oxidized by a certain amount, and a metal oxide film having a thickness of about 0.5 μm is formed as the upper gate electrode 43 (more precisely, only as an upper implantation mask). With the formation of the metal oxide film, the metal oxide film protrudes toward the source electrode side and the drain electrode side of the gate electrode.

(E) In this state, impurities are implanted from the upper surface of the substrate.

(F) Compensation for irregularities in impurity implantation in the LDD region due to irregularities in metal oxide particles and the like by removing the oxide film as necessary and performing a heat treatment for purging hydrogen and bonding dangling bonds. I do.

Hereinafter, the LD is performed in the same procedure as in the previous embodiment.
A D-type TFT is manufactured.

In the present embodiment, the gate metal material is iron, but may be aluminum, chromium, or an alloy thereof. In many of these cases, a passive state is formed, but in this case, the oxide film thickness is naturally constant. Also, in some cases, oxide removal will often be unnecessary.

Further, when iron is used, after implantation of impurities,
Further, an aluminum layer may be provided on the upper surface.

Furthermore, the upper portion of the gate electrode may be formed of a high-density metal such as W, and the lower portion may be formed of a low-resistance metal such as aluminum, and both may be oxidized simultaneously or separately by liquid or electricity. In this case, a high-density metal such as W at the upper portion blocks the permeation of hydrogen, and a low-resistance metal such as aluminum at the lower portion provides low resistance. In this case, if the oxide film is removed after the implantation of the impurity, an LDD TFT having no GOLD structure can be obtained.

<< Third Invention Group >> (Third Embodiment) This embodiment is directed to the implantation of impurities for forming the LDD type TFTs of the first invention group and the second invention group. Prior to this, the gate insulating film except for the lower part of the gate electrode is once removed.

That is, if the gate insulating film is present, the accelerating voltage at the time of impurity implantation must be increased by that amount. However, hydrogen for diluting impurities is excessively accelerated and penetrates to a heavy gate electrode as a mask. This adversely affects the semiconductor in the channel region thereunder.

Further, impurities are scattered in the gate insulating film in the horizontal direction, and therefore, particularly, the boundary between the channel region and the LDD region becomes unclear. As a result, the channel region is 1 μm,
In a small semiconductor device having an LDD region of about 0.2 μm,
Problems may occur depending on the application.

Further, it is difficult to make the gate insulating film completely uniform in thickness, which also hinders uniform implantation of impurities regardless of the high concentration region or the LDD region.

Therefore, in this embodiment, the gate insulating film excluding the portion immediately below the gate electrode is removed in advance when the impurity is implanted. Hereinafter, the present embodiment will be described with reference to FIG.

(A) The upper electrode slightly protrudes toward the source electrode side and the drain electrode side of the lower electrode, or conversely, the lower electrode 42 protrudes slightly from both sides of the upper electrode 43 as shown in the figure. A clean gate electrode is formed.

(B) The gate insulating films 25 and 26 except the portion immediately below the gate electrode are removed. Further, if necessary, heat treatment for recovering the surface of the p-Si film damaged by etching and formation of an extremely thin insulating film on the surface are performed.

(C) Impurities are implanted from above.

(D) The gate insulating film in the removed portion is formed again.

Hereinafter, the LD is performed in the same procedure as in the other embodiments.
A D-type TFT is manufactured.

As a result, an extremely excellent LDD type TFT was obtained, although it was troublesome.

(Third Embodiment) This embodiment is similar to the above-mentioned third embodiment, but uses a gate insulating film for forming an LDD region.

Hereinafter, this embodiment will be described with reference to FIG.

(A) The gate electrode 4 is formed on the gate insulating film 2.

(B) On the side of the source electrode and the side of the drain electrode of the gate electrode, 0.3 to 1 μm depending on the size of the element.
Gate insulating films 254 and 264 excluding portions that have protruded to a degree
Is removed. Further, if necessary, the exposed p-Si film is subjected to a heat treatment or the like.

At this time, the removal of the gate insulating film excluding the portion that protrudes by about 0.3 to 1 μm is performed by oxidizing the gate electrode 4 or performing metal plating, for example, as shown in FIG. (D) and the state shown in FIG. 23 (f), the insulating film is removed by etching using the gate electrode in this state as an etching mask, and furthermore, the oxide or plating film adhering to the gate electrode is removed. Can be

(C) Impurities are implanted from above.

(D) The gate insulating film 2 is formed again.

Hereinafter, the LD is performed in the same procedure as in the other embodiments.
A D-type TFT is manufactured.

As a result, an extremely excellent LDD-type TFT was obtained, although it was troublesome.

{Fourth Invention Group} (Embodiment 4-1) In this embodiment, prior to the implantation of impurities in the aforementioned Embodiment 3-1,
In order to prevent the intrusion of hydrogen, a Ti film is previously formed on the bare p-Si film.

That is, when implanting impurities, H ₂ is used to dilute the impurities. For this reason, the highly accelerated hydrogen ions due to their small mass may be deeply implanted into the semiconductor layer at a high speed due to their small diameter, which adversely affects the performance of the semiconductor. As a countermeasure, with the gate insulating film removed, a Ti layer that is excellent in absorbing hydrogen into the upper surface of the semiconductor and has a low density that does not hinder the implantation of impurities is formed to prevent hydrogen from entering the semiconductor layer. In addition, it is very difficult to etch at the correct depth because it is the same silicon-based material as the semiconductor layer when forming the source and drain electrodes. It plays a role and further contributes to ensuring good electrical contact between the source and drain electrodes and the semiconductor layer.

The present embodiment will be described below with reference to FIG.

(A) The gate electrodes 42 and 43 in which one end of the upper or lower gate electrode on the source electrode side and the drain electrode side protrudes from the end of the other gate electrode.
To form

(B) The gate insulating films 25 and 26 except for the lower part of the gate electrode are once removed.

(C) A Ti film 18 is formed on the entire surface.

(D) Impurity ions are implanted from above.

(E) Except for the portions 52 and 62 which are the lower portions (including some peripheral portions) of the source electrode and the drain electrode,
The Ti film is removed.

(F) The gate insulating film 2 is formed again, and further the interlayer insulating film 3 is formed.

(G) A contact hole 9 is formed at a position where a source electrode and a drain electrode are to be formed. On this occasion,
The Ti film left in (e) or the titanium silicide film on the p-Si surface formed by the reaction of the Ti with the silicon in the heat treatment after implantation and the unreacted Ti on the Ti film serve as an etching stopper.

(H) A contact hole is filled with Al,
A source electrode 5 and a drain electrode 6 are formed.

In the present embodiment, Ti silicide is formed at the lower ends of the source electrode and the drain electrode by the reaction with p-Si, and the electrical contact at the interface between the silicon layer and the Ti silicide layer is improved. Furthermore, the electrical contact at the interface between Ti silicide and Ti is also good, and the interface between the upper part of the Ti layer and aluminum is also the same metal, so that the electrical contact is good. Further, the acceleration voltage is low due to the absence of the gate insulating film. On the other hand, since the Ti layer absorbs hydrogen, the pain of the p-Si layer due to high-speed hydrogen ions and the penetration of hydrogen into the p-Si layer are small.

In addition, since Ti and its silicide have different chemical properties from silicon-based materials, the drilling stops at the insulating film without any special care when drilling a contact hole in the insulating film. Become. In turn,
A margin for the etching depth is not required for the thickness of the p-Si layer, and the contact of the p-Si layer with the source electrode and the like does not vary. For this reason, a very excellent LDD type TFT was obtained.

<< Fifth Invention Group >> (5-1-1th Embodiment) The present embodiment relates to a semiconductor device having a bottom gate type LDD structure.

Although the semiconductor device having the LDD structure of the bottom gate type has restrictions based on the difference in structure from the top gate type, the ideas of the above-described inventions can be applied.

The present embodiment will be described below with reference to FIG.

(A) A gate electrode 4, a gate insulating film 2, and a p-Si layer 1 are formed on a substrate 10.

(B) After forming an interlayer insulating film directly on the p-Si layer, and further above them and directly above the gate electrode,
A patterned lower metal mask 47 made of high density metal is formed.

(C) On the lower metal mask 47, an upper metal mask 48 whose ends slightly protrude toward the source electrode side and the drain electrode side is formed by plating or oxidation.

(D) Impurities are implanted from the upper surface of the substrate.

(E) The upper and lower metal masks are removed.

After forming an interlayer insulating film as necessary, a contact hole is formed, and a source electrode and a drain electrode are formed.

In this embodiment, a Ti film is further formed in a state where the upper and lower masks are formed without forming the interlayer insulating film, and the lower ends of the source electrode and the drain electrode are formed after the impurity is implanted. The film may be used as an etching stopper when forming a contact hole without removing the film. As a result, it is also possible to ensure good electrical contact between the two electrode portions, as in the embodiment 4-1.

(Embodiment 5-2) The present embodiment is directed to
In the embodiment 5-1 described above, in order to form a mask with high accuracy, a gate electrode already formed on a glass substrate is used.

The present embodiment will be described below with reference to FIG. 34. (a) A gate electrode 4, a gate insulating film 2, and a p-Si layer made of a high-density metal such as Ta or Ag are sequentially formed on a substrate. Form.

(B) A photosensitive resin layer 49 is formed on the substrate.

(C) Light, ultraviolet rays or X-rays are irradiated from the back surface of the substrate using the gate electrode as a mask to expose the photosensitive resin.

At this time, since it is p-Si, light and ultraviolet light are easily transmitted without being scattered. In addition, in the case of X-ray irradiation, at present, it is difficult to manufacture a lens or the like. Therefore, it is preferable to irradiate X-rays at some distance from the substrate (provided with an X-ray source) as compared with ultraviolet rays. In addition, the intensity and wavelength of each electromagnetic wave, of course, take into account the material and thickness of the substrate, which greatly affects the attenuation by absorption, and the photosensitivity of the resin.

By the way, the substrate in this state is about 48 cm square and its thickness is at most 1 mm. Therefore, irrespective of the position of the gate electrode on the substrate, only the portion of the resin immediately above the gate electrode on the substrate is exposed.

(D) After development by heating or the like, the exposed portion of the resin 491 is removed, and a lower mask metal film 470 is formed on the upper surface of the substrate.

(E) The unexposed portion of the resin film 49 is removed together with the upper portion of the lower mask metal film 470.
As a result, the lower mask metal film 47 remains only in the exposed portion where the resin is present.

(F) By electroplating, an upper mask metal film 48 of a predetermined material and thickness is formed on the side and upper surfaces of the exposed lower portion of the lower mask metal film 47 after the resin.

(G) Impurities are implanted from the upper surface of the substrate.

(H) The upper and lower metal masks are removed.

After that, formation of an interlayer insulating film, formation of a contact hole, and formation of a source electrode and a drain electrode are performed.

As a modification of this embodiment, using a conductive photosensitive resin (currently a mixture of both resins), only the unexposed portion of the resin above the gate electrode is left as an implantation mask. Further, although it may take some time on the side, a metal may be plated to be used as a mask for LDD formation.

(Embodiment 5-3) This embodiment is directed to
The gate electrode is formed of silicide or a multilayer having at least one silicide layer.

However, since the manufacturing method itself is basically not different from that already described, the description is omitted. In addition, since the structure is not particularly complicated, dedicated drawings are omitted, and drawings of other embodiments are shown. FIG. 33A shows the case of a silicide gate electrode, and FIG. 33E shows the case of a metal electrode 414 on the upper side and a silicide electrode 413 on the lower side.

As a modification, in order to prevent the occurrence of hillocks, the lower aluminum electrode may be wrapped with a lower concave upper silicide electrode and a glass substrate.

{Sixth Invention Group} The invention groups are the same as those of the first to fourth embodiments except that they are not LDD, and therefore one of the upper and lower gate electrodes does not have a protruding portion with respect to the other. Same as the invention group. For this reason, the description using the dedicated drawings is omitted.

(Embodiment 6-1) FIG. 30 (a)
(E), the upper gate metal 43 and the lower gate metal 42 have the same length in the channel direction, unlike FIG.
As a result, just like 13 and 41 in FIG. 23B, they are formed at once by dry etching so that there is no protrusion. At this time, one of the upper gate metal 43 and the lower gate metal 42 is an aluminum alloy having a small electric resistance, and the other is tungsten having a large masking effect on hydrogen.

In this embodiment mode, since there is no gate insulating film, the driving voltage may be lower by that amount.
It became.

{Seventh Invention Group} (Embodiment 7-1) In this embodiment, a plurality of types of LDD TFTs having different characteristics are formed on a substrate.

In the driving circuit portion and the pixels of the liquid crystal display device,
Because the characteristics required for the LDD type TFT are different,
Depending on the application, it is necessary to form an LDD type TFT having a specific property at a specific position on the substrate. In this case, the size of the semiconductor element, the length of the channel region, and the like may be determined according to the size of the hole of the mask in the Photsonography.

Next, regarding the LDD section, in the present embodiment, when the upper gate electrode is formed by plating on the lower gate electrode, the plating time, voltage, and type of metal to be plated are determined on the substrate. It is changed according to.

According to the present embodiment, under the easiness of control,
When the thickness of the upper gate electrode was large, a TFT having a desired LDD region length was obtained by extending the plating time.

FIG. 35 conceptually shows a part of these states. (A) of this figure is a case where the voltage is changed depending on the place, and (b) is a case where the time is changed depending on the place using the timer switch.

[0367] As a modification of the present embodiment, although it takes some time, the concentration of the plating solution and the type of metal may be changed for each location. In this case, the length of the LDD part is
Although different, the ability as a mask when implanting impurities is
It is possible that they are almost the same.

(Embodiment 7-2) In this embodiment, an LDD type TFT having characteristics according to the formation position on the substrate is formed in the same manner as in the previous embodiment. As a means, after the impurity is implanted, a portion of the gate electrode immediately above the LDD portion is removed.

Hereinafter, the present embodiment will be described with reference to FIG.

(A) First, an LDD semiconductor T
An FT is formed.

(B) After the impurity is implanted, a resist layer 1310 is formed only on portions where the protruding portions are not removed.

(C) The metal forming the protruding portion is oxygen,
It is removed by dry etching using fluorine or the like. Therefore, in this portion, if the lower gate electrode protrudes, the upper gate electrode protects the lower gate electrode from the etching gas.

If the upper gate electrode protrudes from the lower gate electrode, the entire upper gate electrode is removed. In this figure, only the pixel portion of the liquid crystal display device has part of the gate electrode removed.

The formation of an interlayer insulating film, the formation of a contact hole, and the formation of a source electrode and a drain electrode are performed below.

(Embodiment 7.3) In this embodiment, an upper or lower electrode is used to change the amount of protrusion of a predetermined amount of the upper or lower gate electrode in accordance with the location, and the other is replaced with the other electrode. The size of the hole of a Photsonography mask used to protrude from the electrode is changed from place to place.

For this reason, the holes in the photolithography mask are adapted from the beginning to the formation of the LDD TFT corresponding to the location on the substrate. However, such a mask and a method of manufacturing an element using such a mask are basically the same as those already described, and thus the description thereof is omitted. The structure is not particularly complicated, so that the illustration is omitted.

Although the present invention has been described based on some embodiments, it is needless to say that the present invention is not limited to these embodiments. That is, for example, the following may be performed.

1) Uses include liquid crystal television receivers,
Other than liquid crystal display devices such as word processors, for example, EL
It is a display.

2) As a semiconductor material, besides Si, Si
-Ge, Si-Ge-C or the like is used.

3) In the first to third embodiments,
At the stage where the metal thin film is formed so as to have a longer length in the channel region direction on the patterned amorphous silicon layer of (b), impurity ions are implanted, and then silicide due to a chemical reaction between the amorphous silicon and the metal thin film The substrate is heated at 550 ° C. to 650 ° C. for about 20 minutes for both the formation of the layer and the heat treatment of the polysilicon.

4) In the first to third embodiments, (a)
A silicide film is formed in place of the amorphous silicon, and a pattern is formed in the same manner as in (b), and a metal film is formed on the silicide film so as to slightly cover the silicide. Thereafter, the impurity is implanted without going through the step (c).

5) The cross section in the channel direction of the gate electrode shown in FIGS. 3 and 4 is not a trapezoid that spreads out (downward) but a rectangle.

6) In forming a panel, formation of any gate electrode film also serves as formation of a reflector, a pixel electrode, and the like.

7) In the case of a bottom gate, when exposing the resin from the substrate side, the semiconductor layer is made as thin as possible, and the insulating film is made of a light-transmitting resin. Like that.

8) In order to change the characteristics of the LDD type TFT, the upper and lower electrodes have the same length in the channel direction, and thus have no GOLD structure.

[0386]

As can be seen from the above description, according to the present invention, a thin film transistor having an LDD structure and capable of forming a source region, a low concentration impurity region, a channel region, and a drain region in a self-aligned manner. Can be realized. Therefore, it is possible to reduce the OFF current and suppress the decrease in the ON current. In addition, since it has a self-aligned structure, the parasitic capacitance can be reduced, and thus miniaturization is possible.

Further, the present invention can be applied to a bottom gate type semiconductor element.

Further, it becomes possible to form an LDD type TFT having a characteristic corresponding to a place on each part of one substrate.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross section of a thin film transistor having a conventional LDD structure.

FIG. 2 is a diagram showing a cross section of a thin film transistor having a GLD type LDD structure according to the related art.

FIG. 3 is a cross-sectional view of a semiconductor device according to Embodiment 1-1 of the present invention;

FIG. 4 is a first half of a diagram showing a change in a cross section in a process of forming the semiconductor element of the above embodiment.

FIG. 5 is a diagram showing a change in a cross section in a forming process following FIG. 4;

FIG. 6 is a diagram showing a change in a cross section accompanying a process of forming a semiconductor element according to a first embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a first to third embodiments of the present invention;

FIG. 8 is a diagram showing a cross section of a semiconductor device according to a first to fourth embodiments of the present invention and the principle thereof.

FIG. 9 is a sectional view of a semiconductor device according to a first to fifth embodiments of the present invention.

FIG. 10 is a diagram showing a principle and a cross section of a semiconductor device according to a first to sixth embodiments of the present invention.

FIG. 11 is a cross-sectional view of a thin film transistor according to Embodiment 2-1 of the present invention;

FIG. 12 is a diagram illustrating the first half of the manufacturing process of the thin film transistor of the above embodiment.

FIG. 13 is a diagram illustrating the latter half of the manufacturing process of the thin film transistor of the above embodiment.

FIG. 14 is a diagram illustrating a main part of a manufacturing process of the thin film transistor according to the second embodiment of the present invention;

FIG. 15 is a diagram illustrating a main part of a manufacturing process of the thin film transistor according to the second to third embodiments of the present invention;

FIG. 16 is a diagram showing a plane and a cross section of a pixel TFT of a liquid crystal panel using the thin film transistor of the present invention.

FIG. 17 is a plan view and a sectional view showing another pixel TFT of a liquid crystal panel using the thin film transistor of the present invention.

FIG. 18 is a diagram schematically showing a cross section of a TFT according to a second to fifth embodiments of the present invention.

FIG. 19 is a view schematically showing the TFT manufacturing method of the above embodiment.

FIG. 20 is a diagram showing voltage / current characteristics of the TFT of the above embodiment.

FIG. 21 is a diagram schematically illustrating a pixel electrode using the TFT array of the above embodiment.

FIG. 22 is a diagram schematically illustrating a main part of a method for manufacturing a pixel electrode using the TFT array according to the above embodiment.

FIG. 23 is a view schematically showing a method of manufacturing a TFT according to a second to seventh embodiments of the present invention.

FIG. 24 is a diagram illustrating a method of manufacturing a TFT according to a second to eighth embodiments of the present invention.

FIG. 25 is a diagram showing TFT voltage / current characteristics of the above embodiment.

FIG. 26 is a view schematically showing a TFT array according to a second to ninth embodiments of the present invention.

FIG. 27 is a diagram schematically illustrating a method of manufacturing the TFT array according to the above embodiment.

FIG. 28 shows a TFT according to a second to tenth embodiments of the present invention.
FIG. 4 is a diagram schematically illustrating an array manufacturing method.

FIG. 29 shows a TFT according to a second to eleventh embodiments of the present invention.
FIG. 4 is a diagram schematically illustrating an array manufacturing method.

FIG. 30 is a view schematically showing a method of manufacturing the TFT array according to the embodiment 3-1 of the present invention;

FIG. 31 is a view schematically showing a method of manufacturing the TFT array according to the third to third embodiments of the present invention.

FIG. 32 is a view schematically showing a method of manufacturing the TFT array according to the fourth embodiment of the present invention.

FIG. 33 is a drawing schematically showing a manufacturing method of the TFT array according to the 5-1 embodiment of the present invention;

FIG. 34 is a view schematically showing a method of manufacturing a TFT array according to a fifth to second embodiments of the present invention.

FIG. 35 is a view schematically showing a method for manufacturing a TFT array according to the seventh to seventh embodiments of the present invention.

FIG. 36 is a view schematically showing a manufacturing method of the TFT array according to the seventh to second embodiments of the present invention;

[Explanation of symbols]

1 p-Si semiconductor (layer) 100 a-Si semiconductor (layer) 150 Same as above (source region) 151, 152 Same as above (source side LDD
156 Same as above (multi-stage LDD section) 1562 Same as above (LDD section) 160 Same as above (drain region) 161 and 162 Same as above (Drain side LDD)
170 Same as above (Channel region) 175 Same as above (Source electrode side) 176 Same as above (Drain electrode side) 2 Gate insulating film 25 Gate insulating film (Source electrode side) 26 Gate insulating film (Drain electrode side) 3 Interlayer insulating film 4 Gate Electrode 41 Sub-gate electrode, upper gate electrode 413 Lower silicide gate electrode 4130 Amorphous silicon gate electrode 414 Upper metal gate electrode 4141 Overhanging portion of upper metal gate electrode 415 Silicide gate electrode 416 Lower metal gate electrode 417 Middle metal gate electrode material 42 Lower Gate electrode 421 First lower gate electrode 422 Second lower gate electrode 43 Upper gate electrode 431 First upper gate electrode 432 Second upper gate electrode 435 Upper gate electrode source side protrusion 436 Sub gate electrode drain Exposed portion 47 Lower implantation mask 48 Upper implantation mask 49 Photosensitive resin 5 Source electrode 51 Source electrode upper 52 Source electrode lower (silicide) 6 Drain electrode 61 Drain electrode upper 62 Drain electrode lower (silicide) 9 Contact hole 95 Contact hole (source electrode side) 96 Contact hole (drain electrode side) 10 Glass substrate 11 Pixel electrode 12 Undercoat film 13 Resist film 14 Alignment film 18 Titanium film 19 Exposure mask

Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court II (Reference) H01L 29/78 617K 617L 617M (31) Priority Claim Number Japanese Patent Application No. 11-83314 (32) Priority Date March 1999 26 (1999. 3.26) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 11-83316 (32) Priority date March 26, 1999 (March. 1999) 26) (33) Priority Country Japan (JP) (72) Inventor Mayumi Inoue 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Tetsuro Kawakita 1006 Kadoma Kadoma Kadoma, Osaka Matsushita Inside Electric Industrial Co., Ltd. MA17 MA25 MA27 MA30 MA41 NA01 NA11 NA22 NA23 NA24 NA29 PA01 PA12 5C094 AA13 AA43 BA03 BA45 CA19 EB05 GB10 5F110 AA02 AA03 AA06 AA16 BB02 BB04 CC02 CC08 DD02 DD13 EE02 EE03 EE04 EE05 EE06 EE07 EE08 EE09 EE14 EE15 EE22 EE23 EE24 EE28 EE33 EE34 EE41 EE44 EE45 FF12 HL29 HK30 GG30 H12 GG30 NN04 NN23 NN24 NN35 NN72 PP03 PP04 PP35 QQ01 QQ03 QQ04 QQ05 QQ08 QQ11 QQ12

Claims (71)

[Claims] A semiconductor layer having a source region, a drain region, and a gate region formed on a substrate, a gate insulating film, a source electrode, a drain electrode, and a gate electrode formed on the gate insulating film. In the semiconductor device having the above-mentioned structure, the gate electrode is composed of upper and lower layers composed of a silicide thin film and a metal thin film, and one thin film slightly protrudes into at least one of the other thin film on the source electrode side and the drain electrode side. L formed
Since the semiconductor layer is implanted with impurity ions using the LDD formation mask / gate electrode as an implantation mask, the semiconductor layer is determined from the positions of the silicide thin film and the metal thin film and the direction of implantation of the impurity ions. LDD formed in the region corresponding to gate electrode position
A semiconductor element having a region. 2. A semiconductor layer having a source region, a drain region, and a gate region formed on a substrate, a gate insulating film, a source electrode, a drain electrode, and a gate electrode formed on the gate insulating film. In the semiconductor device, the gate electrode is composed of upper and lower silicide thin films, and one of the thin films is also used as an LDD forming mask formed by slightly protruding into at least one of the source and drain electrodes of the other thin film. A gate electrode, wherein the semiconductor layer is implanted with impurity ions using the LDD formation mask / gate electrode as an implantation mask, and corresponds to a gate electrode position determined from the positions of the silicide thin film and the metal thin film and the direction of impurity ion implantation. LDD formed in the region
A semiconductor element having a region. 3. A semiconductor layer having a source region, a drain region, and a gate region formed on a substrate, a gate insulating film, a source electrode, a drain electrode, and a gate electrode formed on the gate insulating film. In the semiconductor device having the gate electrode, the gate electrode is composed of a multilayer having at least a silicide thin film, a metal thin film, and a silicon thin film. Further, as a mask at the time of impurity implantation, the center is the thickest, the ends are the thinnest, and the middle is the middle. A multi-stage LDD formation mask / gate electrode that gradually increases in thickness from the middle to the center side from both sides, and the semiconductor layer is configured to implant impurity ions from above using the multi-stage LDD formation mask / gate electrode as an implantation mask. Since it is implanted, it has a multi-stage LDD region formed at a position determined by the mask thickness and the direction of implanting impurity ions. The semiconductor device characterized Rukoto. 4. A semiconductor layer having a source region, a drain region, and a gate region formed on a substrate, a gate insulating film, a source electrode, a drain electrode, and a gate electrode formed on the gate insulating film. In the semiconductor device having the above, the gate electrode has a layer made of a high melting point metal thin film, a layer made of a silicide thin film, and a layer made of an aluminum thin film surrounded by the high melting point metal thin film layer and the silicide thin film layer. Further, as the mask thickness, an LDD mask / intermediate aluminum layer-containing gate electrode having the largest thickness at the center portion and the thinnest at both end portions is provided. To implant impurity ions from above,
L having a single-stage or multi-stage LDD region formed at a position determined from the mask thickness and the direction of impurity implantation
A semiconductor device, which is a DD semiconductor device. 5. The silicide thin film according to claim 1, wherein the silicide thin film is a specific material silicide thin film selected from the group consisting of titanium silicide, cobalt silicide, nickel silicide, zirconium silicide, molybdenum silicide, palladium silicide, and platinum silicide. 5. The semiconductor device according to claim 2, 3 or 4. 6. The thin film of at least one metal or the thin film of high melting point metal, wherein the constituent metal element is a metal thin film of the same material as the metal element forming the silicide. Semiconductor element. 7. The semiconductor element has a silicide thin film layer of the same material as a silicide thin film of the gate electrode at a contact portion between the source electrode and the source region and a contact portion between the drain electrode and the drain region. The semiconductor device according to claim 1, 2, 3, or 4, wherein 8. The semiconductor element has a silicide thin film layer of the same material as a silicide thin film of the gate electrode at a contact portion between the source electrode and the source region and a contact portion between the drain electrode and the drain region. The semiconductor device according to claim 5, wherein 9. The semiconductor device according to claim 1, further comprising: a silicide thin film of the same material as the silicide thin film of the gate electrode at a contact portion between the source electrode and the source region and a contact portion between the drain electrode and the drain region. 7. The semiconductor device according to claim 6, wherein: 10. A basic forming step of forming a semiconductor layer at a predetermined position on a substrate, further forming a gate insulating film on the formed semiconductor layer, and forming at least a silicide thin film layer on the formed gate insulating film. It has a plurality of layers including at least one layer, and at least one layer protrudes in at least one direction of the source electrode and the drain electrode of the other layer. A gate electrode forming step of forming a gate electrode also serving as a mask at the time of implanting an impurity having a structure that becomes thinner in at least one direction of the drain electrode in the direction in which the drain electrode protrudes; The semiconductor layer is implanted with impurity ions, and since there is no mask at all, the source and drain regions with a large amount of impurity ions implanted, And forming a semiconductor layer having an LDD structure including an LDD region in which impurity ions are less implanted because only the portion serves as a mask, and a channel region in which impurity ions are not implanted because the entire thin film layer serves as a mask. A method of manufacturing a semiconductor device, comprising: 11. A semiconductor layer is formed at a predetermined position on a substrate,
A basic forming step for forming a gate insulating film on the formed semiconductor layer; and forming a lower thin film for forming a silicon thin film or a metal thin film as a lower layer of a gate electrode having a multilayer structure on the formed gate insulating film. Forming a metal thin film or a silicon thin film as an upper layer so as to not only completely cover the lower thin film formed above but also have a protrusion in the channel region direction, and to form gate electrodes of different materials in the upper and lower layers Forming a silicide layer at the interface between the two layers by exposing the substrate on which the gate electrode is formed to a predetermined temperature to cause the silicon thin film and the metal thin film to react with each other. Forming a silicide layer, and forming the gate electrode or the silicide layer formed in the gate electrode forming step. Impurity ions are implanted using the gate electrode including the silicide layer formed in the formation step as a mask, and since there is no mask at all, only the source and drain regions with a large amount of implanted impurity ions, A step of forming a semiconductor layer having an LDD structure including an LDD region having a small amount of impurity ions to be implanted as a mask and a channel region in which the upper and lower layers are overlapped and the impurity ions are not implanted because they overlap. A method for manufacturing a semiconductor device, comprising: 12. A gate insulating film partially removing step of temporarily removing the gate insulating film except for a portion located below the gate electrode prior to the implanting step; and after the implanting step is completed, the gate insulating film is temporarily removed. 12. The method for manufacturing a semiconductor device according to claim 10, further comprising: a step of re-forming the gate insulating film in the portion where the gate insulating film is formed. 13. A method for manufacturing a thin-film semiconductor device having a top-gate type LDD structure, which is patterned and arranged on a substrate, comprising: a gate insulating film formed on a patterned semiconductor layer on the substrate; A lower gate electrode forming step of forming a lower gate electrode of a predetermined shape on the upper side, and using the lower gate electrode formed above, the gate electrode is centered at least on one end on the source electrode side and the drain electrode side. An upper gate electrode forming step of forming an upper gate electrode in close contact with the lower gate electrode so as to have a shape having a side part having a poor masking ability at the time of impurity implantation, At least one of the electrode side and the drain electrode side has a side part that has poor masking ability compared to the center part. And a step of implanting impurities into the semiconductor layer. A method of manufacturing a thin film semiconductor element having a top gate type LDD structure, comprising the steps of: 14. A method for manufacturing a thin-film semiconductor device having a top-gate type LDD structure which is patterned and arranged on a substrate, comprising: a gate insulating film formed on a patterned semiconductor layer on the substrate; A lower gate electrode forming step of forming a lower gate electrode of a predetermined shape thereon; an impurity light implanting step of lightly implanting impurities into the semiconductor layer using the formed lower gate electrode as a mask; After the completion, an upper gate electrode is formed by using the lower gate electrode and closely forming an upper gate electrode having a protruding portion on at least one of the source electrode side and the drain electrode side on the upper side thereof. A gate electrode having an upper and lower two-stage structure formed in the lower gate electrode forming step and the upper gate electrode forming step. The use as a mask, the method of manufacturing a thin film semiconductor device of the LDD structure of a top gate type, characterized in that it has an impurity implantation step for implanting impurities into the semiconductor layer. 15. The method according to claim 13, wherein the step of forming the upper gate electrode is a step of forming a plating-use LDD portion mask using a lower gate electrode as one electrode and depositing a predetermined metal by plating. 15. The method for manufacturing a thin film semiconductor device having a top gate type LDD structure according to claim 14. 16. The top gate according to claim 15, wherein the step of forming a mask for an LDD portion using plating is a step of forming a mask for an LDD portion using predetermined plating performed by electroplating or electroless plating as plating. Type LD
A method for manufacturing a thin film semiconductor device having a D structure. 17. An etching step for simultaneously etching an upper gate electrode forming film and a lower gate electrode forming film formed closely above and below in the shape of a lower gate electrode; 14. The method for manufacturing a thin film semiconductor device having a top gate type LDD structure according to claim 13, further comprising: anodizing a small step of anodizing the etched upper gate electrode forming film. 18. The step of forming an upper gate electrode, wherein the lower gate electrode is exposed to a predetermined object to cause a reaction, and at least one of a source electrode side and a drain electrode side is made of a low-density compound generated by the reaction. 15. The method for manufacturing a thin film semiconductor device having a top gate type LDD structure according to claim 13 or 14, wherein the step is a step of forming a mask for a reaction utilizing LDD portion for forming a side portion. 19. A method for manufacturing a thin-film semiconductor device having a top-gate type LDD structure which is patterned and arranged on a substrate, comprising: a gate insulating film formed on a patterned semiconductor layer on the substrate; A lower gate electrode forming step of forming a lower gate electrode having a predetermined shape on the lower gate electrode; and forming a lower gate electrode on the source electrode side of the lower gate electrode by using at least Photsonography and etching. An upper gate electrode forming step of closely forming an upper gate electrode at which at least one end on the drain electrode side protrudes, and at least one of the source electrode side and the drain electrode side Impurity is added to the semiconductor layer by using a gate electrode, which has a side part having a lower masking ability than the center part on the side, as a mask. And a step of implanting impurities. A method of manufacturing a thin film semiconductor element having a top gate type LDD structure, comprising: 20. A method for manufacturing a thin-film semiconductor device having a top gate type LDD structure which is patterned and arranged on a substrate, comprising: a gate insulating film formed on a patterned semiconductor layer on the substrate; A lower gate electrode forming step of forming a lower gate electrode of a predetermined shape thereon; an impurity light implanting step of lightly implanting impurities into the semiconductor layer using the formed lower gate electrode as a mask; After the end, at least one end on the source electrode side and the drain electrode side of the lower gate electrode protrudes by using at least Photsonography and etching on the lower gate electrode. An upper gate electrode forming step of forming electrodes in close contact with each other; the lower gate electrode forming step and an upper gate An impurity implantation step of implanting impurities into the semiconductor layer using the upper and lower two-stage gate electrodes formed as masks in the pole formation step as a mask. A method for manufacturing a thin film semiconductor device. 21. After the upper gate electrode forming step is completed, prior to the impurity implanting step, a gate insulating film removing step of once removing a gate insulating film below a two-stage gate electrode used as a mask; 15. A gate insulating film re-forming step of forming a gate insulating film again on the portion of the semiconductor layer where the gate insulating film has been removed after the impurity implanting step. 21. The method of manufacturing a thin film semiconductor device having a top gate type LDD structure according to claim 19 or 20. 22. After the upper gate electrode forming step is completed, prior to the impurity implanting step, a gate insulating film removing step of once removing a gate insulating film below the two-stage gate electrode used as a mask; 16. The top gate according to claim 15, further comprising, after the impurity implanting step, a gate insulating film re-forming step of forming a gate insulating film again above the semiconductor layer in a portion where the gate insulating film has been removed. Type LDD
A method for manufacturing a thin film semiconductor device having a structure. 23. After the step of removing the gate insulating film,
Forming a hydrogen-adsorbing metal film having a predetermined thickness on the semiconductor layer; forming a hydrogen-adsorbing metal film on the semiconductor after the impurity implanting step and before the gate insulating film re-forming step. A hydrogen-adsorbing metal film removing step of removing the hydrogen-adsorbing metal film while leaving the source electrode portion and the contact electrode portion; and forming the source electrode and the drain electrode on both of the electrode formation portions on the re-formed gate insulating film. 22. The top gate according to claim 21, further comprising: a step of forming a contact hole using a hydrogen-adsorbing metal film using the remaining hydrogen-adsorbing metal film as an etching stopper when forming the contact hole. Of manufacturing a thin-film semiconductor device having an LDD structure. 24. After the impurity implantation step, one side of the upper gate electrode or the lower gate electrode becomes the other electrode by the LDD part mask forming step or the lower gate electrode forming step and the upper electrode forming step. 20. An electrode unnecessary removing step for removing a portion protruding from the source electrode side and the drain electrode side with respect to the source electrode side and the drain electrode side. 21. The method of manufacturing a thin film semiconductor device having a top gate type LDD structure according to claim 20. 25. After the impurity implantation step, one side of the upper gate electrode or the lower gate electrode is connected to the other electrode by the LDD part mask forming step or the lower gate electrode forming step and the upper electrode forming step. 16. The top gate type LDD structure according to claim 15, further comprising an electrode unnecessary removing step for removing a portion protruding from the source electrode side and the drain electrode side. A method for manufacturing a thin film semiconductor device. 26. After the impurity implantation step, one side of the upper gate electrode or the lower gate electrode is connected to the other electrode by the LDD part mask forming step or the lower gate electrode forming step and the chest electrode forming step. 22. The top gate type LDD structure according to claim 21, further comprising an electrode unnecessary removing step of removing a portion protruding from the source electrode side and the drain electrode side. A method for manufacturing a thin film semiconductor device. 27. After the impurity implantation step, one side of the upper gate electrode or the lower gate electrode is connected to the other electrode by the LDD part mask forming step or the lower gate electrode forming step and the chest electrode forming step. 24. The top gate type LDD structure according to claim 23, further comprising an electrode unnecessary removing step for removing a portion protruding from the source electrode side and the drain electrode side. A method for manufacturing a thin film semiconductor device. 28. A method of manufacturing a thin-film semiconductor device having a bottom-gate type LDD structure, which is patterned and arranged on a substrate, the method comprising: forming a predetermined gate electrode patterned on the substrate. A gate insulating film in order on the gate electrode formed above,
An upper element forming layer forming step of forming a patterned semiconductor layer or an interlayer insulating film layer in addition thereto, and directly above the gate electrode of the uppermost layer formed in the upper element forming layer forming step A main mask forming step of forming a main mask, and using the formed main mask, at least one end of the source electrode side and the drain electrode side has poor masking ability at the time of impurity implantation as compared with the central portion. An upper mask forming step of forming side portions in close contact with each other using the upper formed main mask, and using the formed main mask and the upper mask as masks,
A step of implanting impurities into the semiconductor layer from above. A method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure, the method comprising: 29. A method of manufacturing a thin-film semiconductor device having a bottom gate type LDD structure, which is patterned and arranged on a substrate, comprising: forming a predetermined gate electrode patterned on the substrate; A gate insulating film in order on the gate electrode formed above,
An upper element forming layer forming step of forming a patterned semiconductor layer or an interlayer insulating film layer in addition thereto, and directly above the gate electrode of the uppermost layer formed in the upper element forming layer forming step A main mask forming step of forming a main mask, lightly implanting impurities into the semiconductor layer using the formed main mask as a mask, and a main mask formed after the lightly implanted impurity step is completed. An upper mask forming step of forming an upper mask having a protruding portion at least at one end of the source electrode side and the drain electrode side in close contact with the main mask, and the main mask and the upper mask Implanting an impurity into the semiconductor layer using the mask as a mask. Tom gate type LD
A method for manufacturing a thin film semiconductor device having a D structure. 30. The main mask forming step includes: a photosensitive resin layer forming small step of forming a photosensitive resin layer further above the uppermost layer formed in the upper element forming layer forming step; Irradiating a short-wavelength electromagnetic wave with the gate electrode as a mask from the substrate side of the substrate on which the conductive resin layer is formed, a gate electrode corresponding exposure small step of exposing only the photosensitive resin corresponding to the gate electrode, In the gate electrode corresponding exposure small step, use the photosensitive resin of the unexposed portion as it is, regardless of whether it is formed of another material, using the photosensitive resin of the unexposed portion anyway 30. The bottom gate type according to claim 28, further comprising: a main mask forming small step using a photosensitive resin non-exposed portion for forming the main mask. Manufacturing method of a thin film semiconductor device having an LDD structure. 31. The step of forming a main mask, wherein a metal is used as a main mask, and the step of forming an upper mask, wherein the upper mask using plating is a method in which a predetermined metal is adhered by plating using the main mask as one electrode. 30. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 28, wherein the method is a forming step. 32. The step of forming a main mask, wherein a metal is used as a main mask, and the step of forming an upper mask, wherein the upper mask is formed by plating a predetermined metal using the main mask as one electrode. 31. The bottom gate type LD according to claim 30, which is a forming step.
A method for manufacturing a thin film semiconductor device having a D structure. 33. The upper mask forming step, wherein the main mask is exposed to a predetermined object to cause a reaction, and at least one of a source electrode side and a drain electrode side is formed of a side portion made of a low-density compound generated by the reaction. 3. A reaction utilizing upper mask forming step for forming a mask.
30. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 8 or 29. 34. In the main mask forming step, in the upper mask forming step, the main mask is exposed to a predetermined object to cause a reaction, and at least one of a source electrode side and a drain electrode side has a density generated by the reaction. 31. The method as claimed in claim 30, further comprising a step of forming a reaction-based upper mask for forming a side portion made of a low compound. 35. A method for manufacturing a thin-film semiconductor device having a bottom gate type LDD structure which is patterned and arranged on a substrate, comprising: forming a predetermined gate electrode patterned on the substrate; A gate insulating film in order on the gate electrode formed above,
An upper element forming layer forming step of forming a patterned semiconductor layer or an interlayer insulating film layer in addition thereto, and directly above the gate electrode of the uppermost layer formed in the upper element forming layer forming step A main mask forming step of forming a main mask, and using the formed main mask, at least one end of the source electrode side and the drain electrode side has poor masking ability at the time of impurity implantation as compared with the central portion. Forming an upper mask having side portions by at least a method using Photsonography and etching; and using the formed main mask and upper mask as masks,
A step of implanting impurities into the semiconductor layer from above. A method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure, the method comprising: 36. A method for manufacturing a thin-film semiconductor device having a bottom gate type LDD structure, which is patterned and arranged on a substrate, comprising the steps of: forming a predetermined gate electrode patterned on the substrate; A gate insulating film in order on the gate electrode formed above,
An upper element forming layer forming step of forming a patterned semiconductor layer or an interlayer insulating film layer in addition thereto, and directly above the gate electrode of the uppermost layer formed in the upper element forming layer forming step A main mask forming step of forming a main mask, an impurity light implantation step of lightly implanting impurities into the semiconductor layer using the formed main mask as a mask, and after the impurity light implantation step is completed, the formed main mask An upper mask forming step of forming at least an upper mask having a protruding portion on at least one end on the source electrode side and the drain electrode side of the main mask by a method using Photsonography and etching; An impurity implantation step for implanting impurities into the semiconductor layer using the main mask and the upper mask as masks. Characterized by having a tip and a bottom gate type LD
A method for manufacturing a thin film semiconductor device having a D structure. 37. The step of forming a main mask, the step of forming a photosensitive resin layer further above the uppermost layer formed in the step of forming the upper element constituent layer, the step of forming a photosensitive resin layer further comprising: Irradiating visible light or an electromagnetic wave of a shorter wavelength from the substrate side of the substrate on which the conductive resin layer is formed with the gate electrode as a mask, and exposing only the photosensitive resin corresponding to the gate electrode to a portion corresponding to the gate electrode; Step, In the gate electrode corresponding exposure small step, regardless of whether the photosensitive resin of the unexposed portion is used as it is or formed of another material, the photosensitive resin of the unexposed portion anyway 37. The method according to claim 35, further comprising the step of: forming a main mask using a photosensitive resin non-exposed portion for forming the main mask by using the main mask. A method for manufacturing a thin film semiconductor device having a tomgate type LDD structure. 38. The impurity implanting step is a bare semiconductor layer impurity implanting step in which an impurity is implanted in a state where no interlayer insulating film exists on the upper surface of the semiconductor layer. 31. An interlayer insulating film re-forming step of forming an interlayer insulating film on the semiconductor layer after removing the LDD portion mask. 37. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 31, claim 32, claim 33, claim 34, claim 35 or claim 36. 39. The impurity implanting step is a bare semiconductor layer impurity implanting step in which an impurity is implanted in a state where no interlayer insulating film is present on the upper surface of the semiconductor layer. 31. A thin film semiconductor having a bottom gate type LDD structure according to claim 30, further comprising a step of forming an interlayer insulating film on the semiconductor layer after removing the LDD portion mask. Device manufacturing method. 40. The impurity implanting step is a bare semiconductor layer impurity implanting step in which an impurity is implanted in a state where no interlayer insulating film exists on the upper surface of the semiconductor layer. 32. A thin film semiconductor having a bottom gate type LDD structure according to claim 31, further comprising a step of re-forming an interlayer insulating film above the semiconductor layer after removing the LDD portion mask. Device manufacturing method. 41. A hydrogen-adsorbing metal film forming step of forming a hydrogen-adsorbing metal film having a predetermined thickness on a semiconductor layer after the upper element layer forming step and before the impurity implanting step, Then, prior to the interlayer insulating film re-forming step, a hydrogen-adsorbing metal film removing step of removing the hydrogen-adsorbing metal film formed on the semiconductor while leaving a source electrode portion and a contact electrode portion, a source electrode and a drain When forming contact holes in both electrode forming portions on the re-formed interlayer insulating film for forming electrodes, use the remaining hydrogen-adsorbing metal film as an etching stopper to form a contact hole using a hydrogen-adsorbing metal film. 39. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 38, comprising: . 42. After the upper element layer forming step and before the impurity implanting step, a hydrogen absorbing metal film forming step of forming a hydrogen absorbing metal film having a predetermined thickness on the semiconductor; Prior to the step of re-forming the interlayer insulating film, a step of removing the hydrogen-adsorbing metal film formed on the semiconductor while leaving the source electrode portion and the contact electrode portion, and forming a source electrode and a drain electrode. Therefore, when forming contact holes in both electrode formation portions on the re-formed interlayer insulating film, a hydrogen-adsorbing metal film utilizing contact hole forming step using the remaining hydrogen-adsorbing metal film as an etching stopper. 40. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 39, wherein: 43. After the upper element layer forming step and before the impurity implanting step, a hydrogen absorbing metal film forming step of forming a hydrogen absorbing metal film of a predetermined thickness on a semiconductor; Prior to the step of re-forming the interlayer insulating film, a step of removing the hydrogen-adsorbing metal film formed on the semiconductor while leaving the source electrode portion and the contact electrode portion, and forming a source electrode and a drain electrode. Therefore, when forming contact holes in both electrode formation portions on the re-formed interlayer insulating film, a hydrogen-adsorbing metal film utilizing contact hole forming step using the remaining hydrogen-adsorbing metal film as an etching stopper. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 40, comprising: 44. A semiconductor device having a top gate type LDD structure which is patterned and arranged on a substrate, wherein an upper gate electrode and at least one side on a source electrode side and a drain electrode side are formed on the upper gate. A lower gate electrode protruding from the electrode and formed in close contact with the upper gate electrode; a channel region immediately below the upper gate electrode and the lower electrode; and an LDD region immediately below the protruding portion of the lower electrode. A semiconductor device having a top gate type LDD structure, comprising: a semiconductor portion having a source region and a drain region which are not covered by the upper gate electrode and the lower electrode. 45. A semiconductor device having a top gate type LDD structure, which is patterned and arranged on a substrate, wherein a lower gate electrode and at least one side on a source electrode side or a drain electrode side are provided with the lower gate. An upper gate electrode protruding from the electrode and formed in close contact with the upper gate electrode; a channel region immediately below the upper gate electrode and the lower electrode; and an LDD region immediately below the protruding portion of the upper electrode. A semiconductor device having a top gate type LDD structure, comprising: a semiconductor portion having a source region and a drain region which are not covered by the upper gate electrode and the lower electrode. 46. The top gate type LDD structure according to claim 45, wherein the upper gate electrode is a plated upper gate electrode formed by plating a metal on an outer surface of the lower gate electrode. Semiconductor element. 47. The source electrode and the drain electrode each having a silicide layer at a contact portion with the semiconductor layer, and a silicide-forming metal layer on the silicide layer. 47. A semiconductor device having a top gate type LDD structure according to claim 45 or 46. 48. The gate insulating layer according to claim 44, wherein the gate insulating layer is formed immediately below the upper and lower gate electrodes, or in addition to the gate electrode, and in the vicinity thereof and at a different time. , Claim 4
47. A semiconductor device having a top gate type LDD structure according to claim 5 or 46. 49. The gate insulating layer according to claim 48, wherein the gate insulating layer is formed at a different timing immediately under the upper and lower gate electrodes or in the vicinity thereof and other portions. A semiconductor element having a top gate type LDD structure as described in the above. 50. One of the upper gate electrode and the lower gate electrode is made of a low-resistance metal material such as Cu, Al, Ag, Au or the like. The other lower gate electrode or the gate electrode is made of a high-density metal material having a density of 8 or more such as W, Mo, Co, Ta, Au, Nb, and Ag, or a material such as Zr, Ti, or a Ti-based metal. 47. A top gate type electrode according to claim 44, wherein the high mask electrode has a high masking ability for hydrogen ions implanted at the time of impurity implantation since the hydrogen absorbing metal is used. LD
D-shaped semiconductor element. 51. One of the upper gate electrode and the lower gate electrode is made of a low-resistance metal material such as Cu, Al, Ag, Au or the like. The other lower gate electrode or the gate electrode is made of a high-density metal material having a density of 8 or more such as W, Mo, Co, Ta, Au, Nb, and Ag, or a material such as Zr, Ti, or a Ti-based metal. 48. The semiconductor device having a top gate type LDD structure according to claim 47, wherein the high gate electrode has a high masking ability for a hydrogen ion implanted at the time of impurity implantation since the hydrogen absorbing metal is used. 52. One of the upper gate electrode and the lower gate electrode is made of a low-resistance metal material such as Cu, Al, Ag, Au or the like. The other lower gate electrode or the gate electrode is made of a high-density metal material having a density of 8 or more such as W, Mo, Co, Ta, Au, Nb, and Ag, or a material such as Zr, Ti, or a Ti-based metal. 49. The top gate type LDD semiconductor device according to claim 48, wherein the high gate electrode has a high masking ability for masking hydrogen ions implanted at the time of impurity implantation because the hydrogen absorbing metal is used. 53. One of the upper gate electrode and the lower gate electrode is made of a low-resistance metal material such as Cu, Al, Ag, Au or the like. The other lower gate electrode or the gate electrode is made of a high-density metal material having a density of 8 or more such as W, Mo, Co, Ta, Au, Nb, and Ag, or a material such as Zr, Ti, or a Ti-based metal. 50. The semiconductor device having a top gate type LDD structure according to claim 49, wherein the high gate electrode has a high masking ability for hydrogen ions implanted at the time of impurity implantation because the hydrogen absorbing metal is used. 54. The substrate is a TFT array substrate of a liquid crystal display device, and one of the lower gate electrode and the upper gate electrode is formed of the transparent conductive film because it is formed in the same step as the transparent conductive film of the pixel portion. 44 and 45.
47. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 46. 55. The substrate is a TFT array substrate of a liquid crystal display device, and one of the lower gate electrode and the upper gate electrode is made of a transparent conductive film because it is formed in the same step as the transparent conductive film of the pixel portion. 48. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 47. 56. The substrate is a TFT array substrate of a liquid crystal display device, and one of the lower gate electrode and the upper gate electrode is made of a transparent conductive film because it is formed in the same step as the transparent conductive film of the pixel portion. 49. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 48. 57. The substrate is a TFT array substrate of a liquid crystal display device, and one of the lower gate electrode and the upper gate electrode is formed of the transparent conductive film because it is formed in the same step as the transparent conductive film of the pixel portion. 50. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 49. 58. The substrate is a TFT array substrate of a reflection type liquid crystal display device, and one of the lower gate electrode and the upper gate electrode is formed in the same step as the reflection film of the pixel portion, so that a good reflection metal film is formed. 44. The device according to claim 44, wherein
47. The method of manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 5 or 46. 59. The substrate is a TFT array substrate of a reflection type liquid crystal display device, and one of the lower gate electrode and the upper gate electrode is formed in the same step as the reflection film of the pixel portion, so that a good reflection metal film is formed. 48. The method according to claim 47, wherein the thin-film semiconductor device has a bottom-gate LDD structure. 60. The above-mentioned substrate is a TFT array substrate of a reflection type liquid crystal display device, and one of the lower gate electrode and the upper gate electrode is formed in the same step as the reflection film of the pixel portion, so that a good reflective metal film is formed. The method for manufacturing a thin film semiconductor device having a bottom gate type LDD structure according to claim 50, wherein the semiconductor device is manufactured. 61. A patterned arrangement on a substrate,
A top-gate semiconductor element including a gate electrode including an upper gate electrode and a lower gate electrode which are formed closely above and below a gate insulating film, and one of the upper gate electrode and the lower gate electrode is, for example, Since a low-resistance metal material such as Cu, Al, Ag, or Au is used, the low-resistance electrode has an electric resistivity of 5 Ω · cm or less. The other lower gate electrode or the gate electrode is, for example, W , Mo, Co, Ta, Au, Nb, Ag, etc., because a high-density metal material having a density of 8 or more or a hydrogen-adsorbing metal such as Zr, Ti, or a Ti-based metal is used, hydrogen ions are implanted when impurities are implanted. A top gate type semiconductor device characterized by a high mask electrode having a high masking ability. 62. The top electrode according to claim 61, wherein the source electrode and the drain electrode have a silicide layer at a contact portion with the semiconductor layer, and a silicide forming metal layer on the silicide layer. Gate type semiconductor element. 63. The gate insulating layer is formed at different times immediately under the upper and lower gate electrodes or in addition to the vicinity thereof and other portions. 63. A top gate type semiconductor device according to claim 61 or 62. 64. Patterned arrangement on a substrate,
A top-gate type semiconductor device having an LDD structure having a gate electrode including an upper gate electrode and a lower gate electrode which are formed closely above and below a gate insulating film, wherein one of the upper gate electrode and the lower gate electrode is provided. Is a low-resistance electrode having an electric resistivity of 5 Ω · cm or less, for example, because a low-resistance metal material such as Cu, Al, Ag, or Au is used. The other lower gate electrode or the gate electrode is Since a high-density metal material having a density of 8 or more, such as W, Mo, Co, Ta, Au, Nb, and Ag, or a hydrogen-adsorbing metal such as Zr, Ti, or a Ti-based metal is used, it is implanted at the time of impurity implantation. A top gate type LDD structure semiconductor device, which is a high mask electrode having a high masking ability for hydrogen ions. 65. The top electrode according to claim 64, wherein the source electrode and the drain electrode have a silicide layer at a contact portion with the semiconductor layer, and a silicide-forming metal layer on the silicide layer. A semiconductor element having a gate type LDD structure. 66. The gate insulating layer is formed at different times immediately under or in addition to the upper and lower gate electrodes or in the vicinity thereof and other portions. 64. A semiconductor device having a top gate type LDD structure according to claim 64 or claim 65. 67. Since a characteristic required for an LDD type TFT differs depending on a position on a substrate, such as a substrate in which a pixel portion and a peripheral drive circuit portion are integrally formed, an LDD type TFT according to the required characteristic is provided. In order to equip the TFT, a part of the substrate has an upper gate electrode and at least one of the source electrode side and the drain electrode side protrudes from the upper gate electrode and is in close contact with the upper gate electrode. Or, conversely, the lower gate electrode and at least one of the source electrode side and the drain electrode side protrude from the lower gate electrode, and the upper gate electrode A two-stage structure gate electrode comprising an upper gate electrode formed in close contact with a channel region, a channel region immediately below the upper gate electrode and the lower electrode, and immediately below a protrusion of the upper electrode or the lower electrode. An LDD region and a semiconductor portion having a source region and a drain region that are not covered by the upper gate electrode and the lower electrode; and another region or another partial region on the substrate includes an upper gate electrode and the upper gate electrode. A lower gate electrode formed in close contact with the gate electrode, and both upper and lower gate electrodes are formed of a two-stage columnar gate electrode having no protruding portion, or an impurity formed of a single gate electrode. A gate electrode also serving as a complete mask during implantation, a channel region directly below the gate electrode also serving as a complete mask during impurity implantation, an LDD region on at least one side of the source and drain electrodes of the channel region, and both regions. A substrate having a semiconductor portion having source and drain regions at both ends. 68. The substrate is a TFT array substrate for a liquid crystal display device, and the LDD type TFT formed in the pixel portion has one of the upper gate electrode and the lower gate electrode made of, for example, Cu, Al, Ag , Au, etc., is a low-resistance electrode having an electric resistivity of 5 Ω · cm or less because of using a low-resistance metal material or the like. The other lower gate electrode or the gate electrode is, for example, W, Mo, Co, Since a high-density metal material having a density of 8 or more, such as Ta, Au, Nb, and Ag, or Zr, Ti, or a Ti-based metal having a strong bonding force with hydrogen is used, the masking ability of hydrogen ions implanted during impurity implantation is reduced. 68. The substrate according to claim 67, wherein the substrate is a high high mask electrode. 69. A bottom-gate semiconductor having a gate electrode having a silicide or a multilayer structure having a silicide layer. 70. A method for manufacturing a thin-film semiconductor device having a top-gate type LDD structure which is patterned and arranged on a substrate, comprising: a gate insulating film formed on a patterned semiconductor layer on the substrate; A gate electrode forming step of forming a gate electrode of a predetermined shape thereon; and using the formed gate electrode, at least one end on the source electrode side and the drain electrode side thereof with an etching mask when removing the gate insulating film. An etching mask forming step of forming a side portion in close contact with the gate electrode, and once removing the gate insulating film except the portion immediately below the formed gate electrode and the side portion etching mask as an etching mask. Removing the gate insulating film; and removing the gate electrode and the gate insulating film existing thereunder or the gate electrode in addition thereto. A top-gate type LDD structure characterized by performing an implantation step of implanting impurities using an etching mask on the side of the electrode as a mask, and a gate insulation film regeneration step of re-forming the gate insulation film in the removed portion. A method for manufacturing a thin film semiconductor device. 71. A top gate type LDD according to claim 70, wherein said etching mask forming step is a plating utilizing etching mask forming step of depositing a predetermined metal by plating using a gate electrode as one electrode. A method for manufacturing a thin film semiconductor device having a structure.