JP2001210833A - Semiconductor device and method of manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device. SOLUTION: This highly reliable semiconductor device is constituted in such a way that metallic films are caused to be deposited on the side face and top face of gate wiring by electroplating in a GOLD structure in which the metallic films are superposed upon an LDD area through a gate insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of a thin film transistor (hereinafter, referred to as a TFT) on a substrate having an insulating surface and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display device, an electric appliance (also referred to as an electronic device) equipped with the electro-optical device, and a manufacturing method thereof. Note that in this specification, a semiconductor device generally means a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electric appliance on which the electro-optical device is mounted.

[0002]

2. Description of the Related Art Recently, a TFT using a polysilicon film has been developed.
An active matrix type liquid crystal display device in which a circuit is constituted by (hereinafter, referred to as a crystalline TFT) has attracted attention. This realizes a high-definition image display device by controlling an electric field applied to liquid crystal in a matrix by a plurality of pixels arranged in a matrix.

[0003] In many cases, an n-channel TFT is formed in a pixel portion of an active matrix liquid crystal display device (hereinafter, a TFT formed in a pixel portion is referred to as a pixel TFT). Since a gate voltage having an amplitude of about 15 to 20 V is applied to the pixel TFT, it is necessary to satisfy the characteristics of both the ON region and the OFF region. On the other hand, a peripheral circuit provided for driving the pixel portion is configured based on a CMOS circuit, and the characteristics of the ON region are mainly important. But,
The crystalline TFT has a problem that the off-current tends to increase. In addition, when the crystalline TFT was driven for a long period of time, deterioration phenomena such as a decrease in mobility and on-current and an increase in off-current were often observed. One of the causes was considered to be a hot carrier injection phenomenon caused by a high electric field near the drain.

In the technical field of LSI, as a method of reducing the off-state current of a MOS transistor and relaxing a high electric field near the drain, a lightly doped drain (LDD) is used.
pedDrain) structures are known. In this structure, a low-concentration impurity region is provided between a drain region and a channel formation region, and this low-concentration impurity region is called an LDD region.

[0005] Similarly, it has been known that a crystalline TFT also forms an LDD structure. According to the conventional technique, the gate electrode is used as a mask to perform L
A low-concentration impurity region serving as a DD region is formed in advance, and then sidewalls are formed on both sides of the gate electrode using anisotropic etching technology, and the second impurity element is formed using the gate electrode and the sidewall as a mask. This is a method of forming a high-concentration impurity region to be a source region and a drain region by an adding step.

[0006]

However, although the LDD structure can reduce the off current as compared with the TFT having the normal structure, the series resistance component increases structurally.
As a result, there is a disadvantage that the on-current of the TFT is also reduced. Further, deterioration of the on-state current could not be completely prevented.

An object of the present invention is to provide a technique for overcoming such a problem, and to provide a TFT having a structure in which a gate electrode and an LDD region are overlapped. To achieve that goal, in a simple way,
T with a structure in which the gate electrode overlaps the LDD region
It is intended to provide a technique for manufacturing an FT.
It is another object of the present invention to provide a semiconductor device in which a circuit is formed using highly reliable TFTs.

[0008]

According to the structure of the invention disclosed in this specification, a gate wiring is provided on a gate insulating film, and a metal film having the same thickness is provided on the side and upper surfaces of the gate wiring. A semiconductor device having a TFT.

According to another aspect of the present invention, there is provided a TFT having a gate wiring on a gate insulating film, and a metal film deposited on a side surface and an upper surface of the gate wiring by an electrolytic plating method. A semiconductor device characterized by the following.

Another embodiment of the present invention has an n-channel type T
In a semiconductor device having a CMOS circuit formed by an FT and a p-channel TFT, the n-channel TF
T and the p-channel TFT have a gate wiring on a gate insulating film, and the gate wiring has a metal film on a side surface and an upper surface.

Another embodiment of the present invention provides an n-channel type T
In a semiconductor device including a CMOS circuit formed by an FT and a p-channel TFT, the n-channel TFT
And a gate insulating film on each active layer of the p-channel TFT, a gate wiring on the gate insulating film,
A metal film covering side and top surfaces of the gate wiring, wherein an active layer of the n-channel TFT includes a channel formation region, a first impurity region in contact with the channel formation region,
A second impurity region in contact with the first impurity region;
A third impurity region in contact with the impurity region, wherein the gate wiring is formed so as to overlap with the channel formation region, and a width of the first impurity region is equal to a thickness of a metal film formed on a side surface of the gate wiring; The semiconductor device is characterized by being determined by the following.

Another embodiment of the invention has an n-channel type T
In a semiconductor device including a CMOS circuit formed of an FT and a p-channel type TFT, a gate insulating film on an active layer, a gate wiring on the gate insulating film, and a metal film covering side and top surfaces of the gate wiring Wherein the active layer of the n-channel TFT includes a channel forming region, a first impurity region in contact with the channel forming region, a second impurity region in contact with the first impurity region, and the second impurity region. A third impurity region in contact with the semiconductor substrate, and the length of the channel formation region, the width of the gate wiring, the length of the first impurity region, and the film thickness of the metal film match via the gate insulating film. In the third impurity region, the catalyst element used for crystallization of the active layer is 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms /.
A semiconductor device characterized by being present at a concentration of cm ³ .

In another aspect of the invention, a step of crystallizing a semiconductor layer formed on a substrate having an insulating surface to form an active layer, a step of forming a gate insulating film on the active layer, Forming a gate wiring on the gate insulating film, adding an impurity using the gate wiring as a mask to form a first impurity region, and forming a metal film on a side surface and an upper portion of the gate wiring by electrolytic plating. Forming, adding impurities using the metal film as a mask to form a fourth impurity region in the p-channel thin film transistor, and adding impurities using the metal film as a mask to form a second impurity region. And a step of adding a impurity to a selected portion of the active layer to form a third impurity region.

According to another aspect of the invention, a step of adding a catalytic element to a semiconductor layer formed on a substrate having an insulating surface, a step of heat-treating and crystallizing the semiconductor layer to form an active layer. Forming a gate insulating film on the active layer, forming a gate wiring on the gate insulating film, adding impurities using the gate wiring as a mask to form a first impurity region, Forming a metal film on a side surface and an upper portion of the gate wiring by an electrolytic plating method, forming an impurity by adding an impurity using the metal film as a mask to form a fourth impurity region in the p-channel thin film transistor; Forming a second impurity region by adding an impurity as a mask; and forming a third impurity region by adding an impurity to a selected portion of the active layer. A semiconductor device manufacturing method of.

[0015]

[Embodiment 1] In this embodiment, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

First, as the substrate 301, a glass substrate typified by, for example, a 1737 glass substrate manufactured by Corning Incorporated was used. Then, a 200 nm-thick base film 302 made of a silicon oxide film was formed on the surface of the substrate 301 on the side where the TFT was formed. As the base film 302, a silicon nitride film may be deposited, or only a silicon oxynitride film may be used. As a method for forming the base film, a plasma CVD method, a thermal CVD method, or a sputtering method may be used.

Next, an amorphous silicon film having a thickness of 30 nm was formed on the base film 302 by a plasma CVD method. The method for forming the amorphous silicon film may be a thermal CVD method or a sputtering method. After the amorphous silicon film was dehydrogenated, a crystallization step was performed to form a polycrystalline silicon film.

In this crystallization step, a known laser crystallization technique or thermal crystallization technique may be used. In this example, a pulsed KrF excimer laser beam was condensed linearly and irradiated on the amorphous silicon film to form a crystalline silicon film.

In this embodiment, the initial film is used as an amorphous silicon film. However, a microcrystalline silicon film may be used as the initial film, or a crystalline silicon film may be directly formed.

The crystalline silicon film thus formed is patterned to form an active layer 30 made of an island-shaped silicon layer.
3, 304 were formed.

After the crystalline silicon film is formed, the crystallinity may be increased by irradiating an excimer laser beam. Alternatively, it may be performed after forming the active layers 303 and 304.

Next, a gate insulating film 305 made of a silicon oxide film having a thickness of 100 nm was formed to cover the active layers 303 and 304. Subsequently, the gate wiring 30 having a laminated structure of tantalum and tantalum nitride is formed on the gate insulating film 305.
6, 307 were formed. Although another metal can be used for the gate wiring 306, a material having a high etching selectivity with respect to silicon is preferable in consideration of a later process. (Figure 2
(A))

A resist mask 308 was formed on the gate insulating film 305 so as to cover the entire region to be a p-channel thin film transistor (hereinafter, PTFT).

In this state, a first step of adding phosphorus was performed. Here, the acceleration voltage was set to 80 KeV in order to add impurities through the gate insulating film. The first impurity region 309 thus formed has a phosphorus concentration of 1 × 1
0 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ (preferably 3 × 10 ¹⁷ to
The dose was adjusted to be 3 × 10 ¹⁸ atoms / cm ³ ). The phosphorus concentration at this time is represented by (n ⁻ ). The first impurity region was formed in a self-aligned manner using the gate wiring 306 as a mask. The first impurity region 309 is an LD
It will function as the D region. (FIG. 2 (B))

Next, in the present embodiment, CuSO ₄ .5H ₂ O
Copper (Cu) was deposited on the side and top surfaces of the conductive layer by 0.1 to 1 μm (preferably 0.2 to 0.5 μm) by a known electrolytic plating method using an electrolytic solution. (Fig. 2 (C))

As shown in FIG. 1, the electroplating method is performed by immersing two electrodes in an electrolyte solution 103 and passing an electric current from the outside to cause an electrochemical change on both electrode surfaces. Therefore, the cathode electrode 101 (the electrode on the side where the metal is deposited) from which the + ions in the liquid are discharged is used as the gate wiring, and the anode electrode 102 where the-ions are discharged or the metal dissolves to become metal ions is formed of Cu. If it is formed of an electrode and a current flows through a contact pad, a metal film made of Cu can be deposited on the side wall and upper portion of the gate wiring.

The electroplating method is a phenomenon in which metal ions are reduced and precipitated at a cathode electrode. Since the amount of electrode reaction is proportional to the amount of electricity, the thickness of the deposited metal film can be easily adjusted. It is also easy to make the thicknesses of the metal films deposited on the side and top surfaces of the gate electrode equal.

After forming the metal films 311, 312, NT
A resist mask 313 was formed so as to cover the entire FT.

In this state, a step of adding boron was performed. Here, the acceleration voltage is set to 10 KeV, and the fourth impurity region 314 is formed. Boron is 3 × 10 ^{20 to} 3 × 10
²¹ atoms / cm ³ (preferably 5 × 10 ²⁰ to 1 × 10 ²¹ atoms
/ cm ³ ). The boron concentration at this time is represented by (p ⁺⁺ ). Also,
A channel forming region 315 of the PTFT is defined. (Figure 2
(D))

Next, a resist mask 316 was formed so as to cover the entire PTFT.

In this state, a second step of adding phosphorus was performed. Also in this case, the applied voltage was set to 80 KeV.
In the second impurity doping (phosphorus doping) step, the metal layer 3
11 is used as a doping mask to form a second impurity region 317 in a self-aligned manner, and that phosphorus is 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms.
s / cm ³ (preferably 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ )
The dose was adjusted so as to be included at a concentration of. The phosphorus concentration at this time is represented by (n). Second impurity region 3
Reference numeral 17 functions as an LDD region. (Figure 2
(E))

Next, the subsequent n-channel TFT (hereinafter referred to as NT
Notated as FT. ), And a resist mask 319 covering the entire PTFT.
Was formed.

In this state, a third step of adding phosphorus was performed to form a third impurity region 320. Here, the acceleration voltage is set to 10 KeV, and phosphorus in the third impurity region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (preferably, 2 × 1
The dose was adjusted so as to be included at a concentration of 0 ^{20 to} 5 × 10 ²¹ atoms / cm ³ ). The concentration of phosphorus at this time is represented by (n ⁺ ). The third impurity region 320 functions as a source region or a drain region. (FIG. 3 (A))

The resist masks 318 and 319 are removed,
A protective film 321 was formed to cover the entire region to be the later NTFT and the whole region to be the later PTFT. At this time, the silicon nitride film provided as a protective film includes gate wirings (tantalum films) 306 and 307 and metal films (copper films) 311 and 31.
2 is prevented from being oxidized. As the protective film, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used, and the thickness range is 1 to 30 nm, preferably 5 to 20 nm. (FIG. 3 (B))

Since the PTFT is originally high in reliability, it may be more convenient to provide an ON current without providing an LDD region without any problem. Therefore, in this embodiment, the LDD region is also offset with respect to the PTFT. No regions were formed.

Thus, finally, a channel forming region, a first impurity region, a second impurity region, and a third impurity region are formed in the active layer of the _NTFT , and L _ov = 0.5
３3.0 μm (1.0-1.5 μm), L _off = 0.5-
The width was 3.0 μm (1.0 to 2.0 μm). PT
Only the channel formation region and the fourth impurity region were formed in the FT active layer.

A metal film was formed on the side and top surfaces of the gate wiring by electrolytic plating, and an impurity was added using this metal film as a mask, whereby an LDD region could be formed in a self-aligned manner. By changing the thickness of the metal film, the length (width) of the LDD region can be changed.

[Embodiment 2] The TFT manufactured in Embodiment 1 (FIG. 3B) is used as a driver circuit, and the NTFT manufactured by the method shown in Embodiment 1 is applied to the pixel TFT on the active matrix substrate (FIG. 3B). Note that the structure of a storage capacitor connected to a TFT in a pixel portion of an active matrix liquid crystal display device employing a multi-gate structure will be described with reference to FIG.

The first interlayer insulating film 322 was formed to a thickness of 1 μm. In this embodiment, an acrylic resin film is employed. First
After forming the interlayer insulating film 322, the source wirings 323, 324, 325 and the drain wiring 32 made of a metal material are formed.
6, 327 were formed. In this embodiment, a three-layer wiring having a structure in which an aluminum film containing titanium is sandwiched between titanium is used.

After forming the source wiring and the drain wiring in this manner, a 50-nm-thick silicon nitride film 328 was formed as a first interlayer insulating film. A second interlayer insulating film 3 is formed thereon.
29 was formed. As the second interlayer insulating film 329, 5
A structure in which an organic resin film was stacked on a silicon oxide film having a thickness of 0 nm was employed. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film forming method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

Next, a light shielding layer 330 was formed on a part of the pixel region on the second interlayer insulating film 329. The light-blocking layer 330 may be formed using a metal material such as aluminum, titanium, or tantalum, a film containing any of these metals as a main component, or an organic resin film. Here, titanium was formed by a sputtering method.

After forming the light shielding film, the third interlayer insulating film 3
31 are formed. The third interlayer insulating film 331 may be formed using an organic resin film, similarly to the second interlayer insulating film 329. Then, a contact hole reaching the drain electrode 327 was formed in the second interlayer insulating film 329 and the third interlayer insulating film 331, and a pixel electrode 332 was formed. Pixel electrode 3
Reference numeral 32 may be a transparent conductive film for a transmissive liquid crystal display device, or a metal film for a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm.
The pixel electrode 332 was formed to a thickness of m by a sputtering method.

After the state shown in FIG. 4A is formed, an alignment film 333 is formed. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. Opposite substrate 33
6 includes a transparent conductive film (pixel electrode) 335 and an alignment film 33.
4 was formed. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were parallel-aligned with a certain pretilt angle.

After the above steps, the pixel matrix circuit, the substrate on which the CMOS circuit is formed, and the counter substrate are bonded together by a known cell assembling process via a sealing material or a spacer (both not shown). Thereafter, a liquid crystal material 337 was injected between the two substrates, and completely sealed with a sealing material (not shown). Thus, an active matrix liquid crystal display device shown in FIG. 4B was completed.

According to this embodiment, a metal film is formed on the side and top surfaces of the gate wiring, and the completed CMOS circuit has
Since the TFT has excellent reliability, the reliability as a whole circuit is greatly improved. In addition, it was found that the structure as in the present embodiment improves the characteristic balance between the NTFT and the PTFT, so that an operation failure is less likely to occur.

Example 3 In the manufacturing method of Example 1,
After the step shown in FIG. 2A is completed, resist masks 403 and 404 covering the entire PTFT and the entire pixel portion are provided.
Was formed, and the first step of adding phosphorus was performed. As a result, in the NTFT of the drive circuit section, the gate wiring 30
6 as a mask, the first impurity region 30 is self-aligned.
9. The channel formation region 310 is formed. (FIG. 5
(A))

Next, the gate wiring 3 is formed by electrolytic plating.
Metal films 311, 312, 406, 407 were formed on the side surfaces and upper portions of 11, 312, 401, 402. (FIG. 5
(B))

The subsequent steps were performed in accordance with Example 2, and an active matrix type liquid crystal display device as shown in FIG. 7B was completed.

Fourth Embodiment In the first embodiment, the gate wiring 30
Although a stack of tantalum and tantalum nitride was used as 6 and 307, and copper was used as the metal films 311 and 312, in this embodiment,
A low-resistance metal such as Al,
As a material mainly composed of a metal such as W, Mo, Cu, Au, and Nb, and as a material of a high melting point metal as a metal film,
For example, it is formed using a material mainly containing a metal such as Ta, Mo, and W. If the high melting point metal is formed on the side surface and the upper portion of the gate wiring as in the present embodiment, there is an advantage that the high melting point metal can be thermally activated at a high temperature to protect the gate wiring. This embodiment is similar to the first to third embodiments.
Can be used in combination.

Fifth Embodiment In the first embodiment, the gate wiring 30
Although a stack of tantalum and tantalum nitride was used as 6 and 307, and copper was used as the metal films 311 and 312, in this embodiment,
High melting point metal as a material for gate wiring and metal film, for example,
It was formed using a material mainly containing Ta, W, Mo, Cr, Ni, Zn, or the like. Since both the gate wiring and the metal film are refractory metals, they can be thermally activated at high temperatures,
Further, by making the two metals the same, it is possible to make it difficult for the metals to peel off. This embodiment is similar to the first embodiment.
3 can be used in combination.

[Embodiment 6] This embodiment shows an example in which a crystalline semiconductor film used as a semiconductor layer in Embodiment 1 is formed by a thermal crystallization method using a catalytic element. When a catalyst element is used, it is desirable to use the technology disclosed in JP-A-7-130652 and JP-A-8-78329.

FIG. 8 shows an example in which the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 is applied to the present invention.
Shown in First, a silicon oxide film 602 was provided over a substrate 601, and an amorphous silicon film 603 was formed thereon. Further, a nickel acetate solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 604.
(FIG. 8A)

Next, after the dehydrogenation step at 500 ° C. for 1 hour, the temperature is set at 500 to 650 ° C. for 4 to 12 hours (in this embodiment, 5 to 12 hours).
Heat treatment (50 ° C., 14 hours) was performed to form a crystalline silicon film 605. The crystalline silicon film 605 thus obtained has very excellent crystallinity. (FIG. 8 (B))

The technique disclosed in Japanese Patent Application Laid-Open No. 8-78329 allows selective crystallization of an amorphous semiconductor film by selectively adding a catalyst element. FIG. 9 shows a case where the same technology is applied to the present invention.
Will be described.

First, a silicon oxide film 70 is formed on a glass substrate 701.
2, and an amorphous silicon film 703 and a silicon oxide film 704 were continuously formed thereon.

Next, the silicon oxide film 704 was patterned to selectively form openings 705, and then a nickel acetate solution containing 10 ppm by weight of nickel was applied. Thus, a nickel-containing layer 706 was formed, and the nickel-containing layer 706 was in contact with only the amorphous silicon film 702 exposed from the opening 705. (FIG. 9
(A))

Next, heat treatment is performed at 500 to 650 ° C. for 4 to 24 hours (in this embodiment, 580 ° C., 14 hours).
A crystalline silicon film 707 was formed. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally from there. The crystalline silicon film 707 thus formed is made up of a collection of rod-shaped or needle-shaped crystals, each of which is macroscopically grown in a specific direction, and therefore has a uniform crystallinity. There are advantages.

The catalyst elements that can be used in the above two technologies are, in addition to nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (S
n), lead (Pb), cobalt (Co), platinum (Pt),
Elements such as copper (Cu) and gold (Au) may be used.

A semiconductor layer of a TFT can be formed by forming a crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) using the above-described techniques and performing patterning. Although TFTs manufactured from a crystalline semiconductor film have excellent characteristics, they have been required to have high reliability. However, the T of the present invention
By adopting the FT structure, it is possible to manufacture a TFT that makes the most of the technology of this embodiment. This embodiment can be used in combination with any one of Embodiments 1 to 5.

[Embodiment 7] In this embodiment, the method of forming the semiconductor layer used in the embodiment 1 is as follows. An example in which a step of removing a catalytic element from a crystalline semiconductor film after forming a semiconductor film is described. In the present embodiment, the technique described in JP-A-10-135468 or 10-135469 was used as the method.

The technique described in the publication is a technique for removing the catalytic element used for crystallization of the amorphous semiconductor film after crystallization by using the gettering action of phosphorus. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 1
It can be reduced to 0 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ .

The configuration of this embodiment will be described with reference to FIG. Here, an alkali-free glass substrate typified by a Corning 1737 substrate was used. In FIG. 20A, the base film 8 is formed using the crystallization technique described in the sixth embodiment.
02 shows a state where the crystalline silicon film 803 is formed. Then, a silicon oxide film 804 for a mask is formed on the surface of the crystalline silicon film 803 to a thickness of 150 nm, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus was performed to provide a region 805 to which phosphorus was added in the crystalline silicon film.

In this state, 550 to 80
When heat treatment is performed at 0 ° C. for 5 to 24 hours (600 ° C. for 12 hours in this embodiment), the region 805 in which phosphorus is added to the crystalline silicon film functions as a gettering site and remains in the crystalline silicon film 803. The catalyst element was able to move to the region 805 to which phosphorus was added.

Then, a silicon oxide film 804 for a mask is used.
And the region 805 to which phosphorus is added by etching to remove the crystalline silicon film in which the concentration of the catalytic element used in the crystallization step is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. I got it. This crystalline silicon film could be used as it is as the active layer of the TFT of the present invention shown in Example 1. This embodiment is similar to the first embodiment.
5 can be used in combination.

[Embodiment 8] In this embodiment, another embodiment in which a semiconductor layer and a gate insulating film are formed in the step of manufacturing the TFT of the present invention shown in Embodiment 1 will be described.

Here, at least 700-1100 ° C.
A substrate having a high degree of heat resistance is required.
1 was used. Then, the crystalline semiconductor film was formed using the techniques described in the sixth and seventh embodiments, and the active layers 902 and 903 were formed by patterning in an island shape. And
A gate insulating film 904 covering the active layers 902 and 903
Was formed with a film containing silicon oxide as a main component. In this embodiment, a silicon nitride oxide film is formed to a thickness of 70 nm by a plasma CVD method.
The thickness was formed. (FIG. 21A)

Then, a heat treatment was performed in an atmosphere containing halogen (typically chlorine) and oxygen. In this embodiment, 9
50 ° C., 30 minutes. The processing temperature is 700 to 110.
The temperature may be selected within the range of 0 ° C.
I wish I had to choose between the hours. (FIG. 21 (B))

As a result, under the conditions of this embodiment, the active layer 9
A thermal oxide film was formed at an interface between the gate insulating film 904 and the gate insulating film 904, and a gate insulating film 907 was formed.

The gate insulating film 90 manufactured by the above steps
In No. 7, the withstand voltage was high and the interface between the active layers 905 and 906 and the gate insulating film 907 was very good. In order to obtain the structure of the TFT of the present invention, the subsequent steps may be in accordance with the first embodiment.

Of course, the combination of the sixth embodiment and the seventh embodiment with this embodiment may be determined by the practitioner as appropriate.

[Embodiment 9] Various liquid crystals other than the nematic liquid crystal can be used in the above-described liquid crystal display device of the present invention. For example, 1998, SID, "Characteristics and
Driving Scheme of Polymer-Stabilized Monostable FLC
D Exhibiting Fast Response Time andHigh Contrast R
atio with Gray-Scale Capability "by H. Furue et a
l. and 1997, SID DIGEST, 841, "A Full-Color Thresho
ldless Antiferroelectric LCDExhibiting Wide Viewin
g Angle with Fast Response Time "by T. Yoshida eta
l., 1996, J. Mater. Chem. 6 (4), 671-673, "Thresh
oldless antiferroelectricity in liquid crystals an
d its application to displays "by S. Inui et al.
Alternatively, the liquid crystal disclosed in U.S. Pat. No. 5,594,569 can be used.

Ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 10 shows the electro-optical characteristics of a monostable FLC in which a cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage, and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 10 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 10 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
fV-switching mode ”is described by Terada et al.
Half-V Switching Mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Moon, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 19
See page 0 for details.

As shown in FIG. 10, it can be seen that the use of such a ferroelectric mixed liquid crystal enables low-voltage driving and gradation display. A ferroelectric liquid crystal having such electro-optical characteristics can be used in the liquid crystal display device of the present invention.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low-voltage driving can be realized, so that low power consumption can be realized.

[Embodiment 10] A CMOS circuit and a pixel portion formed by carrying out the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display). That is, the present invention can be applied to all electric appliances in which these electro-optical devices are incorporated in a display unit.

Examples of such electric appliances include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggle type display), a personal computer, a portable information terminal (mobile computer, a mobile phone, or an electronic book). Etc.). Examples of these are shown in FIGS.
And FIG.

FIG. 11A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 11B shows a video camera, which includes a main body 2101, a display section 2102, an audio input section 2103, operation switches 2104, a battery 2105, and an image receiving section 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal control circuits.

FIG. 11C shows a mobile computer (mobile computer) including a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 11D shows a goggle type display, which includes a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 11E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display 2402, and a speaker 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 11F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 12A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 12B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 12D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 12C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 12D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 12, a case where a transmission type electro-optical device is used is shown, and examples of application to a reflection type electro-optical device and an EL display device are not shown.

FIG. 13A shows a mobile phone, and the main body 29 is shown.
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.

FIG. 13B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 13C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to eighth embodiments.

[Embodiment 11] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 14A is a top view of an EL display device using the present invention. In FIG. 14A, reference numeral 4010 denotes a substrate; 4011, a pixel portion; 4012, a source driver circuit; 4013, a gate driver circuit;
And connected to the external device.

At this time, at least the pixel portion, preferably the drive circuit and the pixel portion are surrounded by
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 14B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
As the FT, a TFT manufactured according to the present invention may be used.

The present invention can be applied to a TFT 4022 for a driving circuit and a TFT 4023 for a pixel portion.

A TFT 402 for a driving circuit is formed by using the present invention.
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, a cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Further, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

Further, a spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 12] In this embodiment, an example in which an EL display device having a mode different from that of Embodiment 11 is manufactured by using the present invention will be described with reference to FIGS. 15 (A) and 15 (B). I do. 14A and 14B denote the same parts, and a description thereof will not be repeated.

FIG. 15A is a top view of the EL display device of this embodiment, and FIG. 15B is a cross-sectional view taken along line AA ′ of FIG.

In accordance with Embodiment 10, a passivation film 6003 is formed to cover the surface of the EL element.

Further, the filling material 6
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

Further, a spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light transmitting property.

Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 13] FIG. 16 shows a more detailed sectional structure of a pixel portion in an EL display panel, FIG. 17A shows a top view structure, and FIG. 17B shows a circuit diagram. In FIGS. 16, 17A and 17B, common reference numerals are used, and therefore, they may be referred to each other.

In FIG. 16, a switching TFT 3502 provided on a substrate 3501 is an NTF of the present invention.
It is formed using T (see Examples 1 to 7). In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used.

The current controlling TFT 3503 is formed using the NTFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. The wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.

At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which an LDD region is provided in a current control TFT so as to overlap a gate electrode with a gate insulating film interposed therebetween is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 17A, the wiring to be the gate electrode 37 of the current controlling TFT 3503 has 35
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 3503 via an insulating film. At this time, 3
In the region indicated by 504, a capacitor is formed. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, "Polymers f
or Light Emitting Diodes ", Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light-emitting layers, cyanopolyphenylenevinylene is used for a red light-emitting layer, polyphenylenevinylene is used for a green light-emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light-emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used for the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, and the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. And a TFT. Therefore,
EL with high reliability and good image display
A display panel is obtained.

The configuration of the present embodiment can be implemented by freely combining with the configurations of Embodiments 1 to 9.
Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the tenth embodiment.

[Embodiment 14] In this embodiment, Embodiment 13 will be described.
A structure in which the structure of the EL element 3505 is inverted in the pixel portion shown in FIG. FIG. 18 is used for the description. The only difference from the structure of FIG. 16 is the EL element portion and the current controlling TFT, so that the other description will be omitted.

In FIG. 18, the current control TFT 350
3 is formed using PTFT.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of insulating films
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

The configuration of the present embodiment can be implemented by freely combining with the configurations of Embodiments 1 to 9.
Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the tenth embodiment.

[Embodiment 14] In the present embodiment, FIG.
FIGS. 19A to 19C show examples in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, reference numeral 3801 denotes a switching TFT 380.
2 is a source wiring, and 3803 is a switching TFT 38.
02, a gate wiring 3804, a current controlling TFT 38,
05 is a capacitor, 3806 and 3808 are current supply lines,
Reference numeral 3807 denotes an EL element.

FIG. 19A shows an example in which a current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 19B shows a current supply line 380.
8 is provided in parallel with the gate wiring 3803. Note that in FIG. 19B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other; however, if both wirings are formed in different layers,
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

FIG. 19C shows that a current supply line 3808 is provided in parallel with the gate wiring 3803 and two pixels are connected to the current supply line 3808 in the same manner as in the structure of FIG. 19B.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment is similar to those of Embodiments 1 to 9,
The present invention can be implemented by freely combining with the configuration of 11 or 12. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 10.

[Embodiment 16] FIG. 17 shown in Embodiment 13
17A and 17B, a capacitor 350 holds a voltage applied to the gate of the current controlling TFT 3503.
4, but the capacitor 3504 can be omitted. In the case of the twelfth embodiment, since the NTFT of the present invention as shown in the first to eighth embodiments is used as the current control TFT 3503, the TFT has an LDD region provided so as to overlap the gate electrode via the gate insulating film. ing. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, the capacitance is determined by the length of the LDD region included in the overlapping region.

FIGS. 19A to 19C shown in the fourteenth embodiment.
Similarly, in the structure of (C), the capacitor 3805 can be omitted.

The configuration of the present embodiment is similar to those of Embodiments 1 to 9,
The present invention can be implemented by freely combining with the configurations of 11 to 15. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 10.

[0156]

According to the present invention, a metal film can be easily deposited on the side surface and the upper portion of the gate wiring by setting the deposition conditions by the electrolytic plating method. Further, an impurity element is added to the island-shaped semiconductor layer using the metal film as a mask, so that LDD regions can be formed on both sides of the gate wiring with a uniform width. As a result, a semiconductor device having a GOLD structure is obtained, so that a TFT with high breakdown voltage and high reliability can be manufactured. In addition, 15 to 15
A stable operation can be obtained even when driving by applying a gate voltage of 20V. As a result, the reliability of a semiconductor device including a CMOS circuit made of a crystalline TFT, and more specifically, a drive circuit provided around a liquid crystal display device or an EL display device can be improved, and the device can be used for a long time. A liquid crystal display device and an EL display device can be obtained.

[Brief description of the drawings]

FIG. 1 is a simplified diagram of an electrolytic plating method.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT according to the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a TFT according to the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of an active matrix substrate according to the present invention.

FIG. 5 is a cross-sectional view showing a step of manufacturing an active matrix substrate according to the present invention.

FIG. 6 is a cross-sectional view showing a step of manufacturing an active matrix substrate according to the present invention.

FIG. 7 is a cross-sectional view showing a step of manufacturing an active matrix substrate according to the present invention.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 10 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.

FIG. 11 illustrates an example of an electric appliance.

FIG. 12 illustrates an example of an electric appliance.

FIG. 13 illustrates an example of an electric appliance.

FIG. 14 illustrates a structure of an EL display device.

FIG. 15 illustrates a structure of an EL display device.

FIG. 16 illustrates a structure of an EL display device.

FIG. 17 illustrates a structure of an EL display device.

FIG. 18 illustrates a structure of an EL display device.

FIG. 19 illustrates a structure of an EL display device.

FIG. 20 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 21 is a cross-sectional view illustrating a manufacturing process of a TFT.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/3205 G02F 1/136 500 21/8238 H01L 21/88 R 27/092 27/08 321D 27/08 331 29 / 62 G 29/43 29/78 616A 21/336 617J 627G

Claims (18)

[Claims] 2. A semiconductor device comprising: a TFT having a gate wiring on a gate insulating film, and a metal film having the same thickness on a side surface and an upper surface of the gate wiring. 2. A semiconductor device having a gate wiring on a gate insulating film, and a TFT having a metal film deposited by an electrolytic plating method on a side surface and an upper surface of the gate wiring. 3. An n-channel TFT and a p-channel TFT
In a semiconductor device having a CMOS circuit formed by FT, the n-channel TFT and the p-channel TFT
Has a gate wiring on a gate insulating film, and the gate wiring has a metal film on a side surface and an upper surface. 4. An n-channel TFT and a p-channel TFT
In a semiconductor device including a CMOS circuit formed by FT, the n-channel TFT and the p-channel TFT
A gate insulating film on each of the active layers, a gate wiring on the gate insulating film, and a metal film covering side and top surfaces of the gate wiring. The active layer of the n-channel TFT has a channel Forming a first impurity region in contact with the channel forming region, a second impurity region in contact with the first impurity region, and a third impurity region in contact with the second impurity region; A semiconductor device, which is formed so as to overlap a formation region, wherein a width of the first impurity region is determined by a thickness of a metal film formed on a side surface of the gate wiring. 5. An n-channel TFT and a p-channel TF
A semiconductor device including a CMOS circuit formed with T, comprising: a gate insulating film on an active layer; a gate wiring on the gate insulating film; and a metal film covering side and top surfaces of the gate wiring, The active layer of the n-channel TFT includes a channel forming region, a first impurity region in contact with the channel forming region, a second impurity region in contact with the first impurity region, and a third impurity region in contact with the second impurity region. A length of the channel formation region, a width of the gate wiring, a length of the first impurity region, and a thickness of the metal film via the gate insulating film; Wherein the catalyst element used for crystallization of the active layer is present at a concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ . 6. The method according to claim 3, wherein the first impurity region has an impurity concentration of 1 ×.
10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , and the impurity concentration contained in the second impurity region is 2 × 10 ^{16 to} 5 × 10 ¹⁹
atoms / cm ³ , and the third impurity concentration is 1 × 10 ²⁰
A semiconductor device having a density of about 1 × 10 ²¹ atoms / cm ³ . 7. The method according to claim 4, wherein the catalyst element is N
i, Ge, Co, Fe, Pd, Sn, Pb, Pt, C
A semiconductor device, which is one or more elements selected from u, Au, and Si. 8. The method according to claim 1, wherein the metal film is made of Al, Au, Ag, Cu, Cr, N
A semiconductor device formed using one or more kinds selected from i, Zn, Sn, and Co. 9. The semiconductor device according to claim 1, wherein said gate wiring is made of Ta, TaN, W, Mo, A
A semiconductor device formed using a material containing a metal selected from l, Cu, and Au. 10. The semiconductor device according to claim 1, wherein the gate wiring is formed of one or more layers on the gate insulating film. 11. The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display panel or an EL device.
A semiconductor device, which is a display panel. 12. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a projector, a projection TV, a goggle type display, a personal computer, or a portable information terminal. Semiconductor device. 13. A step of crystallizing a semiconductor layer formed on a substrate having an insulating surface to form an active layer, a step of forming a gate insulating film on the active layer, and a step of forming a gate on the gate insulating film. Forming a wiring, forming a first impurity region by adding an impurity using the gate wiring as a mask, forming a metal film on a side surface and an upper part of the gate wiring by electrolytic plating, Forming a fourth impurity region in the p-channel thin film transistor by adding an impurity using the film as a mask, forming an second impurity region by adding an impurity using the metal film as a mask, Forming a third impurity region by adding an impurity to a selected portion. 14. The method according to claim 13, wherein the method of crystallizing the semiconductor layer is performed by one or more methods selected from thermal crystallization, laser crystallization, and crystallization using a catalyst. A method for manufacturing a semiconductor device. 15. A step of adding a catalytic element to a semiconductor layer formed on a substrate having an insulating surface, a step of heat-treating and crystallizing the semiconductor layer to form an active layer, and a step of forming a gate on the active layer. Forming an insulating film; forming a gate wiring on the gate insulating film; adding an impurity using the gate wiring as a mask to form a first impurity region; and forming the gate wiring by electrolytic plating. Forming a metal film on the side surface and the upper portion of the semiconductor device; forming a fourth impurity region in the p-channel thin film transistor by adding an impurity using the metal film as a mask; and adding an impurity using the metal film as a mask. A semiconductor device comprising: forming a second impurity region; and adding a impurity to a selected portion of the active layer to form a third impurity region. Manufacturing method. 16. A catalyst element according to claim 13, wherein the catalyst element used for crystallization is Ni, Ge, C
A method for manufacturing a semiconductor device, comprising one or more elements selected from the group consisting of o, Fe, Pd, Sn, Pb, Pt, Cu, Au, and Si. 17. A method according to claim 13, wherein the semiconductor device is a liquid crystal display panel or an EL display panel. 18. The semiconductor device according to claim 13, wherein the semiconductor device is a video camera, a digital camera, a projector, a projection TV, a goggle-type display, a personal computer, or a portable information terminal. Semiconductor device manufacturing method.