JPH0955508A - Thin film transistor and its manufacture - Google Patents

Thin film transistor and its manufacture

Info

Publication number
JPH0955508A
JPH0955508A JP20460595A JP20460595A JPH0955508A JP H0955508 A JPH0955508 A JP H0955508A JP 20460595 A JP20460595 A JP 20460595A JP 20460595 A JP20460595 A JP 20460595A JP H0955508 A JPH0955508 A JP H0955508A
Authority
JP
Japan
Prior art keywords
region
insulating film
source
drain
gate insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20460595A
Other languages
Japanese (ja)
Inventor
Tsutomu Yamada
努 山田
Masashi Jinno
優志 神野
Kyoko Hirai
恭子 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP20460595A priority Critical patent/JPH0955508A/en
Publication of JPH0955508A publication Critical patent/JPH0955508A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L2029/7863—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent that, at the time of etching a poly silicon gate in a p- SiTFT, defects are generated in a gate insulating film, and a leak current, avalanche deterioration, etc. occur from a carrier trap. SOLUTION: A source region 11S and a drain region 11D which have high concentration are formed. Inside them, an LD region 11L of low concentration is formed. Further inside the LD region 11L, a VLD region 11VL of very low concentration is formed. Thereby electric fields on both end portions of a channel are relieved, so that generation of a leak current and avalanche deterioration is prevented. By covering the side wall of a gate electrode 13 with a spacer 14, and implanting impurity ions in the LD region 11L, the VLD region 11VL is formed in the manner in which the shadow part of the spacer 14 is doped with a very low concentration.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、液晶表示装置（Ｌ
ＣＤ：Liquid Crystal Display）に関し、特に、駆動回
路部を表示画素部と同様に基板上に一体形成した、駆動
回路一体型ＬＣＤに関する。The present invention relates to a liquid crystal display (L).
More specifically, the present invention relates to a drive circuit integrated LCD in which a drive circuit unit is integrally formed on a substrate similarly to a display pixel unit.

【０００２】[0002]

【従来の技術】ＬＣＤは小型、薄型、低消費電力などの
利点があり、ＯＡ機器、ＡＶ機器などの分野で実用化が
進んでいる。特に、スイッチング素子として、薄膜トラ
ンジスタ（ＴＦＴ：Thin Film Transistor）を用いたア
クティブマトリクス型は、原理的にデューティ比１００
％のスタティック駆動をマルチプレクス的に行うことが
でき、大画面、高精細な動画ディスプレイに使用されて
いる。2. Description of the Related Art LCDs have advantages such as small size, thin shape and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a thin film transistor (TFT) as a switching element has a duty ratio of 100 in principle.
Percentage static drive can be performed in multiplex, and it is used for large-screen and high-definition video displays.

【０００３】アクティブマトリクスＬＣＤは、マトリク
ス状に配置された表示電極にＴＦＴを接続形成した基板
（ＴＦＦ基板）と共通電極を有する基板（対向基板）
が、液晶を挟んで貼り合わされて構成されている。表示
電極と共通電極の対向部分は液晶を誘電層とした画素容
量となっており、ＴＦＴにより選択された電圧が印加さ
れる。液晶は電気光学的に異方性を有しており、画素容
量により形成された電界の強度に対応して光を変調す
る。An active matrix LCD has a substrate in which TFTs are connected to display electrodes arranged in a matrix (TFF substrate) and a substrate having a common electrode (counter substrate).
Are bonded together with a liquid crystal interposed therebetween. The opposing portion between the display electrode and the common electrode is a pixel capacitance using a liquid crystal as a dielectric layer, and a voltage selected by the TFT is applied. The liquid crystal has electro-optical anisotropy and modulates light according to the intensity of the electric field formed by the pixel capacitance.

【０００４】近年、ＴＦＴのチャンネル層として多結晶
（ポリ）シリコン（ｐ−Ｓｉ）を用いることによって、
マトリクス画素部と周辺駆動回路部を同一基板上に形成
した駆動回路一体型のＬＣＤが開発されている。一般
に、ｐ−Ｓｉは非晶質シリコン（ａ−Ｓｉ）に比べて移
動度が高く、また、ゲートにもポリシリコンを用いたシ
リコンゲート構造、即ちゲートセルフアラインによる微
細化、寄生容量の縮小による高速化が達成され、ｎ−ｃ
ｈＴＦＴとｐ−ｃｈＴＦＴの相補構造を形成することに
より、高速駆動回路を構成することができる。このよう
に、駆動回路部をマトリクス画素部と一体形成すること
により、製造コストの削減、ＬＣＤモジュールの小型化
が実現される。In recent years, by using polycrystalline (poly) silicon (p-Si) as a channel layer of a TFT,
An LCD integrated with a driving circuit in which a matrix pixel portion and a peripheral driving circuit portion are formed on the same substrate has been developed. Generally, p-Si has a higher mobility than amorphous silicon (a-Si), and a silicon gate structure using polysilicon for a gate, that is, miniaturization by gate self-alignment and reduction of parasitic capacitance. Higher speed is achieved and n-c
By forming a complementary structure of the hTFT and the p-chTFT, a high speed drive circuit can be constructed. Thus, by integrally forming the drive circuit unit and the matrix pixel unit, the manufacturing cost can be reduced and the LCD module can be downsized.

【０００５】図１２にこのようなＬＣＤの構成を示す。
中央部の点線で囲まれた部分はマトリクス画素部であ
り、ＴＦＴのＯＮ／ＯＦＦを制御するゲートライン（Ｇ
１〜Ｇｍ）と画素信号用のドレインライン（Ｄ１〜Ｄ
ｎ）が交差して配置されている。各交点にはＴＦＴとこ
れに接続する表示電極（いずれも不図示）が形成されて
いる。画素部の左右にはゲートライン（Ｇ１〜Ｇｍ）を
選択するゲートドライバー（ＧＤ）が配置され、画素部
の上下には、映像信号をサンプリングしてホールドし、
ゲートドライバ（ＧＤ）の走査に同期して各ドレインラ
イン（Ｄ１〜Ｄｎ）に画素信号電圧を印加するドレイン
ドライバー（ＤＤ）が配置されている。これらのドライ
バー（ＧＤ，ＤＤ）は主としてシフトレジスタからな
り、これは、ｐ−ＳｉＴＦＴのｎ−ｃｈとｐ−ｃｈの相
補構造により構成されている。FIG. 12 shows the structure of such an LCD.
The part surrounded by the dotted line in the center is the matrix pixel part, and the gate line (G
1 to Gm) and drain lines for pixel signals (D1 to Dm)
n) are arranged to intersect. At each intersection, a TFT and a display electrode (not shown) connected to the TFT are formed. Gate drivers (GD) for selecting gate lines (G1 to Gm) are arranged on the left and right of the pixel portion, and video signals are sampled and held above and below the pixel portion,
A drain driver (DD) that applies a pixel signal voltage to each drain line (D1 to Dn) in synchronization with the scanning of the gate driver (GD) is arranged. These drivers (GD, DD) mainly consist of shift registers, which are constructed by the complementary structure of n-ch and p-ch of p-Si TFT.

【０００６】図１３に、このようなｐ−ＳｉＴＦＴの構
造を示す。高耐熱性の石英ガラスなどの基板（１００）
上に、島状にパターニングされたｐ−Ｓｉ（１０１）が
形成され、ｐ−Ｓｉ（１０１）上には、ＳｉＯ2などの
ゲート絶縁膜（１０２）が被覆されている。ゲート絶縁
膜（１０２）上には、ドープドｐ−Ｓｉ（１０３ｐ）と
シリサイド（１０３ｓ）のポリサイド層からなるゲート
電極（１０３）が形成されている。また、ｐ−Ｓｉ（１
０１）は、ゲート電極（１０３）をマスクとしたセルフ
アライン構造で、ｎ型あるいはｐ型に高濃度にドーピン
グされたソース・ドレイン領域（１０１Ｓ，１０１Ｄ）
と、ノンドープのチャンネル領域（１０１Ｎ）が形成さ
れている。またソース及びドレイン領域（１０１Ｓ，１
０１Ｄ）にはそれぞれチャンネル領域（１０１Ｎ）に接
する部分で濃度の低い領域（１０１Ｌ）が介在されてい
る。このようなチャンネルの構造はＬＤＤ（lightlydop
ed drain）と呼ばれ、ｐ−ＳｉＴＦＴＬＣＤにあって
は、画素部のＯＦＦ電流抑制、ドライバー部の信頼性の
向上が達成される。これらｐ−Ｓｉ（１０１）とゲート
電極（１０３）を覆う全面にはＳｉＮXなどの層間絶縁
膜（１０４）が被覆され、層間絶縁膜（１０４）上に
は、Ａｌなどからなるソース及びドレイン電極（１０
５，１０６）が設けられ、コンタクトホール（ＣＴ）を
介して各々ソース・ドレイン領域（１０１Ｓ，１０１
Ｄ）に接続されている。更に図示は省いたが、画素部で
はＩＴＯからなる表示電極が形成されてソース電極（１
０５）へ接続され、ドレイン電極（１０６）は同一列に
ついて１本のドレインラインに接続される。また駆動回
路部では層間絶縁膜と導電膜により多層配線が形成され
て所定の結線が形成される。FIG. 13 shows the structure of such a p-Si TFT. Substrate such as quartz glass with high heat resistance (100)
An island-shaped patterned p-Si (101) is formed thereon, and the p-Si (101) is covered with a gate insulating film (102) such as SiO2. A gate electrode (103) made of a polycide layer of doped p-Si (103p) and silicide (103s) is formed on the gate insulating film (102). Also, p-Si (1
Reference numeral 01) is a self-aligned structure using the gate electrode (103) as a mask, and is a source / drain region (101S, 101D) which is highly doped with n-type or p-type.
And a non-doped channel region (101N) is formed. In addition, the source and drain regions (101S, 1
01D) has a low concentration region (101L) in contact with the channel region (101N). The structure of such a channel is LDD (lightly dop).
In the p-SiTFT LCD, the OFF current is suppressed in the pixel portion and the reliability of the driver portion is improved. The entire surface covering the p-Si (101) and the gate electrode (103) is covered with an interlayer insulating film (104) such as SiNX, and on the interlayer insulating film (104), source and drain electrodes (such as Al) ( 10
5, 106) are provided, and the source / drain regions (101S, 101) are respectively provided through the contact holes (CT).
D). Further, although not shown in the drawing, a display electrode made of ITO is formed in the pixel portion and the source electrode (1
05) and the drain electrode (106) is connected to one drain line for the same column. Further, in the driving circuit portion, a multilayer wiring is formed by the interlayer insulating film and the conductive film to form a predetermined connection.

【０００７】このようにゲート電極及びその配線層とし
て、下層がポリシリコン、上層がシリコンと高融点金属
の化合物合金層のシリサイドからなるポリサイドゲート
構造は、セルフアラインによるトランジスタサイズの小
型化、高速化とともに、ゲート絶縁膜との相性、配線抵
抗の点で有利である。このようなｐ−ＳｉＴＦＴは以下
のように製造している。まず基板（１００）上に、熱Ｃ
ＶＤによりｐ−Ｓｉ（１０１）膜を形成し、これを島状
にエッチングする。ｐ−Ｓｉ（１０１）上にはＣＶＤあ
るいは熱酸化により、ゲート絶縁膜（１０２）を形成
し、続いてポリシリコン（１０３ｐ）を形成し、燐の拡
散注入を行って低抵抗化した後、タングステンシリサイ
ド（１０３ｓ）を形成する。これらポリサイド層をエッ
チングしてゲート電極（１０３）を形成した後、ゲート
電極（１０３）をマスクにｐ−Ｓｉ（１０１）へ不純物
のイオン注入を低ドーズ量で行うことにより、ソース領
域（１０１Ｓ）及びドレイン領域（１０１Ｄ）を形成す
るとともに、ノンドープのチャンネル領域（１０１Ｎ）
を形成する。更に、ゲート電極（１０３）よりも大きな
サイズでマスキングレジストを施した後、高ドーズ量の
イオン注入を行って低濃度のＬＤ領域（１０１Ｌ）を残
しながら高濃度のソース・ドレイン領域（１０１ｓ，１
０１ｄ）を形成する。そして、層間絶縁膜（１０４）及
びコンタクトホール（ＣＴ）を形成した後、ソース電極
（１０５）及びドレイン電極（１０６）を形成してそれ
ぞれソース領域（１０１Ｓ）及びドレイン領域（１０１
Ｄ）に接続することによりＴＦＴが完成する。As described above, as the gate electrode and its wiring layer, the polycide gate structure in which the lower layer is polysilicon and the upper layer is silicide of a compound alloy layer of silicon and a refractory metal has a self-aligned transistor size reduction and high speed. In addition, it is advantageous in compatibility with the gate insulating film and wiring resistance. Such a p-Si TFT is manufactured as follows. First, heat C on the substrate (100)
A p-Si (101) film is formed by VD, and this is etched into an island shape. A gate insulating film (102) is formed on the p-Si (101) by CVD or thermal oxidation, then polysilicon (103p) is formed, and phosphorus is diffused and implanted to reduce the resistance, and then tungsten is formed. A silicide (103s) is formed. After these polycide layers are etched to form the gate electrode (103), impurity ions are implanted into the p-Si (101) at a low dose by using the gate electrode (103) as a mask to form the source region (101S). And a drain region (101D) are formed, and a non-doped channel region (101N) is formed.
To form Further, after a masking resist having a size larger than that of the gate electrode (103) is applied, high dose ion implantation is performed to leave a low concentration LD region (101L) and a high concentration source / drain region (101s, 1s).
01d) is formed. Then, after forming the interlayer insulating film (104) and the contact hole (CT), the source electrode (105) and the drain electrode (106) are formed to respectively form the source region (101S) and the drain region (101).
The TFT is completed by connecting to D).

【０００８】[0008]

【発明が解決しようとする課題】従来は、シリサイド
（１０３ｓ）とポリシリコン（１０３ｐ）のエッチング
は、微細加工をするためにドライエッチング、特に、反
応性イオンエッチング、即ち、ＲＩＥ（reactive ion e
tching）により行っている。ＲＩＥは、高周波放電プラ
ズマにより、反応ガスをイオン化して加速し、これを被
エッチング膜と反応させることでエッチングするもので
ある。このため、電気化学的反応のみならず物理的エネ
ルギーによっても反応が促進され、エッチングレートを
上げることができるが、その反面、ジャストエッチング
の制御が困難であり、オーバーエッチ量を大きくするこ
とが必要となることも加えて、下地へのダメージも大き
い。Conventionally, the etching of silicide (103s) and polysilicon (103p) is performed by dry etching, particularly reactive ion etching, that is, RIE (reactive ion etching) for fine processing.
tching). The RIE is to perform etching by ionizing and accelerating a reaction gas by high-frequency discharge plasma and reacting it with a film to be etched. For this reason, the reaction can be promoted not only by the electrochemical reaction but also by the physical energy, and the etching rate can be increased, but on the other hand, it is difficult to control just etching, and it is necessary to increase the overetch amount. In addition to that, the damage to the base is also large.

【０００９】ゲート電極（１０３）の完成後、ゲート絶
縁膜（１０２）へオーバーエッチがかかり、図１４に示
すようにゲート電極（１０３）の横のゲート絶縁膜（１
０２）表面がダメージを受け（ＤＭ）、膜中の欠陥が増
えると、キャリアトラップによりリーク電流が増大す
る。この結果、画素部にあっては、液晶への印加電圧の
保持率が低下し、コントラスト比が落ちるなのどの問題
を招いていた。特に、小型化が達成されたｐ−ＳｉＴＦ
Ｔでは、リーク電流の抑制が大きな課題となっている。
このようなリーク電流を招くような欠陥は、ソース・ド
レイン領域（１１Ｓ，１１Ｄ）の不純物イオン注入の際
にも生じやすくなっている。After the gate electrode (103) is completed, the gate insulating film (102) is over-etched, and the gate insulating film (1) next to the gate electrode (103) is formed as shown in FIG.
02) When the surface is damaged (DM) and the number of defects in the film increases, the carrier trap increases the leak current. As a result, in the pixel portion, the holding ratio of the voltage applied to the liquid crystal is lowered and the contrast ratio is lowered, which causes problems. In particular, the miniaturization of p-SiTF
At T, suppression of leak current has become a major issue.
Defects that cause such a leak current are also likely to occur during impurity ion implantation of the source / drain regions (11S, 11D).

【００１０】また、ゲート絶縁膜（１０２）のオーバー
エッチがばらつくと、イオン注入の際に、ソース、ドレ
インあるいはＬＤ領域（１０１Ｓ，１０１Ｄ，１０１
Ｌ）の濃度が素子ごとに異なり、特性のばらつきが出る
などの問題もある。更に、駆動回路部においては、キャ
リアトラップをきっかけとしてアバランシェ現象が起こ
りやすく、相補構造において重要なソース・ドレイン間
電圧の飽和領域が縮小し、素子特性が劣化しやすくな
り、さらにはゲート・ソース間あるいはゲート・ドレイ
ン間の絶縁破壊等にもつながり、動作不良の原因となっ
ていた。Further, if the over-etching of the gate insulating film (102) varies, the source, drain or LD regions (101S, 101D, 101) are formed during ion implantation.
There is also a problem that the concentration of L) varies from element to element, resulting in variations in characteristics. Further, in the driving circuit part, the avalanche phenomenon is likely to occur due to the carrier trap, the saturation region of the source-drain voltage which is important in the complementary structure is reduced, and the device characteristics are easily deteriorated. Alternatively, it may lead to dielectric breakdown between the gate and the drain, causing a malfunction.

【００１１】[0011]

【課題を解決するための手段】本発明はこの課題を解決
するために成されたもので、基板上に島状に形成され不
純物を含有しないチャンネル領域と該チャンネル領域の
両側に不純物を高濃度に含有したソース及びドレイン領
域とからなる多結晶半導体島層と、該多結晶半導体島層
を覆うゲート絶縁膜と、該ゲート絶縁膜上の前記チャン
ネル領域上方に形成され少なくとも多結晶シリコン層か
らなるゲート電極と、前記ソース領域に接続するソース
電極と、前記ドレイン領域に接続するドレイン電極とか
らなる薄膜トランジスタにおいて、前記ソース領域及び
ドレイン領域と前記チャンネル領域との間には、不純物
を低濃度に含有した低濃度領域が介在され、この低濃度
領域は各々前記ソース及びドレイン領域の側から前記チ
ャンネル領域の側へ向かって低下する不純物の濃度勾配
を有する構成である。SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and has a high impurity concentration on both sides of a channel region formed in an island shape on a substrate and containing no impurities. And a gate insulating film covering the polycrystalline semiconductor island layer, and at least a polycrystalline silicon layer formed above the channel region on the gate insulating film. In a thin film transistor including a gate electrode, a source electrode connected to the source region, and a drain electrode connected to the drain region, a low concentration of impurities is contained between the source region and the drain region and the channel region. A low concentration region interposed between the source and drain regions and the channel region. A structure having a concentration gradient of the impurity decreases toward.

【００１２】特に、前記低濃度領域は前記ソース及びド
レイン領域の側から前記チャンネル領域の側へ向かって
複数の中間段階の濃度を経て順次に不純物濃度が低下す
る構成である。また特に、前記ゲート電極の側壁には絶
縁性のスペーサが被覆され、このスペーサの直下には最
低の濃度の前記低濃度領域が形成されている構成であ
る。In particular, the low-concentration region has a structure in which the impurity concentration gradually decreases from the source and drain region side toward the channel region side through a plurality of intermediate-stage concentrations. In particular, the sidewall of the gate electrode is covered with an insulating spacer, and the low concentration region having the lowest concentration is formed immediately below the spacer.

【００１３】他に、前記ゲート電極の側壁はテーパー形
状に形成され、このテーパー部分の直下には、最低の濃
度の前記低濃度領域が形成されている構成である。この
ように高濃度のソース領域及びドレイン領域とノンドー
プのチャンネル領域との間に、段階的に不純物濃度の異
なる低濃度領域を複数介在させることにより、ソースあ
るいはドレイン領域近傍の強電界が緩和され、リーク電
流やアバランシェ劣化等が防がれる。In addition, the sidewall of the gate electrode is formed in a tapered shape, and the low concentration region having the lowest concentration is formed immediately below the tapered portion. Thus, by interposing a plurality of low-concentration regions having different impurity concentrations in stages between the high-concentration source and drain regions and the non-doped channel region, a strong electric field near the source or drain region is relaxed, Leakage current and avalanche deterioration can be prevented.

【００１４】また最低の濃度の低濃度領域は、ゲート電
極の側壁にスペーサをつける、あるいは、ゲート電極端
の断面をテーパー形状にすることにより、不純物のイオ
ン注入時に、スペーサあるいはテーパーを通じて注入さ
れる分と、横方向の拡散分などにより、真下に形成され
る。また本発明は、基板上に島状に形成され不純物を含
有しないチャンネル領域と該チャンネル領域の両側に不
純物を含有したソース及びドレイン領域とからなる多結
晶半導体島層と、該多結晶半導体島層を覆うゲート絶縁
膜と、該ゲート絶縁膜上の前記チャンネル領域上方に形
成され少なくとも多結晶シリコン層からなるゲート電極
と、前記ソース領域に接続するソース電極と、前記ドレ
イン領域に接続するドレイン電極とからなる薄膜トラン
ジスタの製造方法において、前記多結晶半導体島層と前
記ゲート絶縁膜が形成された前記基板上に、少なくとも
前記多結晶シリコン層を積層し、更にこの上にゲートパ
ターンを有したレジストを形成した後、放電プラズマの
生成雰囲気中で反応ガスを供給することによりドライエ
ッチングを行って前記ゲート電極を形成し、エッチング
終点において前記放電プラズマの高周波電力を低下し、
その後、オーバーエッチングを行う構成である。Further, the low-concentration region of the lowest concentration is formed by providing a spacer on the side wall of the gate electrode or by making the cross section of the end of the gate electrode into a tapered shape, and is implanted through the spacer or the taper at the time of ion implantation of impurities. And the amount of diffusion in the lateral direction, etc., are formed directly below. Further, the present invention is directed to a polycrystalline semiconductor island layer formed of an island-shaped channel region formed on a substrate and containing no impurities, and source and drain regions containing impurities on both sides of the channel region, and the polycrystalline semiconductor island layer. A gate insulating film covering the gate insulating film, a gate electrode formed above the channel region on the gate insulating film and made of at least a polycrystalline silicon layer, a source electrode connected to the source region, and a drain electrode connected to the drain region. In the method for manufacturing a thin film transistor, the method comprises: laminating at least the polycrystalline silicon layer on the substrate on which the polycrystalline semiconductor island layer and the gate insulating film are formed, and further forming a resist having a gate pattern on the polycrystalline silicon layer. After that, dry etching is performed by supplying a reactive gas in an atmosphere in which discharge plasma is generated. Forming a over gate electrode, it decreases the high-frequency power of the discharge plasma in the etching end point,
After that, over etching is performed.

【００１５】これにより、下地へのダメージの少ないオ
ーバーエッチがなされ、ゲート絶縁膜に生じる欠陥が減
り、キャリアトラップによるリーク電流やアバランシェ
劣化が防がれる。更に本発明は、基板上に島状に形成さ
れ不純物を含有しないチャンネル領域と該チャンネル領
域の両側に不純物を含有したソース及びドレイン領域と
からなる多結晶半導体島層と、該多結晶半導体島層を覆
うゲート絶縁膜と、該ゲート絶縁膜上の前記チャンネル
領域上方に形成され少なくとも多結晶シリコン層からな
るゲート電極と、前記ソース領域に接続するソース電極
と、前記ドレイン領域に接続するドレイン電極とからな
る薄膜トランジスタの製造方法において、前記多結晶半
導体島層と前記ゲート絶縁膜が形成された前記基板上
に、少なくとも前記多結晶シリコン層を積層し、更にこ
の上にゲートパターンを有したレジストを形成した後、
放電プラズマの生成雰囲気中でマグネトロン放電を行う
とともに反応ガスを供給することによりドライエッチン
グを行って前記ゲート電極を形成し、エッチング終点に
おいて前記マグネトロン放電を停止し、その後、オーバ
ーエッチングを行う構成である。As a result, over-etching with less damage to the underlying layer is performed, defects occurring in the gate insulating film are reduced, and leak current and avalanche deterioration due to carrier traps are prevented. Further, the present invention is directed to a polycrystalline semiconductor island layer including island-shaped channel regions formed on a substrate and containing no impurities, and source and drain regions containing impurities on both sides of the channel regions, and the polycrystalline semiconductor island layer. A gate insulating film covering the gate insulating film, a gate electrode formed above the channel region on the gate insulating film and made of at least a polycrystalline silicon layer, a source electrode connected to the source region, and a drain electrode connected to the drain region. In the method for manufacturing a thin film transistor, the method comprises: laminating at least the polycrystalline silicon layer on the substrate on which the polycrystalline semiconductor island layer and the gate insulating film are formed, and further forming a resist having a gate pattern on the polycrystalline silicon layer. After doing
Magnetron discharge is performed in a generation atmosphere of discharge plasma, and dry etching is performed by supplying a reaction gas to form the gate electrode, the magnetron discharge is stopped at the etching end point, and then overetching is performed. .

【００１６】これにより、下地へのダメージの少ないオ
ーバーエッチがなされ、ゲート絶縁膜に生じる欠陥が減
り、キャリアトラップによるリーク電流やアバランシェ
劣化が防がれる。As a result, over-etching with less damage to the base is performed, defects occurring in the gate insulating film are reduced, and leak current and avalanche deterioration due to carrier traps are prevented.

【００１７】[0017]

【発明の実施の形態】図１は本発明の第１の実施形態に
かかる薄膜トランジスタ（ＴＦＴ）部の平面図であり、
図２はそのＡ−Ａ線に沿った断面図である。石英基板
（１０）上に、多結晶シリコン（ｐ−Ｓｉ）（１１）が
島状に形成され、ｐ−Ｓｉ（１１）上にはゲート絶縁膜
（１２）が被覆されている。ゲート絶縁膜（１２）上
の、ｐ−Ｓｉ（１１）島層の中央部に対応する領域に
は、ゲート電極（１３）が形成され、ゲート電極（１
３）の側壁には絶縁性のスペーサ（１４）が被覆されて
いる。このスペーサ（１４）を含んだゲート電極（１
３）をマスクとしたセルフアライン関係をもってｐ−Ｓ
ｉ（１１）中央部にチャンネル領域（１１Ｎ）、チャン
ネル領域（１１Ｎ）の両側にはそれぞれ低濃度のＬＤ領
域（１１Ｌ）と極低濃度のＶＬＤ領域（１１ＶＬ）を挟
んで高濃度のソース及びドレイン領域（１１Ｓ，１１
Ｄ）が形成されている。ゲート電極（１３）は下層がポ
リシリコン（１３ｐ）、上層がタングステンなどのシリ
サイド（１３ｓ）からなるポリサイド層により形成され
ている。これらゲート電極（１３）上には、層間絶縁膜
（１５）が全面に被覆され、ソース領域（１１Ｓ）及び
ドレイン領域（１１Ｄ）上には層間絶縁膜（１５）とゲ
ート絶縁膜（１２）にコンタクトホール（ＣＴ）が形成
され、各々のコンタクトホール（ＣＴ）を介して、それ
ぞれ、ソース電極（１６）及びドレイン電極（１７）が
接続形成されている。FIG. 1 is a plan view of a thin film transistor (TFT) portion according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along the line AA. Polycrystalline silicon (p-Si) (11) is formed in an island shape on a quartz substrate (10), and a gate insulating film (12) is coated on the p-Si (11). A gate electrode (13) is formed on a region of the gate insulating film (12) corresponding to the central portion of the p-Si (11) island layer, and the gate electrode (1) is formed.
The side wall of 3) is covered with an insulating spacer (14). The gate electrode (1 including the spacer (14)
P-S with self-alignment relationship using 3) as a mask
i (11) A channel region (11N) at the center, and a high concentration source and drain with a low concentration LD region (11L) and an extremely low concentration VLD region (11VL) on both sides of the channel region (11N). Area (11S, 11
D) is formed. The gate electrode (13) has a lower layer made of polysilicon (13p) and an upper layer made of a polycide layer made of silicide (13s) such as tungsten. An interlayer insulating film (15) is entirely covered on the gate electrodes (13), and an interlayer insulating film (15) and a gate insulating film (12) are formed on the source region (11S) and the drain region (11D). A contact hole (CT) is formed, and a source electrode (16) and a drain electrode (17) are connected and formed through each contact hole (CT).

【００１８】この構造では、ゲート電極（１３）は、そ
の配線と一体で、ポリシリコン（１３ｐ）とシリサイド
（１３ｓ）の積層構造からなるポリサイドにより形成さ
れ、低抵抗化が達成されているとともに、ゲートセルフ
アライン構造によるトランジスタサイズの縮小と高速化
が実現されている。また、ゲート電極（１３）の側壁に
被覆されたスペーサ（１４）は、ゲート電極（１３）を
マスクとしたＬＤ領域（１１Ｌ）への不純物イオン注入
の際に、ＬＤ領域（１１Ｌ）よりも更に濃度の低いＶＬ
Ｄ領域（１１ＶＬ）を形成する働きを有している。即
ち、スペーサ（１４）を通じて僅かのイオン注入が成さ
れるとともに、横方向の拡散もあって、その真下には極
低濃度のＶＬＤ領域（１１ＶＬ）形成され、低濃度のＬ
Ｄ領域（１１Ｌ）の更に内側に位置し、チャンネル領域
（１１Ｎ）に接している。これら低濃度のＬＤ領域（１
１Ｌ）及び極低濃度のＶＬＤ領域（１１ＶＬ）は、それ
ぞれスペーサ（１４）及びゲート電極（１３）に対して
セルフアライン関係をもって位置している。このように
ＶＬＤ領域（１１ＶＬ）の介在により、チャンネル領域
端部の強電界が更に緩和されるので、キャリアトラップ
の増加によって従来のＬＤＤ構造では防ぎきれなかった
リーク電流やアバランシェ劣化等が防がれるようになっ
た。In this structure, the gate electrode (13) is formed integrally with the wiring by polycide having a laminated structure of polysilicon (13p) and silicide (13s) to achieve low resistance and The gate self-aligned structure has reduced the transistor size and increased the speed. Further, the spacer (14) coated on the side wall of the gate electrode (13) is further deeper than the LD region (11L) when the impurity ions are implanted into the LD region (11L) using the gate electrode (13) as a mask. VL with low concentration
It has a function of forming a D region (11 VL). That is, a slight ion implantation is performed through the spacer (14), and there is lateral diffusion, so that a VLD region (11VL) having an extremely low concentration is formed immediately below the LLD having a low concentration.
It is located further inside the D region (11L) and is in contact with the channel region (11N). These low-concentration LD regions (1
1 L) and the extremely low concentration VLD region (11 VL) are located in a self-aligned relationship with the spacer (14) and the gate electrode (13), respectively. In this way, the presence of the VLD region (11 VL) further relaxes the strong electric field at the end of the channel region, so that an increase in carrier traps prevents leakage current and avalanche deterioration which could not be prevented by the conventional LDD structure. It became so.

【００１９】図３に、側壁スペーサ（１４）を設けるこ
とによりＶＬＤ領域（１１ＶＬ）を形成したＶＬＤＤ構
造のＴＦＴのオフ時のリーク電流と、ＶＬＤ領域（１１
ＶＬ）を形成しない従来のＬＤＤ構造のＴＦＴのオフ時
のリーク電流の測定結果を示した。これにより、ＶＬＤ
領域（１１ＶＬ）を形成することで、ＯＦＦ時のリーク
電流が低減されることがわかる。In FIG. 3, the leak current when the TFT of the VLDD structure in which the VLD region (11VL) is formed by providing the sidewall spacer (14) is turned off, and the VLD region (11).
The measurement results of the leak current when the TFT of the conventional LDD structure in which VL) is not formed are turned off are shown. This makes VLD
It can be seen that by forming the region (11VL), the leak current at the time of OFF is reduced.

【００２０】図４は本発明の第２の実施形態にかかるＴ
ＦＴの平面図であり、図５はそのＢ−Ｂ線に沿った断面
図である。第１の実施形態と重複する部分は割愛しなが
ら本実施形態を説明する。図面では第１の実施形態と同
じ対象物については同一符号を用いている。本実例で
は、ゲート電極（１３）は、上層がシリサイド（１３
ｓ）、下層がポリシリコン（１３ｐ）からなるポリサイ
ドゲート構造であるとともに、その側壁がテーパー形状
になっている。このゲート電極（１３）をマスクとして
不純物イオンの注入を行って、低濃度のＬＤ領域（１１
Ｌ）を形成する際、ＬＤ領域（１１Ｌ）の内側には、更
に濃度の低いＶＬＤ領域（１１ＶＬ）が形成される。即
ち、不純物イオンの注入時に、テーパー部を通じた僅か
の注入分があるとともに、横方向の拡散があり、その真
下には極低濃度のＶＬＤ領域（１１ＶＬ）が形成され、
これは低濃度のＬＤ領域（１１Ｌ）の更に内側に位置
し、チャンネル領域（１１Ｎ）に接している。このよう
なＶＬＤ領域（１１ＶＬ）の介在により、チャンネル領
域端部の強電界が更に緩和されるので、キャリアトラッ
プの増加によって従来のＬＤＤ構造では防ぎきれなかっ
たリーク電流やアバランシェ劣化等が防がれるようにな
った。FIG. 4 shows a T according to the second embodiment of the present invention.
FIG. 5 is a plan view of the FT, and FIG. 5 is a sectional view taken along line BB thereof. This embodiment will be described, omitting the portions overlapping with those of the first embodiment. In the drawings, the same symbols are used for the same objects as in the first embodiment. In this example, the gate electrode (13) has a silicide (13
s), the lower layer has a polycide gate structure made of polysilicon (13p), and its sidewall is tapered. Impurity ions are implanted by using this gate electrode (13) as a mask to reduce the concentration of the LD region (11).
When forming L), the VLD region (11VL) having a lower concentration is formed inside the LD region (11L). That is, at the time of implanting the impurity ions, there is a slight amount of implantation through the taper portion, and there is lateral diffusion, and a VLD region (11VL) of extremely low concentration is formed thereunder,
This is located further inside the low-concentration LD region (11L) and is in contact with the channel region (11N). By interposing the VLD region (11VL), the strong electric field at the end of the channel region is further relaxed, so that the increase of carrier traps prevents the leakage current and the avalanche deterioration which could not be prevented by the conventional LDD structure. It became so.

【００２１】このようなゲート電極（１３）は、ウェッ
トエッチング、あるいは、プラズマエッチ、即ち、アノ
ードカップリング方式にて、高周波放電プラズマが生成
され、そのガスプラズマ中で励起エネルギーが与えられ
た反応種によりエッチングを進めるドライエッチング、
などの等方性エッチングを用いることによりサイドエッ
チが生じて形成されるものである。またこれらのエッチ
ングは、下地へのダメージが少ないので、ゲート絶縁膜
（１２）中に生じる欠陥が減る。Such a gate electrode (13) is a reactive species in which high-frequency discharge plasma is generated by wet etching or plasma etching, that is, an anode coupling method, and excitation energy is given in the gas plasma. Dry etching, which advances etching by
The side etching is generated by using isotropic etching such as. In addition, since these etchings have less damage to the base, the defects that occur in the gate insulating film (12) are reduced.

【００２２】次に、本発明に係るＴＦＴの製造方法を説
明する。まず、図６に、ゲート電極の形成において、反
応性イオンエッチング、即ち、ＲＩＥ（reactive ion e
tch）を用いたＴＦＴと、ウェットエッチングを用いた
ＴＦＴのＯＦＦ時のリーク電流の測定結果を示した。こ
れより、ＲＩＥの方が下地へのダメージが大きく、ゲー
ト絶縁膜の欠陥によりリーク電流を増していることが推
測される。しかし、微細化を達成した駆動回路一体型ｐ
−ＳｉＴＦＴＬＣＤでは、ゲート電極（１３）とその配
線の形成は、ドライエッチングによるのが望ましい。本
発明では、下地へのダメージの少ないドライエッチング
が実現される。Next, a method of manufacturing a TFT according to the present invention will be described. First, in FIG. 6, in forming a gate electrode, reactive ion etching, that is, RIE (reactive ion e)
The measurement results of the leak current when the TFT using tch) and the TFT using wet etching are turned off are shown. From this, it is presumed that RIE causes more damage to the base and increases the leak current due to defects in the gate insulating film. However, the drive circuit integrated p that achieved miniaturization
In the -SiTFT LCD, the gate electrode (13) and its wiring are preferably formed by dry etching. The present invention realizes dry etching with less damage to the base.

【００２３】以下、本発明のドライエッチング法を実現
する実施形態を説明する。なお、ここでは図１及び図２
に示した第１の実施形態のＴＦＴの製造方法により本発
明の製造方法を述べる。図７から図１０は、本実施形態
の薄膜トランジスタの製造方法を示す工程断面図であ
る。まず、図７において、石英などの基板（１０）上
に、熱ＣＶＤによりｐ−Ｓｉ（１１）を成膜し、これを
エッチングすることにより島状に形成する。次に図８に
示すように、ＣＶＤによりゲート絶縁膜（１２）を形成
し、更に、熱ＣＶＤによりポリシリコン（ｐ−Ｓｉ）
（１３ｐ）を形成した後、イオン拡散によりドーピング
し、続いてタングステンなどのシリサイド（ＷＳｉ）
（１３ｓ）を積層する。更に、レジスト（Ｒ）をゲート
パターンに形成した後、ＲＩＥをハイパワーで行い、Ｗ
Ｓｉ／ｐ−Ｓｉ層のエッチング終点までエッチングを行
い、その後、図９に示すように、プラズマの高周波放電
出力を低下し、面上のエッチングばらつきによる不要な
エッチング残り膜を根絶するためのオーバーエッチを行
う。なお、ゲート絶縁膜（１２）の形成は、ｐ−Ｓｉ
（１１）の熱酸化により、ｐ−Ｓｉ（１１）上にのみ形
成してもいい。An embodiment for realizing the dry etching method of the present invention will be described below. In addition, here, FIG. 1 and FIG.
The manufacturing method of the present invention will be described by the manufacturing method of the TFT of the first embodiment shown in FIG. 7 to 10 are process cross-sectional views showing the method of manufacturing the thin film transistor of this embodiment. First, in FIG. 7, a p-Si (11) film is formed by thermal CVD on a substrate (10) such as quartz, and this is etched to form islands. Next, as shown in FIG. 8, a gate insulating film (12) is formed by CVD, and then polysilicon (p-Si) is formed by thermal CVD.
After forming (13p), it is doped by ion diffusion, and then silicide such as tungsten (WSi)
(13s) is laminated. Further, after forming a resist (R) on the gate pattern, RIE is performed with high power to perform W
Etching is performed up to the etching end point of the Si / p-Si layer, and then, as shown in FIG. 9, overetching is performed to reduce the high-frequency discharge output of plasma and eradicate unnecessary etching residual film due to etching variations on the surface. I do. The gate insulating film (12) was formed using p-Si.
It may be formed only on p-Si (11) by thermal oxidation of (11).

【００２４】ＲＩＥでは、カソードカップリング方式に
より反応イオンを被エッチング基板付近に集中すること
により、エッチング速度を高めているが、反応イオンを
基板に垂直に加速して被エッチング膜に到達させること
により、エッチングを進めるものであるため、下地への
ダメージが大きい。このため、本発明では、エッチング
終点到達直後に、プラズマの高周波放電出力を低下する
ことで、下地へのダメージを少なくしている。In RIE, the etching rate is increased by concentrating the reaction ions near the substrate to be etched by the cathode coupling method, but by accelerating the reaction ions perpendicularly to the substrate to reach the film to be etched. Since the etching is advanced, the damage to the base is large. Therefore, in the present invention, the high frequency discharge output of the plasma is reduced immediately after reaching the etching end point to reduce damage to the base.

【００２５】次に、図１０に示すように、スペーサ（１
４）となる絶縁層をＣＶＤなどにより被覆して、ＲＩＥ
など異方性ドライエッチを行って、ゲート電極（１３）
の側壁にのみ残しスペーサ（１４）を形成した後、燐
（Ｐ）などの不純物の１回目のイオン注入を低ドーズ量
で行う。この時、燐イオンは、ポリサイドからなるゲー
ト電極（１３）は通過することができず、また、ＣＶＤ
膜からなるスペーサ（１４）は、僅かに通過することが
できる。また、注入されたイオンは横方向にも拡散する
ため、ｐ−Ｓｉ（１１）の島層中、ゲート電極（１３）
直下にはノンドープのチャンネル領域（１１Ｎ）が形成
されるとともに、スペーサ（１４）直下にも極低濃度の
ＶＬＤ領域（１１ＶＬ）が形成される。この時、ソース
及びドレイン領域（１１Ｓ，１１Ｄ）となる領域も低濃
度にドーピングされる。Next, as shown in FIG. 10, spacers (1
4) Cover the insulating layer that will be 4) by CVD, etc.
Anisotropic dry etching is performed, and the gate electrode (13)
After the spacer (14) is formed by leaving only on the side wall of, the first ion implantation of impurities such as phosphorus (P) is performed at a low dose amount. At this time, phosphorus ions cannot pass through the gate electrode (13) made of polycide, and the CVD
The membrane spacer (14) is slightly permeable. Further, since the implanted ions diffuse laterally, the gate electrode (13) is formed in the island layer of p-Si (11).
A non-doped channel region (11N) is formed immediately below, and an extremely low concentration VLD region (11VL) is also formed immediately below the spacer (14). At this time, the regions to be the source and drain regions (11S, 11D) are also lightly doped.

【００２６】続いて図１１に示すように、ゲート電極
（１３）とスペーサ（１４）を含み、かつ、これよりも
大きなパターンのレジスト（Ｒ）を形成した後、２回目
のイオン注入を高ドーズ量で行い、レジスト（Ｒ）直下
にＬＤ領域（１１Ｌ）を残すとともに、高濃度のソース
及びドレイン領域（１１Ｓ，１１Ｄ）を形成する。そし
て、層間絶縁膜（１５）の形成、及び、コンタクトホー
ル（ＣＴ）の形成の後、ソース電極（１６）とドレイン
電極（１７）、及び、それらの配線を形成して図１及び
図２に示すようなＴＦＴが完成する。Subsequently, as shown in FIG. 11, after forming a resist (R) including a gate electrode (13) and a spacer (14) and having a larger pattern than this, a second ion implantation is performed at a high dose. The LD region (11L) is left directly under the resist (R), and high-concentration source and drain regions (11S, 11D) are formed. Then, after the formation of the interlayer insulating film (15) and the formation of the contact hole (CT), the source electrode (16) and the drain electrode (17) and their wirings are formed to form the structure shown in FIGS. The TFT as shown is completed.

【００２７】このように、ゲート電極（１３）のエッチ
ングにおいて、通常のＲＩＥによりメインエッチングを
行ってゲート電極（１３）のパターンを形成した後、エ
ッチング残りの根絶のためのオーバーエッチを、メイン
エッチ時よりも出力を下げて行うことで、下地であるゲ
ート絶縁膜（１２）へダメージを与えることが避けられ
る。これにより欠陥によりチャンネル領域端部にキャリ
アトラップが増えてリーク電流やアバランシェ劣化を招
くといった問題が防がれる。As described above, in the etching of the gate electrode (13), after the main etching is performed by the normal RIE to form the pattern of the gate electrode (13), the overetching for erasing the etching residue is performed by the main etching. By lowering the output as compared with the case, it is possible to avoid damaging the underlying gate insulating film (12). As a result, it is possible to prevent the problem that carrier traps increase at the ends of the channel region due to defects, which causes leakage current and avalanche deterioration.

【００２８】本発明に係るＴＦＴの製造方法として、他
の実施形態を説明する。前述の製造法において、図８及
び図９に示したゲート電極（１３）のエッチングとその
オーバーエッチにおいて、マグネトロン放電を用いたマ
グネトロンエッチングを用いることもできる。マグネト
ロンエッチングは、マグネトロン放電により、プラズマ
を陰極付近に集中させることで、プラズマの発生効率を
良くし、これにより、エッチング速度をより高めるもの
である。この方法も、下地へのダメージが大きく、リー
ク電流やアバランシェ劣化を招くため、本発明では、Ｒ
ＩＥにおけるプラズマパワーを従来よりも低くしたマグ
ネトロンエッチングでゲート電極（１３）を形成するメ
インエッチを行い、かつ、エッチング終点到達後に、マ
グネトロン放電を停止した出力の低いＲＩＥによりオー
バーエッチを行うことで、オーバーエッチ時の下地への
ダメージを防いでいる。Another embodiment will be described as a method of manufacturing a TFT according to the present invention. In the above-described manufacturing method, magnetron etching using magnetron discharge may be used in the etching of the gate electrode (13) and its overetching shown in FIGS. 8 and 9. In the magnetron etching, the plasma is concentrated near the cathode by the magnetron discharge, so that the plasma generation efficiency is improved and thereby the etching rate is further increased. This method also causes large damage to the underlying layer, leading to leakage current and avalanche deterioration.
By performing main etching to form the gate electrode (13) by magnetron etching with a lower plasma power in IE than before, and performing overetching by low power RIE that stopped magnetron discharge after reaching the etching end point, Prevents damage to the base during overetching.

【００２９】[0029]

【発明の効果】本発明により、シリコンゲートを用いた
駆動回路一体型ｐ−ＳｉＴＦＴＬＣＤにおいて、高濃度
のソース領域及びドレイン領域とノンドープのチャンネ
ル領域との間に、複数段階にわたって濃度の異なる領域
を介在させることにより、チャンネル端部における強電
界が緩和される。これにより、ゲート絶縁膜中及びチャ
ンネル領域との界面に欠陥があって、この欠陥において
キャリアトラップが生じても、リーク電流やアバランシ
ェ劣化を抑えることができる。According to the present invention, in a p-SiTFT LCD integrated with a driving circuit using a silicon gate, regions having different concentrations are interposed between a high concentration source region and a drain region and a non-doped channel region. By doing so, the strong electric field at the channel end is relaxed. Accordingly, even if there is a defect in the gate insulating film and the interface with the channel region and a carrier trap is generated in this defect, it is possible to suppress the leakage current and the avalanche deterioration.

【００３０】また、ゲート電極のドライエッチングにお
いて、高周波放電プラズマの出力をエッチング終点到達
後に低下することにより、エッチング残りを根絶するオ
ーバーエッチ時に下地へダメージを与えることが避けら
れる。これにより、ゲート絶縁膜中の欠陥が減少し、キ
ャリアトラップによるリーク電流やアバランシェ劣化が
防がれる。Further, in the dry etching of the gate electrode, the output of the high frequency discharge plasma is lowered after reaching the etching end point, so that damage to the base during overetching to eradicate the etching residue can be avoided. This reduces defects in the gate insulating film and prevents leakage current and avalanche deterioration due to carrier traps.

【００３１】また、マグネトロン放電を用いたゲート電
極のドライエッチングにおいて、エッチング終点到達後
に、マグネトロン放電を停止することにより、エッチン
グ残りを根絶するオーバーエッチ時に下地へダメージを
与えることが防がれ、リーク電流やアバランシェ劣化が
抑えられる。In the dry etching of the gate electrode using magnetron discharge, by stopping the magnetron discharge after reaching the etching end point, it is possible to prevent damage to the base during overetching to eradicate the etching residue, and to prevent leakage. Current and avalanche deterioration are suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施形態にかかるＴＦＴの平面
図である。FIG. 1 is a plan view of a TFT according to a first embodiment of the present invention.

【図２】図１のＡ−Ａ線に沿った断面図である。FIG. 2 is a sectional view taken along line AA of FIG.

【図３】ＶＬＤＤ構造ＴＦＴとＬＤＤ構造ＴＦＴのリー
ク電流との比較図である。FIG. 3 is a comparison diagram of leakage currents of a VLDD structure TFT and an LDD structure TFT.

【図４】本発明の第２の実施形態にかかるＴＦＴの平面
図である。FIG. 4 is a plan view of a TFT according to a second embodiment of the present invention.

【図５】図４のＢ−Ｂ線に沿った断面図である。5 is a cross-sectional view taken along the line BB of FIG.

【図６】ゲート電極のエッチング方式とＴＦＴＯＦＦ電
流との関係図である。FIG. 6 is a relationship diagram between a gate electrode etching method and a TFT OFF current.

【図７】本発明の製造方法にかかる実施形態を示す工程
図である。FIG. 7 is a process drawing showing an embodiment of the manufacturing method of the present invention.

【図８】本発明の製造方法にかかる実施形態を示す工程
図である。FIG. 8 is a process drawing showing an embodiment of the manufacturing method of the present invention.

【図９】本発明の製造方法にかかる実施形態を示す工程
図である。FIG. 9 is a process drawing showing an embodiment of the manufacturing method of the present invention.

【図１０】本発明の製造方法にかかる実施形態を示す工
程図である。FIG. 10 is a process drawing showing the embodiment of the manufacturing method of the present invention.

【図１１】本発明の製造方法にかかる実施形態を示す工
程図である。FIG. 11 is a process drawing showing an embodiment of the manufacturing method of the present invention.

【図１２】液晶表示装置の構成図である。FIG. 12 is a configuration diagram of a liquid crystal display device.

【図１３】従来のＴＦＴの断面図である。FIG. 13 is a cross-sectional view of a conventional TFT.

【図１４】従来の問題点を説明するＴＦＴの断面図であ
る。FIG. 14 is a cross-sectional view of a TFT illustrating a conventional problem.

【符号の説明】[Explanation of symbols]

１０ 基板 １１ ｐ−Ｓｉ １２ ゲート絶縁膜 １３ ゲート電極 １４ スペーサ １５ 層間絶縁膜 １６ ソース電極 １７ ドレイン電極 ＣＴ コンタクトホール 10 substrate 11 p-Si 12 gate insulating film 13 gate electrode 14 spacer 15 interlayer insulating film 16 source electrode 17 drain electrode CT contact hole

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 基板上に島状に形成され不純物を含有し
ないチャンネル領域と該チャンネル領域の両側に不純物
を高濃度に含有したソース及びドレイン領域とからなる
多結晶半導体島層と、該多結晶半導体島層を覆うゲート
絶縁膜と、該ゲート絶縁膜上の前記チャンネル領域上方
に形成され少なくとも多結晶シリコン層からなるゲート
電極と、前記ソース領域に接続するソース電極と、前記
ドレイン領域に接続するドレイン電極とからなる薄膜ト
ランジスタにおいて、 前記ソース領域及びドレイン領域と前記チャンネル領域
との間には、各々不純物を低濃度に含有した低濃度領域
が介在され、この低濃度領域は各々前記ソース及びドレ
イン領域の側から前記チャンネル領域の側へ向かって低
下する不純物濃度勾配を有することを特徴とする薄膜ト
ランジスタ。1. A polycrystalline semiconductor island layer comprising an island-shaped channel region formed on a substrate and containing no impurities, and source and drain regions containing a high concentration of impurities on both sides of the channel region, and the polycrystalline semiconductor island layer. A gate insulating film covering the semiconductor island layer, a gate electrode formed above the channel region on the gate insulating film and made of at least a polycrystalline silicon layer, a source electrode connected to the source region, and a drain region connected to the drain region. In a thin film transistor including a drain electrode, a low-concentration region containing impurities at a low concentration is interposed between the source region and the drain region and the channel region, and the low-concentration regions are the source and drain regions, respectively. The impurity concentration gradient decreasing from the side of the channel region toward the side of the channel region. Transistor. 【請求項２】 前記低濃度領域は各々前記ソース及びド
レイン領域の側から前記チャンネル領域の側へ向かって
複数の中間段階の濃度を経て順次に不純物濃度が低下す
ることを特徴とする薄膜トランジスタ。2. The thin film transistor according to claim 1, wherein the low-concentration region has a plurality of intermediate-stage concentrations from the source and drain regions toward the channel region, and the impurity concentration is sequentially reduced. 【請求項３】 前記ゲート電極の側壁には絶縁性のスペ
ーサが被覆され、このスペーサの直下には、最低の濃度
の前記低濃度領域が形成されていることを特徴とする請
求項２記載の薄膜トランジスタ。3. A sidewall of the gate electrode is covered with an insulating spacer, and the low concentration region having the lowest concentration is formed immediately below the spacer. Thin film transistor. 【請求項４】 前記ゲート電極の側壁はテーパー形状に
形成され、このテーパー部分の直下には、最低の濃度の
前記低濃度領域が形成されていることを特徴とする請求
項１または請求項２記載の薄膜トランジスタ。4. The sidewall of the gate electrode is formed in a tapered shape, and the low concentration region having the lowest concentration is formed immediately below the tapered portion. The thin film transistor described. 【請求項５】 基板上に島状に形成され不純物を含有し
ないチャンネル領域と該チャンネル領域の両側に不純物
を含有したソース及びドレイン領域とからなる多結晶半
導体島層と、該多結晶半導体島層を覆うゲート絶縁膜
と、該ゲート絶縁膜上の前記チャンネル領域上方に形成
され少なくとも多結晶シリコン層からなるゲート電極
と、前記ソース領域に接続するソース電極と、前記ドレ
イン領域に接続するドレイン電極とからなる薄膜トラン
ジスタの製造方法において、 前記多結晶半導体島層と前記ゲート絶縁膜が形成された
前記基板上に、少なくとも前記多結晶シリコン層を積層
し、この上にゲートパターンを有したレジストを形成し
た後、放電プラズマの生成雰囲気中で反応ガスを供給す
ることによりドライエッチングを行って前記ゲート電極
を形成し、エッチング終点において前記放電プラズマの
高周波電力を低下し、その後、オーバーエッチングを行
うことを特徴とする薄膜トランジスタの製造方法。5. A polycrystalline semiconductor island layer comprising an island-shaped channel region formed on a substrate and containing no impurities, and source and drain regions containing impurities on both sides of the channel region, and the polycrystalline semiconductor island layer. A gate insulating film covering the gate insulating film, a gate electrode formed above the channel region on the gate insulating film and made of at least a polycrystalline silicon layer, a source electrode connected to the source region, and a drain electrode connected to the drain region. In the method of manufacturing a thin film transistor, which comprises, on the substrate on which the polycrystalline semiconductor island layer and the gate insulating film are formed, at least the polycrystalline silicon layer is laminated, and a resist having a gate pattern is formed thereon. After that, dry etching is performed by supplying a reactive gas in an atmosphere in which discharge plasma is generated, and Electrode was formed, to reduce the high-frequency power of the discharge plasma in the etching end point, then, a method of manufacturing the thin film transistor and performing overetching. 【請求項６】 基板上に島状に形成され不純物を含有し
ないチャンネル領域と該チャンネル領域の両側に不純物
を含有したソース及びドレイン領域とからなる多結晶半
導体島層と、該多結晶半導体島層を覆うゲート絶縁膜
と、該ゲート絶縁膜上の前記チャンネル領域上方に形成
され少なくとも多結晶シリコン層からなるゲート電極
と、前記ソース領域に接続するソース電極と、前記ドレ
イン領域に接続するドレイン電極とからなる薄膜トラン
ジスタの製造方法において、 前記多結晶半導体島層と前記ゲート絶縁膜が形成された
基板上に、少なくとも前記多結晶シリコン層を積層し、
この上にゲートパターンを有したレジストを形成した
後、放電プラズマの生成雰囲気中でマグネトロン放電を
行うとともに反応ガスを供給することでドライエッチン
グを行って前記ゲート電極を形成し、エッチング終点に
おいて前記マグネトロン放電を停止し、その後、オーバ
ーエッチングを行うことを特徴とする薄膜トランジスタ
の製造方法。6. A polycrystalline semiconductor island layer comprising island-shaped channel regions formed on a substrate and containing no impurities, and source and drain regions containing impurities on both sides of the channel regions, and the polycrystalline semiconductor island layer. A gate insulating film covering the gate insulating film, a gate electrode formed above the channel region on the gate insulating film and made of at least a polycrystalline silicon layer, a source electrode connected to the source region, and a drain electrode connected to the drain region. In the method of manufacturing a thin film transistor comprising, on the substrate on which the polycrystalline semiconductor island layer and the gate insulating film are formed, at least the polycrystalline silicon layer is laminated,
After forming a resist having a gate pattern thereon, magnetron discharge is performed in a discharge plasma generation atmosphere and dry etching is performed by supplying a reaction gas to form the gate electrode, and at the etching end point, the magnetron is discharged. A method for manufacturing a thin film transistor, which comprises stopping discharge and then performing overetching.
JP20460595A 1995-08-10 1995-08-10 Thin film transistor and its manufacture Pending JPH0955508A (en)

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