JPH1197699A - Thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the performance and reliability by forming a gate electrode, such that the outline thereof is confined within the outline of the upper surface of a channel region and connecting the gate electrode with a gate line through a connection electrode provided on a gate electrode via an insulation film. SOLUTION: An array substrate constituting a liquid crystal display comprises a signal line 12 and a gate line 14 formed, in a matrix form on an insulating substrate, i.e., a glass substrate 10, and a pixel electrode 16 is provided in a region surrounded by the signal line and the gate line. A TFT which functions as a switching element is provided in the vicinity of the intersection between the signal line 12 and the gate line 14 which are connected with the pixel electrode 16 via the TFT. According to the arrangement, the breakdown strength of gate insulation film and the threshold voltage are prevented from being lowered which results in a thin-film transistor superior in the electrical characteristics and reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor, and more particularly to a coplanar thin film transistor using polycrystalline silicon as a semiconductor layer.

[0002]

2. Description of the Related Art MOS type field effect transistors (MOS)
An FET is used in a thin film transistor (hereinafter, referred to as a TFT) functioning as a pixel switching element of an active matrix liquid crystal display device, a semiconductor integrated circuit, and the like. In the case of a TFT, polycrystalline silicon or amorphous silicon is often used for a semiconductor layer. Above all, TFTs using polycrystalline silicon for the semiconductor layer generally adopt a coplanar structure, that is, a gate-placed structure, due to the necessity of the polycrystalline silicon manufacturing method.

In a TFT having a gate-on-top structure, a polycrystalline silicon layer is formed on a glass substrate on which an undercoat is formed, and the polycrystalline silicon layer is etched into islands to separate elements. A gate insulating film on the layer,
It has a structure in which gate electrodes are stacked.

[0004]

In such a TFT having a gate-on-top structure, the polycrystalline silicon layer usually has a trapezoidal shape, and the corner of the upper surface of the polycrystalline silicon layer is in contact with the gate insulating film. Has become. Similarly, since the gate electrode is also formed so as to cover the corner of the upper end surface of the polycrystalline silicon layer on the trapezoid via the gate insulating film,
When sweeping the voltage from the negative side to the gate electrode to operate the n-channel TFT element (p-channel TFT
If so, sweep from the positive side), the electric field is locally concentrated between the corner of the channel region of the polycrystalline silicon layer and the gate electrode,
Causes gate insulating film breakdown.

Furthermore, a current flowing between the source and drain regions starts to flow from the upper end of the polycrystalline silicon layer, causing a decrease in the threshold voltage (Vth). These are major factors for deterioration of TFT performance and reliability.

The present invention has been made in view of the above points, and an object of the present invention is to provide a thin film transistor having improved performance and reliability.

[0007]

In order to achieve the above object, a thin film transistor according to the present invention is provided on an insulating substrate and has a channel region, and a source region and a drain region located on both sides of the channel region. A gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film facing the channel region, and formed on the gate insulating film and the gate electrode. An interlayer insulating layer, wherein the gate electrode is formed such that a contour thereof is included inside a contour of an upper surface of the channel region, and is formed on the gate electrode via the insulating film. Is connected to the gate line through the connection electrode provided in the first line.

As described above, by disposing the gate electrode inside the contour of the channel region, it is possible to suppress the occurrence of electric field concentration at the edge of the channel region during TFT driving.

As a result, it is possible to prevent the breakdown of the gate insulating film and the decrease in the threshold voltage due to the electric field concentration at the upper end portion of the semiconductor layer, and to provide a TFT having excellent gate insulating film breakdown resistance and well controlled threshold voltage. Can be obtained.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to the drawings, an embodiment in which a thin film transistor according to the present invention is used as a switching element of a liquid crystal display device will be described in detail.

FIG. 1 shows a part of an array substrate constituting a liquid crystal display device. This array substrate is composed of a signal line 12 and a gate line formed in a matrix on a glass substrate 10 as an insulating substrate. The pixel electrode 16 is provided in a region surrounded by the signal line and the gate line. In the vicinity of the intersection between the signal line 12 and the gate line 14, a TFT 18 functioning as a switching element is provided, and the pixel electrode 16 is connected to the signal line 12 and the gate line 14 via the TFT 18.

As shown in FIG. 1 and FIG.
Is an undercoat layer 2 for preventing diffusion of impurities.
And a semiconductor layer 22 provided on the surface of the glass substrate 10 via the first substrate. The semiconductor layer 22 is formed in a substantially rectangular shape from polycrystalline silicon. This semiconductor layer 22
Has a channel region 22a, and a source region 22b and a drain region 22c located on both sides of the channel region, respectively.

A gate insulating film 23 is formed on the surfaces of the semiconductor layer 22 and the glass substrate 10, and a gate electrode 24 is formed on the gate insulating film 23 so as to face the channel region 22a of the semiconductor layer 22. ing. Further, an interlayer insulating film 26 is formed on the gate electrode 24.

On the interlayer insulating film 26, a source region 22b
A source electrode 28 and a drain electrode 30 are formed facing the drain region 22c, respectively. Then, the source electrode 28 and the drain electrode 30 are connected to the source region 22b and the drain region 22c via contact holes 34 and 36, respectively. Also,
The drain electrode 30 is formed on the I-layer formed on the interlayer insulating film 26.
While being connected to the pixel electrode 16 made of TO,
A passivation 32 is formed to cover the source electrode 22 and the drain electrode 24. In FIG. 1, the interlayer insulating film 26 and the passivation 32 are omitted for simplicity of the drawing.

As shown in FIGS. 1 and 3, the gate electrode 24 is formed in a rectangular shape, and the area thereof is smaller than the area of the channel region 22a of the semiconductor layer 22. The gate electrode 24 has a length substantially equal to the channel length L1 of the semiconductor layer 22, and is formed to have a width shorter than the channel width L2. The gate electrode 24 is formed such that its contour is included inside the contour of the channel region 22a.
The semiconductor layer 22 is disposed to face the semiconductor layer 22 at a position that does not overlap with the corner of the upper end face of “a”.

The gate electrode 24 is formed on the interlayer insulating film 2.
6 is connected to the gate line 14 via a connection electrode 40 formed on the gate electrode 6. That is, one end of the connection electrode 40 is connected to the gate electrode 24 via the contact hole 42, and the other end is connected to the gate line 14 via the contact hole 44.

The TFT 18 having the above configuration is manufactured by the following steps. First, an undercoat layer 20 is formed on a glass substrate 10 in order to prevent impurity diffusion from the substrate. The undercoat layer 20 uses SiO ₂ formed by a chemical vapor reaction method or a sputtering method.
The undercoat layer 20 may further include Si ₃ N ₄ or S
A thin film having a two-layer structure of i ₃ N ₄ and SiO ₂ may be used.

Subsequently, polycrystalline silicon (polysilicon) as the semiconductor layer 22 is formed on the undercoat layer 20. This polysilicon film is formed, for example, by plasma CV.
After an amorphous silicon film is formed by a film forming method such as a D method, an LPCVD method, or a sputtering method, the amorphous silicon film is subjected to laser annealing and polycrystallized.

Further, as another forming method, for example, a method of forming a solid-phase growth of amorphous silicon _(species), by a plasma CVD method or the like SiH 4 · _SiF 4 · _{H 2} as the raw material gas, directly poly A method for forming a silicon film may be used. Note that an amorphous silicon film may be used as the semiconductor layer 22 in addition to the polysilicon film. The amorphous silicon film is formed by a film forming method such as a plasma CVD method, an LPCVD method, and a sputtering method.

Next, the formed polysilicon film is etched into an island shape. Etching is, for example, CF ₄ .O
_This is performed by chemical dry etching (CDE) using _two gases. The etching conditions were as follows: O ₂ / CF ₄ flow ratio: 4,
Etching pressure = 40 (Pa), microwave power supply: 800 (W), substrate temperature: 60 (° C.). Due to such etching, the angle between the surface of the glass substrate 10 and the side surface of the semiconductor layer 22 in the channel width direction is about 30 degrees.
And a trapezoidal polysilicon film is formed.

Subsequently, SiO 2 as the gate insulating film 23 is used.
_{The two} films are made of tetraethylorthosilicate (TEOS)
It is formed by a plasma CVD method using O ₂ as a source gas. Other methods for forming the gate insulating film 23 include a normal pressure CVD method, an LPCVD method, an ECR plasma CVD method,
Another CVD method such as a remote plasma CVD method, a sputtering method, or the like may be used. TE as raw material gas
Instead of the OS-O ₂ gas, SiH ₄ .O ₂ may be used.

After the gate insulating film 23 is formed, annealing may be performed, for example, in a nitrogen atmosphere at 600 ° C. for 5 hours in order to further improve the film quality of the gate insulating film.

Subsequently, an electrode forming layer for forming the gate electrode 24 and the gate line 14 is formed on the gate insulating film 22. As the electrode formation layer, a low-resistance metal such as a molybdenum-tungsten alloy (Mo-W) or aluminum (AI), or polycrystalline silicon into which an impurity is introduced is used.

Next, as shown in FIG. 4, the electrode forming layer is patterned to form a gate line 14 and a gate electrode 24.
a is formed. At this time, the gate electrode 24a has a length in the channel length L1 direction according to the design value of the channel length L1.
The width in the direction of the channel width L2 is formed so as to cover the peripheral corner of the semiconductor layer 22. This is to prevent the impurity from being implanted into the channel width direction end of the semiconductor layer 22 by using the gate electrode 24a as a mask at the time of impurity implantation in the next step.

Then, using the gate electrode 24a as a mask, the semiconductor layer 22 is doped with phosphorus (P) which is an n-type impurity.
Of the source region 22b and the drain region 22
Form c. After that, phosphorus introduced by the above-described ion implantation is activated by annealing such as laser annealing or thermal annealing. When manufacturing a p-type channel TFT, a p-type impurity such as boron (B) is ion-implanted.

Next, as shown in FIG.
a is smaller than the area of the upper end of the semiconductor layer 22 and is shorter than the channel width L2.
Then, a gate electrode 24 separated from the gate line 14 and located only on the semiconductor layer 22 is formed.

Thereafter, an interlayer insulating film 26 is formed on the entire surface,
In the interlayer insulating film 26, contact holes 34, 3 continuous with the source region 22b and the drain region 22c, respectively.
6, and contact holes 42 and 44 continuous with the gate electrode 24 and the gate line 14, respectively.

After a metal film such as Al is formed on the interlayer insulating film 26, the metal film is patterned to form the signal line 12, the source electrode 28 and the drain electrode 3.
0 and the connection electrode 40 are respectively formed. afterwards,
By forming the passivation 32, the TFT 18
Is completed.

The present inventor has proposed a TFT 18 according to the present embodiment having the above-described structure and a conventional n-channel TF.
T (channel width = 9 μm, channel length = 4.5 μm) was fabricated, and the relationship between TFT characteristics and gate withstand voltage and threshold voltage was examined. The results are shown in Table 1 below.

[0030]

[Table 1]

As can be seen from Table 1, the area of the gate electrode formed on the semiconductor layer via the gate insulating film is smaller than the area of the semiconductor layer, and the gate electrode is shorter than the channel width. Thus, as compared with the conventional TFT, the gate withstand voltage was improved, and the decrease in the threshold voltage was suppressed, thereby achieving the original value.

According to the TFT according to the present embodiment configured as described above, the contour of the gate electrode formed on the semiconductor layer via the gate insulating film has the contour of the upper surface of the channel region. Is formed so as to be included in the inside, that is, the area is formed smaller than the area of the channel region, and is provided at a position that does not overlap with the corner of the peripheral edge of the channel region. It is possible to suppress a decrease in gate dielectric breakdown voltage and a decrease in threshold voltage due to electric field concentration occurring at the upper end portion of the semiconductor layer. Thus, a thin-film transistor having excellent electrical characteristics and reliability can be provided.

[0033]

As described above in detail, according to the present invention, in a coplanar thin film transistor using polycrystalline silicon as a semiconductor layer, the gate electrode formed on the semiconductor layer via the gate insulating film has The outline is formed so as to be included inside the outline on the upper surface of the channel region, and the occurrence of electric field concentration at the upper end portion of the semiconductor layer during operation can be suppressed. Thus, it is possible to provide a thin film transistor which prevents gate insulating film breakdown and lowering of the threshold voltage, has excellent gate insulating film breakdown resistance, and has a well-controlled threshold voltage.

[Brief description of the drawings]

FIG. 1 is a plan view of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA in FIG. 1;

FIG. 3 is a sectional view taken along line BB in FIG. 1;

FIG. 4 is a plan view of the thin film transistor during a manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Glass substrate 12 ... Signal line 14 ... Gate line 16 ... Pixel electrode 18 ... TFT 22 ... Semiconductor layer 22a ... Channel region 22b ... Source region 22c ... Drain region 23 ... Gate insulating film 24 ... Gate electrode 26 ... Interlayer insulating film 28 ... Source electrode 30 ... Drain electrode 40 ... Connection electrode

Claims (4)

[Claims] A semiconductor layer provided on an insulating substrate and having a channel region and source and drain regions located on both sides of the channel region; and a gate insulating film formed on the semiconductor layer. And a gate electrode formed on a gate insulating film so as to face the channel region. The gate electrode is formed so that its contour is included inside the contour of the upper surface of the channel region. The thin film transistor, wherein the gate electrode is connected to a gate line by a connection electrode formed on the gate electrode via an interlayer insulating film. 2. The device according to claim 1, wherein said gate electrode has a length substantially equal to a channel length of said channel region and a width shorter than a channel width of said channel region. Thin film transistor. 3. A source electrode and a drain electrode formed on the interlayer insulating layer and connected to the source region and the drain region, respectively, wherein the connection electrode is the same as the source electrode and the drain electrode. The thin film transistor according to claim 1, wherein the thin film transistor is formed by the electrode forming layer. 4. The thin film transistor according to claim 1, wherein said gate electrode is formed of the same layer as said gate line.