JP3171673B2 - Thin film transistor and method of manufacturing the same - Google Patents
Thin film transistor and method of manufacturing the sameInfo
- Publication number
- JP3171673B2 JP3171673B2 JP18933492A JP18933492A JP3171673B2 JP 3171673 B2 JP3171673 B2 JP 3171673B2 JP 18933492 A JP18933492 A JP 18933492A JP 18933492 A JP18933492 A JP 18933492A JP 3171673 B2 JP3171673 B2 JP 3171673B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- thin film
- electrode
- film transistor
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000010408 film Substances 0.000 claims description 86
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 58
- 229920005591 polysilicon Polymers 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 33
- 239000012535 impurity Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 62
- 229910004298 SiO 2 Inorganic materials 0.000 description 14
- 239000011521 glass Substances 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
Description
【０００１】[0001]
【産業上の利用分野】この発明は薄膜トランジスタ及び
その製造方法に関するものであり、特に液晶ディスプレ
イ等の絶縁性基板上に作製される薄膜トランジスタ及び
その製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly to a thin film transistor formed on an insulating substrate such as a liquid crystal display and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、液晶ディスプレイの性能向上はめ
ざましく、特に、絵素毎にダイオードや薄膜トランジス
タ等のスイッチング機能をもたせたアクティブマトリク
ス型液晶ディスプレイは画質の向上、画面サイズの大型
化に大きく貢献している。絵素毎に設けた薄膜トランジ
スタは絶縁性の基板上に、トランジスタの活性層として
非晶質シリコンを用いたものが多く、大面積化が可能で
あり、プロセス温度が低温（〜３５０℃）であるといっ
た長所を有している。2. Description of the Related Art In recent years, the performance of a liquid crystal display has been remarkably improved. In particular, an active matrix type liquid crystal display having a switching function of a diode, a thin film transistor or the like for each picture element greatly contributes to improvement of image quality and enlargement of a screen size. ing. Many thin film transistors provided for each picture element use amorphous silicon as an active layer of a transistor on an insulating substrate, can have a large area, and have a low process temperature (up to 350 ° C.). It has such advantages.
【０００３】また、ポリシリコンを活性層とした薄膜ト
ランジスタも一部に商品化されており、その高移動度特
性を利用して、絵素毎のスイッチングのみならず駆動回
路をも構成しており、駆動回路一体型液晶ディスプレイ
を実現している。しかし、ポリシリコン薄膜トランジス
タは、通常、プロセス温度が高温であるため、ガラス基
板を使用することができず石英基板が使用されている。
石英基板はガラス基板に比べ高価であり、また大面積化
が困難である。したがって、ポリシリコン薄膜トランジ
スタの当面の目標はガラス基板の使用可能な温度（〜６
００℃）で安定した特性の得られるプロセスを開発する
ことにある。Also, thin film transistors using polysilicon as an active layer have been commercialized in part, and by utilizing their high mobility characteristics, not only switching for each pixel but also a driving circuit have been constructed. The drive circuit integrated type liquid crystal display is realized. However, since the process temperature of the polysilicon thin film transistor is usually high, a glass substrate cannot be used and a quartz substrate is used.
Quartz substrates are more expensive than glass substrates, and it is difficult to increase the area. Therefore, the immediate goal of the polysilicon thin film transistor is to set the usable temperature of the glass substrate (〜6
(00 ° C.).
【０００４】[0004]
【発明が解決しようとする課題】前記のようにポリシリ
コン薄膜トランジスタを用いた場合、駆動回路一体型液
晶ディスプレイを実現できることが最大の利点である。
しかし、ポリシリコン薄膜トランジスタのオフ電流は非
晶質シリコン薄膜トランジスタに比べ高いことから、絵
素毎に設けるトランジスタとしては決して適していると
はいえない。When a polysilicon thin film transistor is used as described above, the greatest advantage is that a liquid crystal display integrated with a driving circuit can be realized.
However, since the off-state current of a polysilicon thin film transistor is higher than that of an amorphous silicon thin film transistor, it cannot be said that the transistor is provided as a transistor provided for each picture element.
【０００５】ポリシリコン薄膜トランジスタのオフ電流
の低減方法としてはデュアルゲート構造、ポリシリコン
の薄膜化、ＬＤＤ(Lightly Doped Drain) 構造が考えら
れているがいずれも一長一短がある。デュアルゲート構
造は２個以上のトランジスタを並列に接続し、ゲート電
極を共通にする方法であり、トランジスタをオフしたと
きのドレイン電界を緩和することによってオフ電流を減
少させる。しかし、限られたスペースに２個以上のトラ
ンジスタを形成することは、絵素の開口率の低下につな
がってしまい、望ましくない。As a method of reducing the off-state current of the polysilicon thin film transistor, a dual gate structure, a thinner polysilicon film, and an LDD (Lightly Doped Drain) structure have been considered, all of which have advantages and disadvantages. The dual-gate structure is a method in which two or more transistors are connected in parallel to share a gate electrode, and the off-state current is reduced by relaxing the drain electric field when the transistor is turned off. However, forming two or more transistors in a limited space undesirably leads to a decrease in the pixel aperture ratio.
【０００６】ポリシリコンの薄膜化は非常に簡便な方法
であり薄膜化によりソース、ドレイン間の抵抗を高くす
ることでオフ電流の低減を図る。しかし、期待されるほ
どの低減効果は得られていない。ＬＤＤ(Lightly Doped
Drain) 構造は、例えば、ソース・ドレインがｎ+ 層の
場合、チャネルとソースとの間、およびチャネルとドレ
インとの間にｎ- 層を設けている。これは、図１３に示
すように、通常、ポリシリコン膜２２上にゲート電極２
３を形成したのち、ゲート電極２３をマスクとして低濃
度イオンを注入してｎ- 層２４を形成する（図１３
（ａ））。次にゲート電極２３の側壁にサイドウォール
絶縁体２５を形成した後、再度イオン注入し、ｎ+ 層２
６を形成する（図１３（ｂ））ことで実現される。The thinning of polysilicon is a very simple method, and the off-current is reduced by increasing the resistance between the source and drain by thinning. However, the expected reduction effect has not been obtained. LDD (Lightly Doped
The Drain) structure has, for example, when the source / drain is an n + layer, an n − layer is provided between the channel and the source and between the channel and the drain. This usually means that the gate electrode 2 is formed on the polysilicon film 22 as shown in FIG.
After the formation of the gate electrode 23, low concentration ions are implanted using the gate electrode 23 as a mask to form the n − layer 24 (FIG. 13).
(A)). Next, after a sidewall insulator 25 is formed on the side wall of the gate electrode 23, ion implantation is performed again to form the n + layer 2.
6 (FIG. 13B).
【０００７】また、別の方法として図１４に示すよう
に、ゲート電極３３をマスクとして、斜め回転イオン注
入によりｎ- 層３４を形成した（図１４（ａ））後、通
常のイオン注入法にてｎ+ 層３５を形成する（図１４
（ｂ））。この方法ではｎ- 層３４が深くチャネル領域
に入り込み、ゲートと大きく重なりを有する構造となる
ことから、ゲートオーバーラップＬＤＤ構造と呼ばれて
いる。As another method, as shown in FIG. 14, an n − layer 34 is formed by oblique rotation ion implantation using the gate electrode 33 as a mask (FIG. 14A), and then a normal ion implantation method is performed. To form an n + layer 35 (FIG. 14)
(B)). This method is called a gate overlap LDD structure because the n − layer 34 penetrates deeply into the channel region and has a large overlap with the gate.
【０００８】どちらの構造においてもドレイン電界を緩
和させ耐圧の向上を図ることでオフ電流を減少させる事
ができるが、図１３のＬＤＤ構造ではゲートに電圧を印
加していったときソースｎ- 層の寄生抵抗により電流駆
動能力が低下してしまう。一方、図１４のゲートオーバ
ーラップＬＤＤ構造においてはｎ- 層がゲート電極の下
に存在することにより、電流駆動能力を損なうことがな
い。しかし、いずれの方法にしても、イオン注入を２回
行う必要があることや、サイドウォール絶縁体の形成あ
るいは斜め回転イオン注入など製造工程が複雑になると
いう課題があった。In either structure, the off-current can be reduced by relaxing the drain electric field and improving the breakdown voltage. However, in the LDD structure of FIG. 13, the source n − layer is applied when a voltage is applied to the gate. , The current driving capability is reduced by the parasitic resistance. On the other hand, in the gate overlap LDD structure of FIG. 14, since the n − layer exists below the gate electrode, current driving capability is not impaired. However, any of these methods has a problem that it is necessary to perform ion implantation twice and that the manufacturing process becomes complicated such as formation of a side wall insulator or oblique rotation ion implantation.
【０００９】次に、ガラス基体の使用可能な低温プロセ
スのポリシリコン薄膜トランジスタの問題点について触
れる。薄膜トランジスタは、一般に電界効果トランジス
タであるために、その特性はゲート絶縁層とチャネルと
なる多結晶Ｓｉ膜との界面状態に非常に大きく影響され
る。このため、従来の高温プロセスでは熱酸化法によ
り、ゲート絶縁層とチャネルの界面とをチャネル層内部
に作り込み、界面状態を良好に保っている。これに対
し、低温プロセスでは、ゲート絶縁層も低温で形成する
必要があるため、上記の熱酸化法は使えない。そのた
め、多結晶Ｓｉ膜を所定の形状に加工した後、弗酸等を
用いて表面の清浄化処理を行い、その後スパッタ、ある
いは、ＣＶＤ法等を用いてゲート絶縁膜を形成する方法
が採られているが、界面準位密度の十分な低減には至っ
ていない。Next, the problem of the low-temperature process polysilicon thin film transistor which can use the glass substrate will be described. Since a thin film transistor is generally a field effect transistor, its characteristics are greatly affected by an interface state between a gate insulating layer and a polycrystalline Si film serving as a channel. For this reason, in the conventional high-temperature process, the interface between the gate insulating layer and the channel is formed inside the channel layer by a thermal oxidation method, and the interface state is maintained well. On the other hand, in a low-temperature process, the above-described thermal oxidation method cannot be used because the gate insulating layer also needs to be formed at a low temperature. Therefore, after the polycrystalline Si film is processed into a predetermined shape, a surface cleaning process is performed using hydrofluoric acid or the like, and then a gate insulating film is formed using sputtering, a CVD method, or the like. However, the interface state density has not been sufficiently reduced.
【００１０】そこで、多結晶Ｓｉ膜を成膜した後、大気
にさらさずゲート絶縁膜を連続して成膜する方法が検討
されているが、この方法においては、ゲート絶縁膜およ
び多結晶Ｓｉ膜を所定の形状に加工したときに、多結晶
Ｓｉ膜側面が露出してしまう。そして、その後ゲート電
極を形成した際にゲート電極と露出した多結晶Ｓｉ膜と
の側壁が接し、リーク電流が増大することになるという
問題があった。したがって、ポリシリコンの側壁を絶縁
体で保護する必要があるが、ポリシリコンの側壁を保護
する絶縁体とゲート絶縁膜とが選択的にエッチングでき
ることが必要条件となるため、ゲート絶縁膜、及び側壁
保護のための絶縁体材料が限定されてしまうという問題
があった。Therefore, a method of forming a gate insulating film continuously without exposing it to the atmosphere after forming a polycrystalline Si film has been studied. Is processed into a predetermined shape, the side surface of the polycrystalline Si film is exposed. Then, when the gate electrode is formed thereafter, there is a problem that the side wall of the gate electrode and the exposed polycrystalline Si film come into contact with each other, and the leakage current increases. Therefore, it is necessary to protect the side wall of the polysilicon with an insulator. However, since the insulator for protecting the side wall of the polysilicon and the gate insulating film must be selectively etched, the gate insulating film and the side wall are required. There is a problem that the insulator material for protection is limited.
【００１１】この発明は上記のような問題点に鑑みてな
されたもので、ガラス基板の使用可能な低温プロセスに
おいても理想的な製造方法であるとともに、オフ電流を
低減するための最良の方法であるゲートオーバーラップ
ＬＤＤ構造を比較的容易に実現することができる薄膜ト
ランジスタ及びその製造方法を提供することを目的とし
ている。The present invention has been made in view of the above-mentioned problems, and is an ideal manufacturing method even in a low-temperature process in which a glass substrate can be used, and a best method for reducing off-current. An object of the present invention is to provide a thin film transistor and a method for manufacturing the same, which can relatively easily realize a certain gate overlap LDD structure.
【００１２】[0012]
【課題を解決するための手段】上記の目的を達成するた
め、この発明によれば、絶縁性基板上に、トランジスタ
の活性層となるポリシリコン層、ゲート絶縁膜及びゲー
ト電極が順次形成されてなる薄膜トランジスタであっ
て、前記ゲート絶縁膜上に形成されるゲート電極は、上
層ゲート電極と下層ゲート電極との２層構造からなると
ともに、前記上層ゲート電極と前記下層ゲート電極とが
異なる電極幅により構成され、前記ゲート絶縁膜下に形
成されるポリシリコン層は、前記２層構造からなるゲー
ト電極がマスクとなって形成される不純物拡散領域を有
しており、前記ポリシリコン層と前記ゲート絶縁膜とか
らなる積層パターンの側壁には、絶縁体が形成されてい
る薄膜トランジスタが提供される。According to the present invention, a polysilicon layer to be an active layer of a transistor, a gate insulating film, and a gate electrode are sequentially formed on an insulating substrate. Wherein the gate electrode formed on the gate insulating film has a two-layer structure of an upper gate electrode and a lower gate electrode, and the upper gate electrode and the lower gate electrode have different electrode widths. The polysilicon layer formed under the gate insulating film has an impurity diffusion region formed by using the gate electrode having the two-layer structure as a mask, and the polysilicon layer and the gate insulating film are formed. There is provided a thin film transistor in which an insulator is formed on a side wall of a stacked pattern including a film.
【００１３】また、上記目的を達成するため、絶縁性基
板上に、トランジスタの活性層となるポリシリコン層、
ゲート絶縁膜及びゲート電極が形成された薄膜トランジ
スタの製造方法であって、前記絶縁性基板上に、前記ポ
リシリコン層からなるトランジスタの活性層と、前記ゲ
ート絶縁膜と、下層ゲート電極とをそれぞれ順次形成
し、該３層の膜を同一のレジストパターンによりエッチ
ングして島状パターンに加工する工程と、前記下層ゲー
ト電極を所定の形状にパターニングする工程と、前記下
層ゲート電極上に上層ゲート電極を成膜し、該上層ゲー
ト電極を前記下層ゲート電極の電極幅とは異なる幅の所
定の形状にパターニングする工程と、前記下層ゲート電
極及び上層ゲート電極をマスクとして、不純物イオンを
前記ポリシリコン層に注入して、不純物拡散領域を形成
する工程とを含む薄膜トランジスタの製造方法が提供さ
れる。In order to achieve the above object, a polysilicon layer serving as an active layer of a transistor is provided on an insulating substrate,
A method for manufacturing a thin film transistor in which a gate insulating film and a gate electrode are formed, wherein an active layer of the transistor made of the polysilicon layer, the gate insulating film, and a lower gate electrode are sequentially formed on the insulating substrate. Forming, etching the three layers with the same resist pattern to form an island pattern, patterning the lower gate electrode into a predetermined shape, and forming an upper gate electrode on the lower gate electrode. Forming a film, patterning the upper gate electrode into a predetermined shape having a width different from the electrode width of the lower gate electrode, and using the lower gate electrode and the upper gate electrode as a mask to deposit impurity ions on the polysilicon layer. Implanting to form an impurity diffusion region.
【００１４】この発明における絶縁性基板とは、通常薄
膜トランジスタに用いられる基板であれば特に限定され
るものではなく、ガラス基板、石英基板等を用いること
ができる。そして、この絶縁性基板上に直接、あるいは
基板からの不純物の拡散を防止するために窒化膜等の絶
縁膜を５００〜３０００Å程度積層した上に、薄膜トラ
ンジスタの活性層となるポリシリコン膜を形成する。こ
のポリシリコンは、公知の方法、例えば、ＣＶＤ法によ
り、４００〜６００℃でシランガス等を用いて非晶質の
シリコン膜を形成したのち、真空中あるいは不活性ガス
雰囲気中で、５００〜６００℃、数時間アニールを行う
ことにより形成することができる。また、石英基板等を
使った高温プロセスにおいても同様に行うことができ
る。この際のポリシリコンの膜厚は５００〜１５００Å
程度が好ましい。また、ゲート絶縁膜として形成される
膜は、トランジスタ特性に悪影響を及ぼさない範囲で種
々選択することができるが、ＳｉＯ2 膜が好ましい。Ｓ
ｉＯ2 膜は公知の方法、例えば、ＣＶＤ法により形成す
ることができる。この際のＳｉＯ2 膜の膜厚は５００〜
１５００Å程度が好ましい。なお、絶縁性基板上に非晶
質シリコンを形成する工程からゲート絶縁膜を成膜する
までの工程は、外気に曝されることなく、真空中あるい
は不活性ガス雰囲気中に保持して行うことが好ましい。The insulating substrate in the present invention is not particularly limited as long as it is a substrate usually used for a thin film transistor, and a glass substrate, a quartz substrate or the like can be used. Then, a polysilicon film to be an active layer of the thin film transistor is formed on an insulating film such as a nitride film on the insulating substrate directly or on a layer of about 500 to 3000 ° to prevent diffusion of impurities from the substrate. . After forming an amorphous silicon film using a silane gas or the like at 400 to 600 ° C. by a known method, for example, a CVD method, the polysilicon is formed at 500 to 600 ° C. in a vacuum or an inert gas atmosphere. Can be formed by performing annealing for several hours. Further, it can be similarly performed in a high-temperature process using a quartz substrate or the like. At this time, the thickness of the polysilicon is 500 to 1500 °.
The degree is preferred. Further, the film formed as the gate insulating film can be variously selected within a range that does not adversely affect the transistor characteristics, but an SiO 2 film is preferable. S
The iO 2 film can be formed by a known method, for example, a CVD method. At this time, the thickness of the SiO 2 film is 500 to
It is preferably about 1500 °. Note that the steps from the step of forming amorphous silicon over the insulating substrate to the step of forming the gate insulating film must be performed in a vacuum or an inert gas atmosphere without being exposed to the outside air. Is preferred.
【００１５】また、この発明における薄膜トランジスタ
のゲート電極は下層及び上層の２層構造からなってお
り、上層ゲート電極と下層ゲート電極との電極幅は同一
幅を有していない。つまり、上層ゲート電極が下層ゲー
ト電極より大きな電極幅を有しているか、あるいは下層
ゲート電極が上層ゲート電極より大きな電極幅を有して
いるものである。しかし、下層ゲート電極の電極幅が上
層ゲート電極の電極幅より大きい場合には、上層ゲート
電極を加工する際、下層ゲート電極の一部が露出するこ
ととなるので、エッチング時間を精度よく管理しないと
下層ゲート電極をエッチングしてしまうという問題が生
じるが、下層ゲート電極の方が上層ゲート電極の電極幅
より小さい場合には上記のような問題が防止されるとう
いう点から、上層ゲート電極が下層ゲート電極より大き
な電極幅を有している方が好ましい。なお、これらゲー
ト電極の電極幅は作製する薄膜トランジスタの大きさに
依存しており、特に限定されるものではない。また、下
層ゲート電極及び上層ゲート電極は、それぞれ各種メタ
ルあるいはポリシリコン膜等、トランジスタ特性に悪影
響を及ぼさない範囲で種々選択することができるが、ポ
リシリコンの場合はソース・ドレイン形成のイオン注入
時に同時にイオン注入することによってゲート電極とす
ることが出来る。ポリシリコンは、公知の方法、例え
ば、シランガスを用いたＣＶＤ法で形成することができ
る。The gate electrode of the thin film transistor according to the present invention has a two-layer structure of a lower layer and an upper layer, and the upper gate electrode and the lower gate electrode do not have the same width. That is, the upper gate electrode has a larger electrode width than the lower gate electrode, or the lower gate electrode has a larger electrode width than the upper gate electrode. However, when the electrode width of the lower gate electrode is larger than the electrode width of the upper gate electrode, a part of the lower gate electrode is exposed when the upper gate electrode is processed, so that the etching time is not precisely controlled. However, when the lower gate electrode is smaller than the electrode width of the upper gate electrode, the above-described problem is prevented. It is preferable to have a larger electrode width than the lower gate electrode. Note that the electrode width of these gate electrodes depends on the size of a thin film transistor to be manufactured, and is not particularly limited. The lower gate electrode and the upper gate electrode can be variously selected from various metals and polysilicon films, respectively, as long as they do not adversely affect the transistor characteristics. A gate electrode can be formed by ion implantation at the same time. Polysilicon can be formed by a known method, for example, a CVD method using silane gas.
【００１６】この発明においては、絶縁性基板上にポリ
シリコン層、ゲート絶縁膜及び下層ゲート電極を順次形
成したのち、同一のレジストパターンを用いて、これら
３層構造を同時にエッチングして島状のパターンに形成
する。この場合のエッチングは公知の方法により、それ
ぞれエッチングすることができるが、各層のエッチング
後の断面形状が基板に対して垂直になるように、異方性
エッチングによりパターニングすることが好ましい。ま
た、これらパターニングされた３層構造の側壁には絶縁
体のサイドウォールが形成されている。このサイドウォ
ールは、公知の絶縁膜、例えば、ＳｉＯ2 膜を３０００
〜８０００Å程度積層し、異方性エッチングによるよう
な、公知の方法により形成することができる。According to the present invention, a polysilicon layer, a gate insulating film, and a lower gate electrode are sequentially formed on an insulating substrate, and then, using the same resist pattern, these three-layer structures are simultaneously etched to form an island shape. Form into a pattern. In this case, etching can be performed by a known method. However, it is preferable to perform patterning by anisotropic etching so that the cross-sectional shape of each layer after the etching is perpendicular to the substrate. Insulating sidewalls are formed on the sidewalls of the patterned three-layer structure. This sidewall is made of a known insulating film, for example, a SiO 2 film of 3000.
It can be formed by laminating about 8000 ° and a known method such as by anisotropic etching.
【００１７】また、この発明においては、下層ゲート電
極のみを所定の形状に加工し、さらに下層ゲート電極上
に上層ゲート電極を成膜、加工した後、下層及び上層ゲ
ート電極をマスクにして不純物イオンをポリシリコン層
に注入して、不純物拡散領域を形成する。In the present invention, only the lower gate electrode is processed into a predetermined shape, an upper gate electrode is formed on the lower gate electrode, processed, and then the impurity ions are formed using the lower and upper gate electrodes as a mask. Is implanted into the polysilicon layer to form an impurity diffusion region.
【００１８】[0018]
【作用】上記のような構造及び方法においては、ゲート
電極が上層ゲート電極及び下層ゲート電極の２層構造か
らなり、かつ上層ゲート電極の電極幅と下層ゲート電極
の電極幅とが同一幅でないので、上層及び下層ゲート電
極をマスクに不純物イオンを注入することで、ゲートオ
ーバーラップＬＤＤ構造が容易に形成される。In the above structure and method, the gate electrode has a two-layer structure of an upper gate electrode and a lower gate electrode, and the electrode width of the upper gate electrode is not the same as the electrode width of the lower gate electrode. By implanting impurity ions using the upper and lower gate electrodes as a mask, a gate overlap LDD structure can be easily formed.
【００１９】また、トランジスタの活性層となるポリシ
リコン層、ゲート絶縁膜及び下層ゲート電極を順次連続
して成膜するので、ポリシリコン層とゲート絶縁膜との
界面が常に安定で良好な状態が保たれる。さらに、ポリ
シリコン層、ゲート絶縁膜及び下層ゲート電極の積層膜
の上面が下層ゲート電極材料となっているので、パター
ニングされた３層構造の積層膜の側壁に絶縁体を形成す
るためのエッチング加工の際、特にゲート絶縁膜との選
択的なエッチングを必要とせず、容易に形成することが
できる。Further, since the polysilicon layer serving as the active layer of the transistor, the gate insulating film and the lower gate electrode are sequentially formed, the interface between the polysilicon layer and the gate insulating film is always stable and good. Will be kept. Further, since the upper surface of the laminated film of the polysilicon layer, the gate insulating film, and the lower gate electrode is a lower gate electrode material, an etching process for forming an insulator on the side wall of the patterned three-layer laminated film. In this case, it is possible to form the gate insulating film easily without requiring selective etching with the gate insulating film.
【００２０】[0020]
【実施例】この発明に係わる薄膜トランジスタの実施例
を図面に基づいて説明する。 実施例１ 図１は薄膜トランジスタの一実施例を示しており、
（ａ）は平面図、（ｂ）はＡ−Ａ線断面図、（ｃ）はＢ
−Ｂ線断面図である。この薄膜トランジスタは、ガラス
基板１上にＳｉＮ膜２、ポリシリコン層３及びＳｉＯ2
膜４が順次積層されて構成されており、ＳｉＯ2 膜４上
に下層ゲート電極５が形成されており、下層ゲート電極
５上に下層ゲート電極５幅よりも小さい幅を有する上層
ゲート電極７が形成されている。そして、チャネル部と
なるポリシリコン層３には自己整合的にＬＤＤ構造を有
する不純物拡散領域１０が形成されており、不純物拡散
領域１０にメタル電極配線９が接続されて、薄膜トラン
ジスタが形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a thin film transistor according to the present invention will be described with reference to the drawings. Embodiment 1 FIG. 1 shows an embodiment of a thin film transistor.
(A) is a plan view, (b) is a sectional view taken along line AA, (c) is B
FIG. 4 is a cross-sectional view taken along line B. This thin film transistor is composed of a SiN film 2, a polysilicon layer 3 and a SiO 2 film on a glass substrate 1.
The lower gate electrode 5 is formed on the SiO 2 film 4. The upper gate electrode 7 having a width smaller than the width of the lower gate electrode 5 is formed on the lower gate electrode 5. Is formed. An impurity diffusion region 10 having an LDD structure is formed in a self-aligned manner in the polysilicon layer 3 serving as a channel portion, and a metal electrode wiring 9 is connected to the impurity diffusion region 10 to form a thin film transistor. .
【００２１】以下に、上記の薄膜トランジスタの製造方
法を図面に基づいて説明する。まず、図２に示したよう
に、ガラス基板１上にガラスからの不純物の拡散を防ぐ
ためにＳｉＮ膜２を約３０００Å堆積させた後、その上
にプラズマＣＶＤ装置にて非晶質シリコン膜を成膜す
る。成膜条件は基板温度４００〜６００℃でＨ2希釈さ
れたＳｉＨ4 ガスを熱とプラズマとで分解し、約１００
０Å堆積させる。次に非晶質シリコン膜を多結晶化する
ため、真空中にて約６００℃で１時間のアニールを行
い、ポリシリコン膜３とする。続いて、減圧ＣＶＤ装置
にてゲート絶縁膜となるＳｉＯ2 膜４を約１０００Å成
膜する。以上の非晶質シリコン膜の成膜からゲート絶縁
膜の成膜までの工程において、プラズマＣＶＤ装置から
アニール炉、及びアニール炉から減圧ＣＶＤ装置へのガ
ラス基板１の移動は真空で保持されたロードロック室を
介して行っている。次に、減圧ＣＶＤ装置にて下層ゲー
ト電極５となるポリシリコン膜を約１５００Å成膜す
る。Hereinafter, a method of manufacturing the above thin film transistor will be described with reference to the drawings. First, as shown in FIG. 2, an SiN film 2 is deposited on a glass substrate 1 for about 3000.degree. To prevent diffusion of impurities from glass, and then an amorphous silicon film is formed thereon by a plasma CVD apparatus. Film. The film formation conditions are as follows: SiH 4 gas diluted with H 2 at a substrate temperature of 400 to 600 ° C. is decomposed by heat and plasma, and is heated to about
Deposit 0 °. Next, in order to polycrystallize the amorphous silicon film, annealing is performed at about 600 ° C. for 1 hour in a vacuum to form a polysilicon film 3. Subsequently, an SiO 2 film 4 serving as a gate insulating film is formed to a thickness of about 1000 ° by a low pressure CVD apparatus. In the steps from the formation of the amorphous silicon film to the formation of the gate insulating film, the movement of the glass substrate 1 from the plasma CVD apparatus to the annealing furnace and from the annealing furnace to the reduced-pressure CVD apparatus is performed by a load maintained in vacuum. Going through the lock room. Next, a polysilicon film to be the lower gate electrode 5 is formed by a reduced pressure CVD apparatus at about 1500 °.
【００２２】次いで、図３に示したように、窒化シリコ
ン膜２上のポリシリコン層３、ＳｉＯ2 膜４及び下層ゲ
ート電極５の３層の膜を同一のレジストパターンでエッ
チングし、島状パターンに加工する。各層のエッチング
は反応性イオンエッチャーを用い、エッチングした後の
断面形状がガラス基板１に対し垂直となるように異方性
エッチングを行っている。尚、ポリシリコン層３のエッ
チングにはＳＦ6 とＣＣｌ4 との混合ガスを、ＳｉＯ2
膜４のエッチングにはＣＨＦ3 をそれぞれエッチングガ
スとして用いた。Next, as shown in FIG. 3, the three layers of the polysilicon layer 3, the SiO 2 film 4 and the lower gate electrode 5 on the silicon nitride film 2 are etched with the same resist pattern to form an island pattern. Process into The etching of each layer is performed using a reactive ion etcher, and anisotropic etching is performed so that the cross-sectional shape after the etching is perpendicular to the glass substrate 1. Note that a mixed gas of SF 6 and CCl 4 is used for etching the polysilicon layer 3 by using SiO 2.
CHF 3 was used as an etching gas for etching the film 4.
【００２３】次に、図４に示したように、ガラス基板１
全面にスパッタ装置にてＳｉＯ2 膜６を約５０００Å成
膜する。その後、反応成イオンエッチャーにてＣＨＦ3
を反応性ガスとして用い、図５に示したように、ＳｉＯ
2 膜６が島状パターンの側壁のみに残存するように異方
性エッチングを行う。エッチングの終点はエッチングが
進行し、窒化シリコン膜２が露出したことをプラズマ分
析により知ることで検知が可能である。Next, as shown in FIG.
An SiO 2 film 6 is formed on the entire surface by a sputtering device at about 5000 °. After that, CHF 3 was used in the reaction ion etcher.
Is used as a reactive gas, and as shown in FIG.
Anisotropic etching is performed so that the two films 6 remain only on the side walls of the island pattern. The end point of the etching can be detected by knowing that the silicon nitride film 2 has been exposed by the progress of the etching and the plasma analysis.
【００２４】その後、図６に示したように、下層ゲート
電極５を反応性イオンエッチャーにて、所定の形状に加
工する。この際、下層ゲート電極５の電極幅（図６
（ｂ）中、トランジスタ長：Ｌ）を５μｍとした。その
後、図７に示したように、下層ゲート電極５を含むガラ
ス基板１全面に、減圧ＣＶＤ装置にて上層ゲート電極７
となるポリシリコン膜を約１５００Å成膜する。Thereafter, as shown in FIG. 6, the lower gate electrode 5 is processed into a predetermined shape by a reactive ion etcher. At this time, the electrode width of the lower gate electrode 5 (FIG. 6)
(B), (transistor length: L) was set to 5 μm. Thereafter, as shown in FIG. 7, the upper gate electrode 7 is formed on the entire surface of the glass substrate 1 including the lower gate electrode 5 by a low pressure CVD apparatus.
A polysilicon film having a thickness of about 1500 ° is formed.
【００２５】次いで、図８に示したように、下層ゲート
電極５の電極幅の中心線を同一として、上層ゲート電極
７の電極幅（図８（ｂ）中、トランジスタ長：Ｍ）を３
μｍに加工する。次に、図９に示したように、プラズマ
イオンドーピング装置にて水素ガスで希釈されたＰＨ3
ガスを用いてプラズマを形成し、Ｐ（リン）イオンを注
入して、ゲート電極６に高濃度領域を形成するととも
に、ポリシリコン膜にＬＤＤ構造を有する不純物拡散領
域１０を形成する。Next, as shown in FIG. 8, the electrode width of the upper gate electrode 7 (transistor length: M in FIG. 8B) is set to 3 with the center line of the electrode width of the lower gate electrode 5 being the same.
Process to μm. Next, as shown in FIG. 9, PH 3 diluted with hydrogen gas was used in a plasma ion doping apparatus.
Plasma is formed using a gas, and P (phosphorus) ions are implanted to form a high concentration region in the gate electrode 6 and to form an impurity diffusion region 10 having an LDD structure in the polysilicon film.
【００２６】その後、図１０に示したように、層間絶縁
膜となるＳｉＯ2 膜１１を約５０００Å成膜し、不純物
拡散領域１０となる部分にコンタクトホールを形成した
後、メタル配線９を形成してＮ型の薄膜トランジスタを
作製する。このように作製した薄膜トランジスタのＰイ
オンの濃度分布を図１１に示す。図１１に示したよう
に、直上にゲート電極６の存在しない不純物拡散領域１
０となる部分のポリシリコン層３には、充分な濃度のＰ
イオンが注入されて、ｎ+領域となっている。一方、下
層ゲート電極５のみが直上に存在するポリシリコン層３
には高濃度の不純物拡散領域１０に比べ、約２桁少ない
量のＰイオンが注入されて、ｎ- 領域となっている。ま
た、上層ゲート電極７及び下層ゲート電極５の両方が直
上に存在するポリシリコン層３にはほとんどＰイオンは
到達していなかった。Thereafter, as shown in FIG. 10, an SiO 2 film 11 serving as an interlayer insulating film is formed to a thickness of about 5000.degree., A contact hole is formed in a portion serving as the impurity diffusion region 10, and a metal wiring 9 is formed. To manufacture an N-type thin film transistor. FIG. 11 shows the concentration distribution of P ions in the thin film transistor thus manufactured. As shown in FIG. 11, the impurity diffusion region 1 where the gate electrode 6 does not exist immediately above
In the portion of the polysilicon layer 3 which becomes 0, a sufficient concentration of P
The ions are implanted to form an n + region. On the other hand, the polysilicon layer 3 on which only the lower gate electrode 5 exists directly
P ions are implanted about two orders of magnitude less than the high concentration impurity diffusion region 10 to form an n − region. Further, P ions hardly reached the polysilicon layer 3 on which both the upper gate electrode 7 and the lower gate electrode 5 exist directly.
【００２７】従って、この薄膜トランジスタは上層ゲー
ト電極７及び下層ゲート電極５の電極幅を同一の３μｍ
とした場合の薄膜トランジスタと比較して、オフ電流が
約２桁低減できた。また、オン時のドレイン電流の駆動
能力は同程度であった。 実施例２ 実施例１と同様の方法により、活性層となるポリシリコ
ン層３、ゲート絶縁膜であるＳｉＯ2 膜４及び下層ゲー
ト電極１５となるポリシリコン膜の３層膜を島状パター
ンに加工し、その島状パターンの側壁にＳｉＯ2 膜６の
絶縁体を形成する。実施例２においては下層ゲート電極
１５の電極幅（Ｌ）を３μｍに加工した後、上層ゲート
電極１７となるポリシリコン膜を成膜し、下層ゲート電
極１５の電極幅の中心線を同一にして、上層ゲート電極
１７の電極幅（Ｍ）を５μｍに加工する。そして、実施
例１と同様の方法で図１２に示す、薄膜トランジスタを
作製した。Therefore, in this thin film transistor, the upper gate electrode 7 and the lower gate electrode 5 have the same electrode width of 3 μm.
The off-state current was reduced by about two orders of magnitude as compared with the thin film transistor in the case where In addition, the driving capability of the drain current at the time of ON was almost the same. Example 2 A three-layer film of a polysilicon layer 3 serving as an active layer, a SiO 2 film 4 serving as a gate insulating film, and a polysilicon film serving as a lower gate electrode 15 was processed into an island pattern by the same method as in the first embodiment. Then, an insulator of the SiO 2 film 6 is formed on the side wall of the island pattern. In Example 2, after processing the electrode width (L) of the lower gate electrode 15 to 3 μm, a polysilicon film serving as the upper gate electrode 17 is formed, and the center line of the electrode width of the lower gate electrode 15 is made the same. Then, the electrode width (M) of the upper gate electrode 17 is processed to 5 μm. Then, a thin film transistor shown in FIG. 12 was produced in the same manner as in Example 1.
【００２８】このように作製された薄膜トランジスタの
オフ電流も実施例１と同等の約２桁の低減効果が認めら
れた。以上の実施例１、及び２のように上層ゲート電極
と下層ゲート電極のそれぞれの電極幅を異ならせた形状
としたうえで、イオン注入を施すことによりゲートオー
バーラップＬＤＤが実現されるため、オン電流の駆動能
力を損なうことなくオフ電流の低減を図ることができ
た。The off-state current of the thin film transistor thus manufactured was also reduced by about two orders of magnitude, which was equivalent to that of Example 1. Since the upper gate electrode and the lower gate electrode are formed to have different electrode widths as in Examples 1 and 2 described above and then subjected to ion implantation, the gate overlap LDD is realized. The off-state current can be reduced without impairing the current driving capability.
【００２９】[0029]
【発明の効果】上記のようにこの発明の薄膜トランジス
タ及びその製造方法においては、ゲート電極が上層ゲー
ト電極及び下層ゲート電極の２層構造からなり、かつ上
層ゲート電極の電極幅と下層ゲート電極の電極幅とが同
一幅でないので、上層及び下層ゲート電極をマスクに不
純物イオンを１回注入することで、ゲートオーバーラッ
プＬＤＤ構造を容易に形成することができる。従って、
イオン電流の駆動能力を損なうことなく、オフ電流の低
減化を実現することができた。As described above, in the thin film transistor and the method of manufacturing the same according to the present invention, the gate electrode has a two-layer structure of an upper gate electrode and a lower gate electrode, and the electrode width of the upper gate electrode and the electrode of the lower gate electrode. Since the width is not the same, the gate overlap LDD structure can be easily formed by implanting impurity ions once using the upper and lower gate electrodes as a mask. Therefore,
It was possible to reduce the off-state current without impairing the driving capability of the ion current.
【００３０】また、トランジスタの活性層となるポリシ
リコン層、ゲート絶縁膜、及び下層ゲート電極を順次連
続して成膜するので、ポリシリコン層とゲート絶縁膜と
の界面を常に安定に良好な状態で、薄膜トランジスタを
製造することができる。従って、６００℃以下の低温プ
ロセスにおいても高性能なトランジスタ特性を安定して
得ることができる。Further, since the polysilicon layer serving as the active layer of the transistor, the gate insulating film, and the lower gate electrode are successively formed sequentially, the interface between the polysilicon layer and the gate insulating film is always kept in a stable state. Thus, a thin film transistor can be manufactured. Therefore, high-performance transistor characteristics can be stably obtained even in a low-temperature process of 600 ° C. or lower.
【００３１】さらに、ポリシリコン層、ゲート絶縁膜及
び下層ゲート電極の積層膜の上面が下層ゲート電極材料
となっているので、パターニングされた３層構造の積層
膜の側壁に絶縁体を形成するためのエッチング加工の
際、特にゲート絶縁膜との選択的なエッチングを必要と
せず、薄膜トランジスタの製造工程を簡略化することが
できる。Further, since the upper surface of the laminated film of the polysilicon layer, the gate insulating film, and the lower gate electrode is a lower gate electrode material, an insulator is formed on the side wall of the patterned three-layer laminated film. In the case of the etching process, selective etching of the gate insulating film is not particularly required, so that the manufacturing process of the thin film transistor can be simplified.
【図１】この発明に係わる薄膜トランジスタの一実施例
を示す要部の概略平面図、概略断面図である。FIG. 1 is a schematic plan view and a schematic cross-sectional view of a main part showing an embodiment of a thin film transistor according to the present invention.
【図２】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 2A and 2B are schematic cross-sectional views of a main part showing a manufacturing process in Example 1, wherein FIG. 2A is a cross-sectional view taken along line AA of FIG. 1 and FIG. 2B is a cross-sectional view taken along line BB of FIG. .
【図３】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 3A and 3B are schematic cross-sectional views of a main part showing a manufacturing process in Example 1, wherein FIG. 3A is a cross-sectional view taken along line AA of FIG. 1 and FIG. 3B is a cross-sectional view taken along line BB of FIG. .
【図４】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 4A and 4B are schematic cross-sectional views of main parts showing a manufacturing process of Example 1, wherein FIG. 4A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 4B is a cross-sectional view taken along line BB of FIG. .
【図５】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 5A and 5B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1, wherein FIG. 5A is a cross-sectional view taken along line AA of FIG. 1 and FIG. 5B is a cross-sectional view taken along line BB of FIG. .
【図６】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 6A and 6B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1. FIG. 6A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 6B is a cross-sectional view taken along line BB of FIG. .
【図７】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 7A and 7B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1. FIG. 7A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 7B is a cross-sectional view taken along line BB of FIG. .
【図８】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 8A and 8B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1. FIG. 8A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 8B is a cross-sectional view taken along line BB of FIG. .
【図９】実施例１の製造工程を示す要部の概略断面図で
あり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１の
Ｂ−Ｂ線断面図である。FIGS. 9A and 9B are schematic cross-sectional views of a main part showing a manufacturing process in Example 1, where FIG. 9A is a cross-sectional view taken along line AA of FIG. 1 and FIG. 9B is a cross-sectional view taken along line BB of FIG. .
【図１０】実施例１の製造工程を示す要部の概略断面図
であり、（ａ）は図１のＡ−Ａ線断面図、（ｂ）は図１
のＢ−Ｂ線断面図である。FIGS. 10A and 10B are schematic cross-sectional views of a main part showing a manufacturing process in Example 1, wherein FIG. 10A is a cross-sectional view taken along line AA of FIG.
FIG. 7 is a sectional view taken along line BB of FIG.
【図１１】実施例１における薄膜トランジスタの、Ｐイ
オン注入後のＰイオン濃度分布を示す図である。FIG. 11 is a diagram showing a P ion concentration distribution of a thin film transistor in Example 1 after P ion implantation.
【図１２】この発明に係わる薄膜トランジスタの別の実
施例を示す要部の概略平面図、概略断面図である。FIG. 12 is a schematic plan view and a schematic sectional view of a main part showing another embodiment of the thin film transistor according to the present invention.
【図１３】従来のＬＤＤ(Lightly Doped Drain) 構造を
有する薄膜トランジスタの製造方法を説明するための概
略断面図である。FIG. 13 is a schematic cross-sectional view for explaining a method of manufacturing a thin film transistor having a conventional LDD (Lightly Doped Drain) structure.
【図１４】従来のゲートオーバラップＬＤＤ構造を有す
る薄膜トランジスタの製造方法を説明するための概略断
面図である。FIG. 14 is a schematic cross-sectional view for explaining a method for manufacturing a conventional thin film transistor having a gate overlap LDD structure.
【符号の説明】 １ ガラス基板（絶縁性基板） ３ ポリシリコン層 ４ ＳｉＯ2 膜（ゲート絶縁膜） ５ 下層ゲート電極 ６ ＳｉＯ2 膜（絶縁体） ７ 上層ゲート電極 ８ ゲート電極 １０ 不純物拡散領域DESCRIPTION OF SYMBOLS 1 Glass substrate (insulating substrate) 3 Polysilicon layer 4 SiO 2 film (gate insulating film) 5 Lower gate electrode 6 SiO 2 film (insulator) 7 Upper gate electrode 8 Gate electrode 10 Impurity diffusion region
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−159730（ＪＰ，Ａ) 特開 昭63−16672（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/786 H01L 21/336 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-159730 (JP, A) JP-A-63-16672 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/786 H01L 21/336
Claims (4)
となるポリシリコン層、ゲート絶縁膜及びゲート電極が
順次形成されてなる薄膜トランジスタであって、 前記ゲート絶縁膜上に形成されるゲート電極は、上層ゲ
ート電極と下層ゲート電極との２層構造からなるととも
に、前記上層ゲート電極と前記下層ゲート電極とが異な
る電極幅により構成され、 前記ゲート絶縁膜下に形成されるポリシリコン層は、前
記２層構造からなるゲート電極がマスクとなって形成さ
れる不純物拡散領域を有しており、 前記ポリシリコン層と前記ゲート絶縁膜とからなる積層
パターンの側壁には、絶縁体が形成されていることを特
徴とする薄膜トランジスタ。1. A thin film transistor in which a polysilicon layer serving as an active layer of a transistor, a gate insulating film, and a gate electrode are sequentially formed on an insulating substrate, wherein the gate electrode formed on the gate insulating film is A two-layer structure of an upper gate electrode and a lower gate electrode, wherein the upper gate electrode and the lower gate electrode have different electrode widths, and the polysilicon layer formed under the gate insulating film is An impurity diffusion region formed by using a gate electrode having a two-layer structure as a mask is formed, and an insulator is formed on a side wall of a stacked pattern including the polysilicon layer and the gate insulating film. A thin film transistor characterized by the above-mentioned.
領域は、ゲート電極が存在しない領域が高濃度の不純物
拡散領域であり、上層ゲート電極と下層ゲート電極との
いずれか一方のみが存在する領域が低濃度の不純物拡散
領域である請求項１に記載の薄膜トランジスタ。2. An impurity diffusion region formed in a polysilicon layer is a region where a gate electrode is not present is a high concentration impurity diffusion region, and a region where only one of an upper gate electrode and a lower gate electrode is present. Is a low concentration impurity diffusion region.
となるポリシリコン層、ゲート絶縁膜及びゲート電極が
形成された薄膜トランジスタの製造方法であって、 前記絶縁性基板上に、前記ポリシリコン層からなるトラ
ンジスタの活性層と、前記ゲート絶縁膜と、下層ゲート
電極とをそれぞれ順次形成し、該３層の膜を同一のレジ
ストパターンによりエッチングして島状パターンに加工
する工程と、 前記下層ゲート電極を所定の形状にパターニングする工
程と、 前記下層ゲート電極上に上層ゲート電極を成膜し、該上
層ゲート電極を前記下層ゲート電極の電極幅とは異なる
幅の所定の形状にパターニングする工程と、 前記下層ゲート電極及び上層ゲート電極をマスクとし
て、不純物イオンを前記ポリシリコン層に注入して、不
純物拡散領域を形成する工程とを含むことを特徴とする
薄膜トランジスタの製造方法。3. A method for manufacturing a thin film transistor in which a polysilicon layer serving as an active layer of a transistor, a gate insulating film and a gate electrode are formed on an insulating substrate, wherein the polysilicon layer is provided on the insulating substrate. Forming an active layer, a gate insulating film, and a lower gate electrode of the transistor in sequence, and etching the three layers with the same resist pattern to form an island pattern; Patterning an electrode into a predetermined shape; forming an upper gate electrode on the lower gate electrode; and patterning the upper gate electrode into a predetermined shape having a width different from the electrode width of the lower gate electrode. Implanting impurity ions into the polysilicon layer using the lower gate electrode and the upper gate electrode as a mask to form an impurity diffusion region; A method of manufacturing the thin film transistor, which comprises a step of forming.
に、絶縁体を形成する請求項３に記載の薄膜トランジス
タの製造方法。4. The method of manufacturing a thin film transistor according to claim 3, wherein an insulator is formed on a side wall of the island-shaped pattern including the three-layered film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18933492A JP3171673B2 (en) | 1992-07-16 | 1992-07-16 | Thin film transistor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18933492A JP3171673B2 (en) | 1992-07-16 | 1992-07-16 | Thin film transistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0637314A JPH0637314A (en) | 1994-02-10 |
| JP3171673B2 true JP3171673B2 (en) | 2001-05-28 |
Family
ID=16239606
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18933492A Expired - Fee Related JP3171673B2 (en) | 1992-07-16 | 1992-07-16 | Thin film transistor and method of manufacturing the same |
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| Country | Link |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100248123B1 (en) * | 1997-03-04 | 2000-03-15 | 구본준 | Thin-film transistor and method for manufacturing thereof |
| US6909114B1 (en) | 1998-11-17 | 2005-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having LDD regions |
| US7235810B1 (en) | 1998-12-03 | 2007-06-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| US6531713B1 (en) | 1999-03-19 | 2003-03-11 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and manufacturing method thereof |
| DE20006642U1 (en) | 2000-04-11 | 2000-08-17 | Agilent Technologies Inc | Optical device |
| US6562671B2 (en) | 2000-09-22 | 2003-05-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device and manufacturing method thereof |
| JP4098049B2 (en) * | 2001-11-30 | 2008-06-11 | シャープ株式会社 | Display panel |
| JP4382375B2 (en) | 2003-03-13 | 2009-12-09 | Ｎｅｃ液晶テクノロジー株式会社 | Thin film transistor manufacturing method |
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1992
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