JPH07131018A - Thin film transistor and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a thin film transistor having excellent characteristics in which fluctuation of leak current is suppressed at the time of turn OFF of the transistor. CONSTITUTION:An Si oxide 3, an Si nitride 4 and an Si oxide 5 constitute a gate electrode. When the uppermost Si oxide 3 is partially removed, the Si nitride 4 having different etching conditions serves as a stopper and thereby a desired layer can be removed by simply selecting the etchant. Since each part of an element is made uniform before an impurity diffusion layer is formed by ion implantation, a transistor having LDD structure of stabilized impurity profile can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (Thin Film) used as a control element of a liquid crystal display device, for example.
Film Transistor: hereinafter referred to as TFT) and its manufacturing method.

[0002]

2. Description of the Related Art In LCDs as liquid crystal devices, the development of a simple matrix system to an active matrix system has become popular in recent years. The active matrix system includes a TFT type in which a thin film transistor is attached to each pixel and a diode type in which a non-linear diode is attached. Among them, the TFT type holds the voltage applied during the selection period until the next scanning by utilizing its switching characteristic and pixel capacitance, and it is possible to easily obtain high contrast and halftone with a large capacitance. it can.

However, this TFT type LCD is
There is a problem that leakage current is generated during the so-called TFT OFF period in which the applied voltage is held. Therefore, in order to reduce this leakage current, an LDD structure transistor is adopted. Although various methods of manufacturing a transistor having an LDD structure have been proposed, a technique of forming in self alignment in order to simplify the process is disclosed in, for example, Japanese Patent Laid-Open No. 5-55255
Japanese Patent Publication (H01L21 / 336).

This will be described with reference to FIG. First,
A polycrystalline silicon film 52 is formed on a quartz glass substrate 51, and a silicon oxide film 53 as a gate insulating film is formed thereon.
Are formed (A). Next, the doped polycrystalline silicon is deposited on the Si oxide film 53 and patterned to obtain a gate.
And a Si oxide film 55 is deposited thereon (B).

Next, the resist 5 is wrapped around the gate electrode 54.
6 and cover the Si oxide film 5 by anisotropic etching.
The thickness of the portion not covered with the resist 56 of No. 3 is reduced (C). When the resist 56 is removed, as shown in FIG. 2D, the Si oxide film 53 has a thick film on both sides of the gate electrode 54 and a thin film next to the gate electrode 54.
When phosphorus ions 57 are implanted into the polycrystalline silicon 52 from above using the gate electrode 54 as a mask, the impurity concentration in the polycrystalline silicon 52 is low in the thick portion of the Si oxide film 53 and is thin. The portion becomes thicker, and the impurity diffusion regions of the LDD structure as the source and the drain are formed in a self-aligned manner.

[0006]

In the conventional example, since the film thickness of the Si oxide film 53 is reduced by anisotropic etching, etching is performed so that the film thickness of each element is uniform. Is very difficult to adjust.
If the film thickness of each element changes subtly, the impurity profile of the LDD structure also changes, so there is a problem that the characteristics tend to vary from element to element. FIG. 4 shows the gate voltage (Vg) -drain current (Id) characteristics of this conventional thin film transistor. It can be seen that the error is large and the leakage current when the transistor is off tends to vary.

In particular, since the LCD has several hundreds of thousands of pixels, variations in the elements directly affect the display characteristics, so it is necessary to control the characteristics of each element quite strictly. The present invention relates to a thin film transistor and a manufacturing method thereof, and solves such a problem.

[0008]

A thin film transistor of the present invention comprises a semiconductor film formed on an insulating substrate and a laminated film of two or more layers on the semiconductor film, and at least 2
A gate insulating film whose layers are made of materials having different etching conditions and at least a region of the lowermost film is larger than a region of the upper film, and a gate insulating film formed on the gate insulating film. -A gate electrode having a smaller area than the gate insulating film, and an impurity diffusion region of LDD structure which is formed on both sides of the gate electrode in the semiconductor film and serves as a source and a drain. .

Further, the method of manufacturing a thin film transistor of the present invention comprises a step of forming a semiconductor film on an insulating substrate and a laminated film of two or more layers on the semiconductor film, wherein at least two layers are etching conditions. Forming a gate insulating film made of different materials, forming a gate electrode on the gate insulating film, and forming at least the uppermost layer of the gate insulating film in the region Etching away so that it is smaller than the lower layer and larger than the gate electrode; and using the gate electrode as a mask, ions are implanted into the semiconductor film from above to form both sides of the gate electrode. To
And a step of forming an impurity diffusion region to be a source and a drain.

Further, the method of manufacturing a thin film transistor according to the present invention comprises a step of forming a semiconductor film on an insulating substrate and a laminated film of two or more layers on the semiconductor film, wherein at least two layers are etching conditions. Forming a gate insulating film made of different materials, etching removing at least the uppermost layer of the gate insulating film so that its region becomes smaller than the lower layer, and the gate insulating film On top of the,
Forming a gate electrode having a region smaller than the gate insulating film; and using the gate electrode as a mask, ions are implanted into the semiconductor film from above so that both sides of the gate electrode are formed. , A step of forming an impurity diffusion region serving as a source and a drain.

[0011]

That is, at least two layers of the gate insulating film are composed of laminated films having different etching conditions. Then, when removing at least a part of the uppermost layer of the gate insulating film by etching, another layer having different etching conditions serves as a stopper and only the desired layer is removed by simply selecting an etchant. You can

Therefore, when ion implantation is performed, the film thickness of each part of the element before forming the impurity diffusion region becomes uniform for each element, and an LDD structure transistor having a stable impurity profile can be obtained.

[0013]

EXAMPLE An example of the present invention will be described with reference to FIG.
FIG. 1 is a cross-sectional view showing a process for producing the thin film transistor of the present invention. In FIG. 1A, a 700Å polycrystalline silicon film 2 is formed on an insulating substrate 1 such as quartz glass by a low pressure CVD method, and this is thermally oxidized at 1050 ° C. A 200 Å silicon oxide film 3 is formed. Further, 200Å silicon nitride films 4 and 60 are formed on the Si oxide film 3 by a low pressure CVD method.
A 0Å silicon oxide film 5 is sequentially formed. The Si oxide film 3, the Si nitride film 4, and the Si oxide film 5 form a gate insulating film.

Next, referring to FIG. 1B, the Si oxide film 5 is formed.
A 2000 Å polycrystalline silicon film is deposited on the above by a low pressure CVD method, and phosphorus (P) is diffused at 900 ° C. Furthermore,
15 is formed on the polycrystalline silicon film by the low pressure CVD method.
After depositing a silicon oxide film 6 of 00Å, the polycrystalline silicon film is processed by using a lithography technique and an etching technique to form a gate electrode 7.

Next, referring to FIG. 1C, the gate electrode 7 is formed.
On the other hand, a resist 8 having an offset structure was patterned, and a normal RIE method (conditions: RF power 500 W, processing chamber pressure 40 mTorr, used gas CHF ₃ , gas flow rate 80) was used.
The gate oxide film 4 is removed by anisotropic etching with a ccm). At this time, since the Si oxide film 5 and the Si nitride film 4 have different etching conditions, the Si nitride film 4 serves as a stopper to remove only the Si oxide film 5.

Then, in FIG. 1D, phosphorus (P) ions 9 are accelerated from above by an ion implantation method to an acceleration voltage of 40 Ke.
Implanting into the polycrystalline silicon film 2 under the conditions of V and dose amount 2 × 10 ¹⁵ cm ^-2 . At this time, due to the offset structure of the resist, the peak portion of phosphorus ions exists in the remaining portion of the Si oxide film 5 (P region in FIG. 1D) in the gate oxide film as shown in FIG. And for this reason
The effective dose amount in the polycrystalline silicon film 2 is 4 × 1.
It is a low concentration region of 0 ¹³ cm ^-2 .

On the other hand, the portion where the Si oxide film 5 does not exist (Q region in FIG. 1D) has a phosphorus ion peak as shown in FIG.
A high concentration exists in the polycrystalline silicon film 2 and becomes a high concentration region. Therefore, in the low and high density regions, L
The DD structure is constructed. Finally, 900 in a nitrogen atmosphere
A heat treatment is carried out at 30 ° C. for 30 minutes to activate phosphorus to form impurity diffusion regions 10 and 11 of LDD structure as sources and drains on both sides of the gate electrode 7.

FIG. 3 shows the gate of the thin film transistor of this embodiment.
The graph shows the characteristics of the voltage (Vg) -drain current (Id). It can be seen that the error is smaller than that in FIG. 4 and the leakage current when the transistor is off is stable.
In this embodiment, after the gate electrode 7 is processed, the Si
Although a part of the oxide film 5 was removed by etching, there is no problem even if the process is reversed.

Further, in this embodiment, the gate electrode has a three-layer structure of the Si oxide film 3, the Si nitride film 4 and the Si oxide film 5, and the Si nitride film 4 is used as the stopper, but the present invention is not limited to this. Not something to do. For example, when the gate electrode has a two-layer structure of the Si oxide film 3 and the Si nitride film 4, the Si oxide film 3 functions as a stopper. In this case, Si nitride film 4
The conditions for removing RIE by the RIE method are, for example, RF power 200 W, processing chamber pressure 40 mTorr, used gas CHF ₃ + O ₂ , gas flow rate CHF ₃ 80 ccm, O ₂ 1.
It should be 6 ccm. By doing so, only the Si nitride film 4 is removed and the Si oxide film 3 remains.

[0020]

According to the thin film transistor and the method of manufacturing the same of the present invention, it is possible to provide an element having good characteristics with little variation in leakage current when the transistor is off.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a thin film transistor in an example of the present invention.

FIG. 2 is a view corresponding to FIG. 1 in a conventional example.

FIG. 3 is a gate current-drain current characteristic diagram of a thin film transistor according to an example of the present invention.

FIG. 4 is a gate current-drain current characteristic diagram of a conventional thin film transistor.

FIG. 5 is a diagram showing an impurity profile of a high concentration region after ion implantation of a thin film transistor in an example of the present invention.

FIG. 6 is a diagram showing an impurity profile of a low concentration region after ion implantation of a thin film transistor in an example of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Polycrystalline silicon film (semiconductor film) 3 Silicon oxide film (gate insulating film) 4 Silicon nitride film (gate insulating film) 5 Silicon oxide film (gate insulating film) 7 Gate electrode 10, 11 Impurity diffusion region

Claims (3)

[Claims] 1. A semiconductor film formed on an insulating substrate,
On this semiconductor film, two or more laminated films are formed, at least two layers are made of materials having different etching conditions, and at least the lowermost film region is formed to be larger than the upper film region. A gate insulating film, a gate electrode formed on the gate insulating film and having a smaller area than the gate insulating film, and a gate electrode formed on both sides of the gate electrode in the semiconductor film. -LDD as drain and drain
A thin film transistor comprising an impurity diffusion region having a (Lightly Doped Drain) structure. 2. A step of forming a semiconductor film on an insulating substrate, and a laminated film having two or more layers on the semiconductor film,
Forming a gate insulating film having at least two layers made of materials having different etching conditions; forming a gate electrode on the gate insulating film; and forming at least the gate insulating film. Etching the upper layer so that its region is smaller than the lower layer and larger than the gate electrode; and by implanting ions from above into the semiconductor film using the gate electrode as a mask. A method of manufacturing a thin film transistor, which comprises performing a step of forming an impurity diffusion region serving as a source and a drain on both sides of a gate electrode. 3. A step of forming a semiconductor film on an insulating substrate, comprising a laminated film of two or more layers on the semiconductor film,
A step of forming a gate insulating film in which at least two layers are made of materials having different etching conditions, and a step of etching and removing at least the uppermost layer of the gate insulating film so that its region becomes smaller than the lower layer. A step of forming a gate electrode having a smaller area than the gate insulating film on the gate insulating film, and using the gate electrode as a mask,
And a step of implanting ions into the semiconductor film from above to form impurity diffusion regions serving as a source and a drain on both sides of the gate electrode.