JP3167445B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor,
In particular, the present invention relates to a method of manufacturing a thin film transistor for a peripheral circuit of a liquid crystal display or an image sensor.

[0002]

2. Description of the Related Art Conventionally, thin film transistors (hereinafter, referred to as TFTs) have been used.
Also called. The following two methods are available for forming the ohmic layer region in the method (1).

As one method, a coplanar TFT shown in FIG. 5 will be described as an example.

The structure of this TFT is such that a semiconductor film 14, for example, a non-doped (doped with no impurity) polysilicon film is formed on a glass substrate 10, and a non-doped polysilicon film is formed for forming an n ⁺ layer polysilicon. Phosphine (PH ₃ ) is newly introduced into the gas for forming the (Si) film. Thereafter, the portion to be left as the ohmic layer is covered with a mask, and the remaining polysilicon portion is removed by etching to form a predetermined ohmic layer 16. Then, after covering the semiconductor film 14 and the ohmic layer 16 formed on the substrate with the gate insulating film 12, for example, Si-N (silicon nitride film), the gate insulating film 12 is formed.
A window for source / drain electrodes for exposing the ohmic layer 16 is formed in the gate insulating film 12.

Next, the source / drain electrode 1 is protruded from the ohmic layer 16 to the surface of the gate insulating film 12.
8 is formed. The source / drain electrode 18 is formed by, for example, an evaporation method or a sputtering method. Also,
In the middle of each source / drain electrode 18, and
A gate electrode 19 is also formed on the gate insulating film 12 at the same time.

As another method, there is a method of manufacturing a TFT by self-alignment (self-alignment).

FIGS. 6 and 7 are process diagrams for explaining a conventional manufacturing method using self-alignment.

According to this method, first, for example, a non-doped (undoped impurity) polysilicon layer is formed as a semiconductor film 32 on a quartz substrate 30 (FIG. 4A). Next, the surface of the semiconductor film 32 is thermally oxidized at a temperature of, for example, about 1000 ° C. to form a thin gate oxide film 34 (FIG. 6B).

Next, a gate electrode 36 is formed on the gate oxide film 34 by using any conventionally known suitable method (FIG. 6).
(C)). Thereafter, ions are implanted into the semiconductor film 32 using the gate electrode 36 as a mask, and the semiconductor film 3
2 is changed to an ohmic layer 38 (FIG. 7A). In this process, the gate is
A channel region 37 having substantially the same dimensions as the gate electrode is formed in the semiconductor film 32. Thereafter, the ohmic layer 38, the gate oxide film 34, and the gate electrode 36 formed on the substrate 30 are covered with an interlayer insulating film 40 (for example, using an SiO ₂ film). And gate oxide film 3
4 is etched to form an ohmic layer opening 41 to form an ohmic layer exposed portion 39 (FIG. 7B). At this time, an ohmic layer opening 41 is formed.

Next, a source / drain electrode 42 is formed in the ohmic layer opening 41 by using a sputtering method or a vapor deposition method (FIG. 7C).

[0011]

However, in the case of the above-mentioned conventional coplanar TFT structure, the substrate 1
After forming the semiconductor film 14 on the semiconductor film 14, when forming the ohmic layer 16 on the semiconductor film 14, the polysilicon film region for the ohmic layer 16 is masked and the polysilicon film is etched. Do. At this time, there is a problem that the surface of the semiconductor film is roughened because the surface of the semiconductor film is over-etched. For this reason, the electrical characteristics deteriorate, such as a decrease in the mobility of the transistor and a decrease in the on-state current. Further, when the surface of the semiconductor film is damaged by the over-etching, there is a problem that a stable channel region cannot be formed.

In the structure of the conventional coplanar TFT, the gate insulating film 12 is formed as shown by an arrow 20 in FIG.
, The gate electrode and the ohmic layer overlap each other. When formed by a conventional method, the overlap amount (also referred to as an overlap capacitance) reaches about 5 μm. In addition, such an increase in the overlap capacitance deteriorates the rise of a pulse when used as a TFT for a peripheral circuit, and causes waveform distortion.

On the other hand, the conventional TFT having a structure based on self-alignment described with reference to FIGS. 6 and 7 has the following problems in its process.

A high-temperature treatment is required at the stage of forming the oxide film (for example, the oxidation treatment is performed at 1000 ° C. or higher).

In ion implantation, it is difficult to form a large area.

A high-temperature treatment for activating the ion-implanted ohmic layer is required (for example, the activation treatment is performed at 600 ° C. or higher).

When a liquid crystal display or an image sensor is manufactured, low-temperature processing is required to form a predetermined film on a glass substrate, and it is necessary to manufacture a large-area polysilicon TFT. It is becoming. However, when manufacturing a liquid crystal display or an image sensor by using a conventional self-alignment method, the above-mentioned problems (1) to (4) cannot be solved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device in which a channel region is formed without damaging the surface thereof.
It is an object of the present invention to provide a method of manufacturing a thin film transistor capable of reducing an overlapping capacity between a gate electrode and an ohmic layer via a gate insulating film and manufacturing a large area thin film transistor by a low-temperature process.

[0019]

In order to achieve the object, according to the method of manufacturing a thin film transistor of the present invention,
Forming a semiconductor film pattern on the substrate; and covering the entire surface of the substrate including the semiconductor film pattern with a thin film for forming a gate insulating film and a thin film for forming a gate electrode. Forming two windows for exposing a region where the ohmic layer is to be formed in the semiconductor film pattern; and introducing predetermined impurities into the region where the ohmic layer is to be formed by plasma doping; Partially removing the gate electrode forming thin film to form a remaining gate electrode thin film.

In practicing the present invention, it is preferable to use ECR plasma doping as the plasma doping.

[0021]

According to the method of manufacturing a thin film transistor of the present invention described above, first, a semiconductor film pattern is formed on a substrate, and then the entire substrate including the semiconductor pattern is formed on a gate insulating film forming thin film and a gate insulating film. -After successively covering with a thin film for forming
A window is formed in these thin films to expose a region where the ohmic layer is to be formed in the semiconductor film pattern. By such a process, the semiconductor film surface is not etched as in the related art, so that damage to the semiconductor film surface due to over-etching can be avoided. Therefore, deterioration of electrical characteristics such as reduction in mobility of the transistor and reduction in on-state current can be prevented.

Next, plasma doping is performed through the two exposed windows to introduce impurities into a predetermined region where an ohmic layer is to be formed. At this time, the method by plasma doping can be performed by a low temperature treatment (about 300 ° C.). The ohmic layer is formed by plasma doping using a thin film for a gate insulating film, a thin film for forming a gate electrode, and a resist as a mask, so that two channel regions are formed in the semiconductor film. The size of the gate electrode thin film between the windows is transferred to the channel region as it is. For this reason, the overlap capacitance between the gate electrode and the ohmic layer via the gate insulating film is significantly reduced as in the prior art.

Therefore, when the thin film transistor of the present invention is used for a peripheral circuit, the delay in rising of the pulse and the distortion of the waveform are small, so that the electric characteristics can be improved.

Next, the thin film for the gate electrode to be used as a part of the gate electrode is formed by removing the thin film for forming the gate electrode partially. Therefore, according to the present invention, it is not necessary to activate the ohmic layer at a high temperature when forming the n ⁺ layer by ion implantation as in the prior art. Another advantage is that the thin film can be formed at a low temperature by using the above-described plasma doping method, so that the area can be increased.

Further, by using ECR plasma doping as the plasma doping, about 1000 A °
(A ° is a symbol representing an Angstrom), and an ohmic layer having a depth of about で き る can be formed.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. The drawings merely schematically show the dimensions, shapes, and arrangements of the components to the extent that these inventions can be understood. Further, in the following description, specific materials and conditions will be described, but these materials and conditions are only one suitable example, and therefore are not limited thereto.

First, a basic outline of the steps of the embodiment of the present invention will be described with reference to FIGS.

A glass substrate 50 is used as a substrate, and a semiconductor film pattern (also referred to as an active layer pattern) 52 is formed on the substrate 50. At this time, a predetermined semiconductor film pattern
In order to form a semiconductor layer, a semiconductor film is once formed on a substrate by using a usual technique, and then the film is masked and the film is etched (FIG. 1A).

Next, the entire surface of the substrate including the semiconductor film pattern 52 is sequentially covered with the thin film 54 for forming a gate insulating film and the thin film 56 for forming a gate electrode. Further, after a resist pattern 58 is formed on the thin film 56 by using a normal technique, two windows 59 for exposing the ohmic layer forming region 60 of the semiconductor film pattern 52 are formed. ((B) of FIG. 1). The exposure window 59 is formed by partially etching and removing the thin films 56 and 54 through the opening of the resist pattern 58 by using an ordinary etching technique. Therefore, the surface of the region of the semiconductor film pattern 52 which is to be a channel region is covered with an insulating film or the like and is not damaged by etching.

Next, in the region 60 where the ohmic layer is to be formed,
A predetermined impurity (for example, an element such as phosphorus (P) or boron) is introduced into this region 60 by performing plasma doping, for example, ECR plasma doping on the exposed portion of the semiconductor pattern 52. Thereby, the semiconductor film pattern
An ohmic layer 61 of an n ⁺ layer or a p ⁺ layer is formed in a partial region on the surface side of the pin 52 (FIG. 1C).

Next, the thin film 56 for forming the gate electrode is partially removed to form a thin film 62 for the gate electrode, thereby obtaining a structure having a sectional structure as shown in FIG. . This figure 1
3D, the gate electrode thin film 62 is left between the two windows, and the other gate electrode forming thin films are removed by etching.

Next, the ohmic layer 61, the gate insulating film 5
After covering the entire surface of the thin film 5 and the gate electrode thin film 62 with an insulating film, an interlayer insulating film pattern 6 is formed by photolithographic etching.
4 (FIG. 2A). Subsequently, the gap between the gate insulating film 55 and the interlayer insulating film 64 on the ohmic layer is filled with an electrode material, for example, aluminum (Al) by using EB vapor deposition or sputtering to form a coplanar thin film transistor. (FIG. 2B).

Next, a method of manufacturing a thin film transistor according to the present invention will be described in detail with reference to the sectional views of FIGS. 1 and 2 and the plan views of FIGS. In FIGS. 3 and 4, hatching and the like do not represent a cross section, but emphasize a specific region when viewed in a plan view.

First, plasma CVD is performed on a glass substrate 50.
A semiconductor film is formed by a method or the like.

This semiconductor film is formed, for example, as a non-doped polysilicon film to a thickness of 3000 A ° to 4000 A ° (not shown).

Next, a semiconductor film pattern 52 is formed by photolithography using a mask to form a semiconductor pattern. At this time, as a film forming gas of plasma CVD, silicon tetrafluoride (SiF ₄ ), silane (SiH ₄ )
₄ ) Use a mixed gas containing hydrogen (H ₂ ). still.
In this case, the semiconductor film pattern 52 can be formed at a low temperature of about 300 ° C. (FIG. 1A and FIG. 3A).

Next, after the semiconductor film pattern 52 is formed, the entire surface of the substrate including the semiconductor film pattern 52 is covered with the gate insulating film forming thin film 54. This gate insulating film forming thin film 54 is, for example, a silicon nitride film (Si-N). This silicon nitride film is formed using a plasma CVD method. In this CVD method, 13.56 in a mixed gas atmosphere containing silane (SiH ₄ ) and ammonia (NH ₃ ).
The gas is decomposed by glow discharge at a high frequency of MHz. Subsequently, a thin film 56 for forming a gate electrode is formed on the thin film 54 for forming a gate insulating film. The gate electrode forming thin film 56
Is formed by gasifying chromium (Cr) using EB (Electron Beam) and vapor-depositing it on the thin film 54 for a gate insulating film.

A resist material is applied on the thin film sequentially formed as described above, and the resist material is dried and cured under any appropriate conditions to form a resist layer. The resist layer is etched to form a semiconductor film pattern. A window 59 (also referred to as an exposure window) for exposing the ohmic layer forming region 60 of the pin 52 is formed (FIG. 1B and FIG. 3).
(B)).

Next, ECR (Electron Cyclotron Resonance)
Semiconductor film pattern 5 through window 59 using a plasma method.
A predetermined impurity that determines the conductivity type is introduced into the exposed portion of No. 2. At this time, the gas used for plasma doping is usually a gas (PH ₃ or B ₂ H ₆ ) containing atoms to be doped, for example, phosphorus (P) or boron (B), such as helium (He) or hydrogen ( A mixed gas diluted with H ₂ ) gas is used. In the embodiment of the present invention, a mixed gas of 5 vol% phosphine (PH ₃ ) diluted with helium (He) is supplied by about 14%.
was introduced at a flow rate of sccm, a silane (SiH ₄₎ gas is introduced 0.1Sccm～1sccm. Also, under the condition of microwave output of about 400 W and RF power of 480 W,-
A self-bias voltage of about 210 V is generated on the surface of the semiconductor pattern. By performing the plasma treatment for about 7 minutes, the silane (S
When iH ₄ ) is introduced at 1 sccm, about 180 KΩ
The sheet resistance of the mix layer is obtained. The region into which the plasma doping has been introduced becomes the ohmic layer 61 (FIG. 1C and FIG. 3C).

In this embodiment, since a small amount of silane (SiH ₄ ) gas is added, the etching amount of the semiconductor film 52 can be reduced. According to experiments performed by the inventor of the present application, it has been found that He used as a diluent gas in ECR plasma doping is ionized and irradiated to the semiconductor film surface to cause etching of the semiconductor surface. Therefore, a small amount of monosilane (SiH ₄ ) is added to He gas.
, The etching of the semiconductor surface is reduced. The reason for this is that the addition of a small amount of monosilane (SiH ₄ ) gas reduces the etching rate. This is because silicon (Si) atoms are replenished to the surface to be doped (the surface of the region where the ohmic layer is to be formed), so that apparently etching is reduced and the sheet resistance in the region to be doped is also reduced. It is thought to be. Here, monosilane (S) is used as a gas capable of replenishing silicon (Si) atoms.
Although iH ₄ ) was used, it is not limited to this gas at all, and any other gas that can supply silicon (Si) may be used.

As described above, phosphorus (P) is introduced into the region 60 where the ohmic layer is to be formed by the ECR plasma doping, thereby forming the n ⁺ -layer separated ohmic layers 61. At this time, the depth of the ohmic layer is 500 A ° -1.
It is about 000 A ° (FIG. 1 (C) and FIG. 3 (C)). The region of the semiconductor film pattern 52 between the ohmic layers 61 becomes a channel region.

Next, after the resist pattern 58 is peeled off by any suitable method, the portion of the gate electrode forming thin film 56 between the two windows 59 is mainly masked, and the other electrode forming thin films 56 are removed. The part is etched away. As a result, the portion of the thin film 56 remaining above the channel region becomes the thin film 62 for the gate electrode. The channel region formed between the ohmic layers 61 has substantially the same dimensions as the gate electrode thin film 62 (FIG. 1D and FIG. 4A). Here, the thin film portion for the gate insulating film below the thin film 62 for the gate electrode functions as the gate insulating film 55, and the other thin film portion 57 for the gate insulating film functions as an interlayer insulating film. Works.

Next, the ohmic layer 61, the gate insulating film 5
After covering the entire surface of the thin film 5 and the gate electrode thin film 62 with another interlayer insulating film, for example, an SiO ₂ film, an interlayer insulating film pattern 64 is formed by photolithographic etching (FIG. 2A and FIG. FIG. 4 (B)). The ohmic layer 61 and the gate electrode thin film 62 are exposed at the opening of the interlayer insulating film pattern 64.

Next, a gate electrode 66 is formed on the gate electrode thin film 62 by using a sputtering method or an EB evaporation method, and a gate / drain electrode 68 is formed on the ohmic layer 61, respectively. Form. At this time, for example, aluminum (Al) or the like is used as the electrode material (FIG. 2B and FIG. 4C).

According to the above-described manufacturing process according to the present invention, after the insulating film is formed on the semiconductor pattern, the window is formed without exposing the channel region and in the region where the ohmic layer is to be formed. Since the plasma doping is performed later, the channel region of the semiconductor film does not suffer surface damage unlike the case where a conventional coplanar ohmic layer is formed. Accordingly, deterioration of the electrical characteristics due to a decrease in the mobility of the transistor and a decrease in the on-state current are reduced. In addition, as is apparent from this embodiment, since the channel dimensions substantially the same as those of the gate electrode thin film can be obtained, the gate insulating film can be interposed more than the conventional coplanar TFT. As a result, the overlap capacitance between the gate electrode and the ohmic layer can be reduced. Therefore, when the TFT of the present invention is used in a peripheral circuit, it is possible to reduce a delay in rising of a pulse and distortion of a waveform.

In addition, T by conventional self-alignment
The FT process requires a high-temperature treatment for forming a gate oxide film and a high-temperature treatment for activation after forming an ohmic layer. However, as is apparent from the embodiment of the present invention, a TFT can be formed by low-temperature processing (300 ° C. or lower). Further, there is also obtained an advantage that it is possible to easily form a thin film having a large area, which has been conventionally difficult because ion implantation is not used.

[0047]

As is apparent from the above description, after a semiconductor pattern is formed on a substrate, the entire substrate including the semiconductor pattern is formed on a substrate to form a gate insulating film forming thin film and a gate electrode. After sequentially covering with a thin film for use, a window for exposing a region where an ohmic layer is to be formed of the semiconductor film pattern is formed in these thin films. After these steps, as described later, ECR plasma doping is performed to introduce impurities into a region where an ohmic layer is to be formed, and the surface of the semiconductor film pattern serving as a channel region is exposed to etching. Therefore, the semiconductor film is not over-etched by etching after forming a thin film for an ohmic layer as in the related art. For this reason, surface damage of the semiconductor film pattern can be avoided. Therefore, deterioration of electrical characteristics such as a decrease in mobility of the transistor and a decrease in on-state current can be prevented.

According to the present invention, an ohmic layer is formed by plasma doping in a region where an ohmic layer is to be formed.
The treatment can be performed at a low temperature of 300 ° C. or less without giving any dirt. The ohmic layer is formed by forming a thin film for forming a gate insulating film, a thin film for forming a gate electrode, and a resist pattern.
In the same manner as in the conventional self-alignment method, the channel region formed in the semiconductor layer has the same size as that of the gate electrode thin film formed between the windows transferred as it is in the conventional self-alignment method. You. For this reason, the overlapping capacitance between the gate electrode and the ohmic layer via the gate insulating film is reduced as in the prior art, and when the TFT of the present invention is used in a peripheral circuit, the rise delay of the pulse and the waveform of the waveform are reduced. Since distortion is reduced, electric characteristics can be improved.

Further, according to the present invention, the thin film for forming a gate electrode is partially removed, and the thin film for a gate electrode is formed on the remaining thin film for forming a gate electrode. This eliminates the need for the conventional activation treatment of the ohmic layer at a high temperature. In addition, since impurities are introduced into a region where an ohmic layer is to be formed by using a plasma doping method, the treatment can be performed at a low temperature.

Further, since it is possible to increase the area of the thin film, which has been difficult with the ion implantation method, it is easy to integrate peripheral circuits, for example, TFTs of a liquid crystal display or an image sensor.

Further, by using ECR plasma doping as plasma doping, about 1000 A °
An ohmic layer of about a depth can be formed.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing a manufacturing process for explaining an embodiment of the present invention.

FIGS. 2 (A) and 2 (B) are cross-sectional views showing manufacturing steps for explaining the embodiment of the present invention continued from FIG.

FIGS. 3A to 3C are plan views showing manufacturing steps for explaining an embodiment of the present invention.

FIGS. 4A to 4C are plan views showing a manufacturing process for explaining the embodiment of the present invention continued from FIG. 3;

FIG. 5 is a cross-sectional view illustrating a structure of a conventional coplanar TFT.

FIGS. 6A to 6C are cross-sectional views showing a process for manufacturing a TFT by conventional cell alignment.

FIGS. 7A to 7C are cross-sectional views showing a manufacturing process of a TFT by conventional cell alignment following FIG.

[Explanation of symbols]

 50: Glass substrate 52: Semiconductor film pattern 54: Gate insulating film forming thin film 55: Gate insulating film 56: Gate electrode forming thin film 57: Gate insulating thin film 58: Resist pattern 59: Window 60: Ohmic layer formation planned area 61: Ohmic layer 62: Gate electrode thin film 64: Interlayer insulating film 66: Gate electrode 68: Source / drain electrode

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-162719 (JP, A) JP-A-61-48979 (JP, A) JP-A-5-55258 (JP, A) JP-A-1- 165172 (JP, A) JP-A-5-206165 (JP, A) JP-A-4-37061 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 G02F 1 / 1368 H01L 21/265 H01L 21/336

Claims (2)

(57) [Claims] A step of forming a semiconductor film pattern on a substrate; and a step of sequentially covering the entire surface of the substrate including the semiconductor film pattern with a gate insulating film forming thin film and a gate electrode forming thin film. rear,
Forming two windows in the thin film to expose the region where the ohmic layer is to be formed of the semiconductor film pattern; and introducing predetermined impurities into the region where the ohmic layer is to be formed by plasma doping. A method of manufacturing a thin film transistor, comprising: a step of partially removing the gate electrode forming thin film and forming a remaining gate electrode thin film. 2. The method for manufacturing a thin film transistor according to claim 1, wherein an ECR plasma doping is used as said plasma doping.