JP3452981B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention refers to an insulating substrate (in this specification, refers to the entire object having an insulating surface, and unless otherwise specified, not only on an insulating material such as glass but also on a material such as a semiconductor or a metal. A thin-film insulating gate type semiconductor device (thin film transistor,
And a method for forming the same. The semiconductor integrated circuit according to the present invention is
Those used for active matrix circuits such as liquid crystal displays and their peripheral driving circuits, driving circuits for image sensors, etc., or SOI integrated circuits and conventional semiconductor integrated circuits (microprocessors, microcontrollers, microcomputers, semiconductor memories, etc.) Is.

[0002]

2. Description of the Related Art Conventionally, when a circuit such as an active matrix type liquid crystal display device or an image sensor is formed on a glass substrate, a thin film transistor (TF) is used.
A configuration in which T) is integrated and used is widely known. In this case, a method of forming a first-layer wiring including a gate electrode first, then forming an interlayer insulator, and then forming a second-layer wiring is generally used. In some cases, the wirings of the third and fourth layers may be formed.

[0003]

The greatest problem in such an integrated circuit of thin film transistors is that there are two problems in the wiring on the extension of the gate electrode (gate wiring) and the crossing portion (override portion) of the wiring of the second layer. It was a disconnection (also called a step break) of the wiring of the layer. This is because it is difficult to form the interlayer insulator on the gate electrode / wiring with good step coverage and further planarize it.

FIG. 4 shows a state of disconnection failure often seen in a conventional TFT integrated circuit. TF on the substrate
A T region 401 and a gate wiring 402 are provided, and an interlayer insulator 403 is formed so as to cover them. However, if the edge of the gate wiring 402 is steep, the inter-layer insulator 403 cannot sufficiently cover the gate wiring. When the second-layer wirings 404 and 405 are formed in such a state, the second-layer wiring is broken (stepped) as shown in the figure at the crossover portion 406 of the gate wiring.

In order to prevent such disconnection, it is necessary to increase the thickness of the second layer wiring. For example, it has been desired to make the thickness about twice that of the gate wiring. However, this means that the unevenness of the integrated circuit is further increased, and when it is necessary to further stack wiring on it, disconnection due to the thickness of the second layer wiring must be taken into consideration. . Further, when forming a circuit such as a liquid crystal display in which unevenness of the integrated circuit is not preferred, it is practically impossible to deal with it by increasing the thickness of the second layer wiring. In an integrated circuit, if there is even one step break, the whole becomes defective, so how to reduce the step break is an important issue. It is an object of the present invention to provide a method for reducing such step disconnection defects, and thus increasing the yield of integrated circuits.

[0006]

In the present invention, an oxide film is formed by oxidizing a gate electrode on at least the upper surface of the gate electrode / wiring by an anodic oxidation method, and further on the side surface of the gate electrode / wiring. After forming an approximately triangular insulator (sidewall) by anisotropic etching, an interlayer insulator is deposited, and further a second layer wiring is formed. The oxide film formed by the anodic oxidation method needs to be less likely to be etched than the material of the sidewall that is formed later. When the sidewall is formed of silicon oxide, aluminum oxide is used. , Tantalum oxide, titanium oxide, molybdenum oxide, tungsten oxide and the like are preferable. These materials have an extremely low etching rate under the conditions for etching silicon oxide by the dry etching method, that is, under the etching with a fluorine-based etching gas (for example, NF ₃ , SF ₆ ).

The first method for carrying out the present invention is as follows. First, an island-shaped semiconductor layer is formed. Further, a film to be a gate insulating film is formed thereon. Further, a gate electrode / wiring is formed. At this time, the gate electrode / wiring is formed of a material that is anodized, and as a result of the anodization, it is necessary that the film obtained is less likely to be etched than the sidewalls. Then, a positive voltage is applied to the gate electrode / wiring in an approximately neutral electrolytic solution to form an anodic oxide film on at least the upper surface of the gate electrode / wiring. This step may be performed by a vapor phase anodic oxidation method. This is the first stage.

After that, an insulating film is formed to cover the gate electrode / wiring and the anodic oxide film around it. Coverability is important in forming this coating, and a thickness of 1/3 to 2 times the height of the gate electrode / wiring is suitable. For this purpose, plasma CVD method or low pressure CVD method,
A chemical vapor deposition (CVD) method such as atmospheric pressure CVD method is preferable. Then, the insulator thus formed is preferentially etched in a direction substantially perpendicular to the substrate by anisotropic etching. The etching is finished to such an extent that the insulating film on the flat portion is etched, and further the etching may be advanced to such an extent that the gate insulating film thereunder is etched. As a result, the gate electrode
In the step portion such as the side surface of the wiring, since the insulating film is originally thick, the insulating material (sidewall) of the approximately triangular castle is left behind. The above is the second stage.

Then, after forming an interlayer insulator, TF
A contact hole is formed in one or both of the source / drain of T and a second layer wiring is formed. Up to this point is the third stage. In the above steps, there are various cases in which doping is performed to form the source / drain of the TFT. For example, when only an N-channel TFT is formed on the substrate, a relatively high concentration of N-type impurities is masked between the gate electrode and the surrounding anodic oxide film between the first step and the second step. It may be introduced as a self-alignment into the semiconductor layer. In this case, if the anodic oxide film is present on the side surface of the gate electrode,
The so-called offset gate type is formed in which the source / drain and the gate electrode are separated by the thickness of the anodic oxide. However, in the following description, such a case will be referred to as a normal TFT.

Similarly, when forming an N-channel type TFT, a TF having a low concentration drain (LDD) is also formed.
When a T (LDD type TFT) is formed, a relatively low concentration of impurities is introduced into the semiconductor layer between the first step and the second step, and then the second step and the third step are performed. High-concentration N-type impurities may be introduced into the semiconductor layer in a self-aligned manner using the gate electrode and the sidewall as a mask. In this case, the LDD width is approximately the same as the sidewall width. The same applies to the case where only the P-channel TFT is formed on the substrate.

A so-called complementary circuit (CMOS) in which N-channel TFTs and P-channel TFTs are mixed on a substrate
A circuit) can be similarly formed using the above method. N-channel TFT and P-channel TF
In the case where both T are composed of normal TFTs, or both are composed of LDD type TFTs, impurities are introduced by the method of forming only one of the N-channel type or P-channel type TFTs described above on the substrate. The impurities may be introduced into each of the N-type impurities and the P-type impurities.

For example, when the N-channel type TFT which requires countermeasures against hot carriers is the LDD type and the P-channel type TFT which does not require it is a normal TFT, the step of introducing impurities becomes slightly special. In that case, the first
A relatively low concentration of N-type impurities is introduced into the semiconductor layer between the step and the second step. This is the first impurity introduction. At this time, N-type impurities may be introduced into the semiconductor layer of the P-channel TFT. Further, the semiconductor layer of the N-channel TFT is masked, and a high-concentration P-type impurity is introduced only into the semiconductor layer of the P-channel TFT. This is the second impurity introduction. Even if N-type impurities are present in the semiconductor layer of the P-channel TFT due to the introduction of the N-type impurities as described above, a higher concentration of P-channel impurities is introduced, resulting in the conductivity type of the semiconductor. Is P-type. Of course, compared to the impurity concentration introduced in the first impurity introduction, that of the second impurity introduction is larger, preferably one to three orders of magnitude larger.

Finally, a relatively high concentration of N-type impurities is introduced between the second and third steps to form the source / drain of the N-channel TFT. This is the third impurity introduction. In this case, P-channel TFT
The impurities may be introduced by masking so that the N-type impurities are not introduced into the mask, or the mask may not be particularly masked. However, in the latter case, the concentration of the N-type impurity introduced needs to be lower than the concentration of the P-type impurity introduced in the second impurity introduction, and preferably the second
The concentration is 1/10 to 2/3 of the P-type impurity concentration of the impurity introduction. As a result, N-type impurities are also introduced into the region of the P-channel TFT, but since the impurity concentration is lower than the concentration of P-type impurities introduced before that, the P-type is maintained.

[0014]

In the present invention, the presence of the sidewall improves the step coverage of the interlayer insulating material at the portion where the gate wiring is crossed over, and can reduce the disconnection of the second wiring. Further, as described above, it is possible to obtain the LDD structure by using the sidewall.
In the present invention, the presence of the anodic oxide coating is important. In the above second step, anisotropic etching is performed to form sidewalls. However,
It was difficult to control the plasma on the insulating surface, and variations in etching within the substrate were unavoidable. If the anodic oxide is not formed on the upper surface of the gate electrode, the gate electrode may be severely etched depending on the location even in the same substrate. The presence of the anodic oxide coating stops the etching and protects the gate electrode. Hereinafter, the present invention will be described in more detail with reference to examples.

[0015]

【Example】

Example 1 FIG. 1 shows this example. First, the substrate (Corning 7059, 300 mm x 400 mm or 1
A silicon oxide film having a thickness of 1000 to 5000 Å, for example, 2000 Å, was formed as a base oxide film 102 on a (00 mm × 100 mm) 101. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. But,
In order to enhance the mass productivity, TEOS may be formed by decomposing / depositing by the plasma CVD method. Further, the silicon oxide film thus formed may be annealed at 400 to 650 ° C.

After that, an amorphous silicon film of 300 to 500 is formed by a plasma CVD method or an LPCVD method.
0Å, preferably 400 to 1000Å, for example 500
Å Deposit and place this in a reducing atmosphere at 550 to 600 ° C for 8
Allow to crystallize by standing for ~ 24 hours. In that case, a small amount of a metal element such as nickel that promotes crystallization may be added to promote crystallization. Further, this step may be performed by laser irradiation. Then, the crystallized silicon film was etched to form the island-shaped region 103. Further, a thickness of 700 to 1500Å, for example 1200Å
The silicon oxide film 104 was formed.

Thereafter, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc (scandium)) film having a thickness of 1000 Å to 3 μm, for example 5000 Å, is formed by a sputtering method, and this film is formed. Etching was performed to form the gate electrode 105 and the gate wiring 106. (FIG. 1 (A)) Then, an electric current is applied to the gate electrode 105 and the gate electrode 106 in an electrolytic solution to perform anodic oxidation to obtain a thickness of 500 to 250
0Å, for example, 2000Å anodized oxide 107, 108
Was formed. The electrolytic solution used was prepared by diluting L-tartaric acid in ethylene glycol at a concentration of 5% and adjusting the pH to 7.0 ± 0.2 using ammonia. The substrate 101 is dipped in the solution, the + side of the constant current source is connected to the gate wiring on the substrate, and the platinum electrode is connected to the-side of the substrate for 20 m.
Voltage was applied in the constant current state of A, and oxidation was continued until it reached 150V. Furthermore, the oxidation was continued at a constant voltage of 150 V until the current became 0.1 mA or less. As a result, an aluminum oxide film having a thickness of 2000Å was obtained.

After that, an impurity (here, phosphorus) is self-alignedly injected into the island-shaped silicon film 103 by ion doping using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) as a mask. As shown in FIG. 1B, a low concentration impurity region (LDD) 109 was formed.
The dose amount is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage is 10 to 90 kV. For example, the dose amount is 5 × 10.
^{It was 13} atoms / cm ² and the acceleration voltage was 80 kV. (Fig. 1
(B))

Then, a silicon oxide film 110 was deposited by the plasma CVD method. Here, the source gas is TEO
S and oxygen, or monosilane and nitrous oxide were used.
The optimum value of the thickness of the silicon oxide film 110 differs depending on the height of the gate electrode / wiring. For example, as in this embodiment, the height of the gate electrode / wiring is about 60 including the anodic oxide film.
In case of 00Å, 1/3 to 2 times of 2000Å
1.2 μm is preferable, and here, it is 6000 Å.
In this film forming process, it is required that the film thickness be uniform in the flat portion and that the step coverage be good. As a result, the thickness of the silicon oxide film on the side surface of the gate electrode / wiring is increased by the amount shown by the dotted line in FIG. (Fig. 1 (C))

Next, anisotropic dry etching is performed by the known RIE method to obtain the silicon oxide film 1.
08 etching was performed. This etching was completed when the etching reached the gate insulating film 105. Regarding the end point of such etching, for example,
It is possible to control the gate insulating film 105 by making the etching rate smaller than that of the silicon oxide film 110. Through the above steps, the substantially triangular insulators (sidewalls) 111 and 112 remained on the side surfaces of the gate electrode / wiring. (Fig. 1 (D))

After that, phosphorus was introduced again by the ion doping method. The dose amount in this case is as shown in FIG.
It is preferable that the dose is 1 to 3 orders of magnitude larger than the dose in the step. In this embodiment, the dose is 2 × 10 ¹⁵ atoms / cm ^{2 which} is 40 times the dose of the first phosphorus doping. Acceleration voltage is 80kV
And As a result, a region (source / drain) 114 into which a high concentration of phosphorus was introduced was formed, and a low concentration region (LDD) 113 was left below the sidewall.
(Fig. 1 (E))

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . In this embodiment, since aluminum is used for the gate electrode and wiring, there is a problem in heat resistance and it is difficult to implement, but thermal annealing may be used instead of laser irradiation.

Finally, an interlayer insulator 115 is formed on the entire surface.
A silicon oxide film having a thickness of 5000 Å was formed by the CVD method. Then, contact holes are formed in the source / drain of the TFT, and the second-layer aluminum wiring / electrode 11 is formed.
6, 117 were formed. The thickness of the aluminum wiring was set to 4000 to 6000Å, which is almost the same as that of the gate electrode / wiring. Through the above steps, a TFT having an N-channel LDD was completed. To activate the impurity region,
Further, hydrogen annealing may be performed at 200 to 400 ° C. Since the step of the second layer wiring 117 over the gate wiring 106 is gentle due to the presence of the sidewall 112, the thickness of the second layer wiring is almost the same as that of the gate electrode / wiring. Regardless, almost no breaks were observed. (Fig. 1 (F))

Regarding the thickness of the second layer wiring, as a result of the study by the present inventor, the thickness of the gate electrode / wiring is x
[Å] When the thickness of the second layer wiring was y [Å] and y ≧ x-1000 [Å], there was no noticeable disconnection. The smaller the value of y is, the more preferable it is. Particularly in the case of a circuit which requires a small unevenness on the substrate surface such as an active matrix circuit of a liquid crystal display, x-1000 [Å] ≤ y ≤ x + 1000 [Å] Was found to be suitable.

[Second Embodiment] FIG. 2 shows the present embodiment. The present embodiment relates to a so-called monolithic active matrix circuit in which an active matrix circuit and its drive circuit are simultaneously manufactured on the same substrate. In this embodiment, a P-channel TFT is used as the switching element of the active matrix circuit, and a complementary circuit composed of an N-channel TFT and a P-channel TFT is used as the drive circuit. On the left side of FIG. 2, N used in the drive circuit is shown.
A manufacturing process sectional view of a channel type TFT is shown, and a manufacturing process sectional view of a P channel type TFT used for a drive circuit and an active matrix circuit is shown on the right side of the figure. P for the switching element of the active matrix circuit
The channel type TFT is used because the leak current (also referred to as off current) is small.

First, the substrate (Corning 7059) 201
Similar to the first embodiment, the base oxide film 202, the island-shaped silicon semiconductor region, and the silicon oxide film 2 functioning as a gate oxide film are formed above.
03, and gate electrodes 204 and 205 made of an aluminum film (thickness 5000Å) were formed. Thereafter, as in Example 1, anodic oxidation was performed to form 2,000 Å-thick anodic oxide around the gate electrode (side surface and upper surface).
Then, phosphorus was implanted by ion doping using the gate electrode portion as a mask to form low-concentration N-type impurity regions 206 and 207. The dose amount was 1 × 10 ¹³ atoms / cm ² .

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . (FIG. 2A) After that, the region of the N-channel type TFT is covered with the photoresist 2
After masking with No. 08, in this state, high concentration boron doping was performed by an ion doping method. The dose amount was 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 65 kV. As a result, due to the previous doping of phosphorus, the impurity region 207 that has become a weak N type is inverted to a strong P type and becomes a P type impurity region 209. After that, the impurities were activated again by laser irradiation. (Fig. 2
(B)) In this embodiment, the high concentration boron is partially selectively doped after the low concentration phosphorus is entirely doped, but this step may be reversed.

After removing the photoresist mask 208, a thickness of 4000 to 8000 is formed by plasma CVD.
A Å silicon oxide film 210 was deposited. (FIG. 2 (C)) Then, as in Example 1, anisotropic etching was performed to obtain
A side wall 211 of silicon oxide on the side surface of the gate electrode,
212 was formed. (FIG. 2D) After that, phosphorus was introduced again by the ion doping method. In this case, the dose amount is preferably one to three orders of magnitude larger than the dose amount in the step of FIG. 2A, and 1/10 to 2/3 of the dose amount in the step of FIG. 2B. In this embodiment, the dose of the first phosphorus doping is 200 times 2 × 10 ^15.
Atom / cm ² . However, this is 40% of the dose of boron in the step of FIG. Acceleration voltage is 80k
It was set to V. As a result, a region (source / drain) 213 in which a high concentration of phosphorus was introduced was formed, and a low concentration impurity region (LDD) 214 was left below the sidewall.

Furthermore, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . On the other hand, phosphorus was also doped in the region of the P-channel TFT (on the right side of the figure), but the concentration of the previously doped boron was 2.5 times that of phosphorus, so that it remained P-type. Apparently, there are two types of P-type regions of the P-channel TFT, that is, a region 216 below the sidewall and a region 215 outside the sidewall (opposite the channel formation region) 215, but from the viewpoint of electrical characteristics. There was no significant difference between the two. (Fig. 2 (E))

Finally, as shown in FIG. 2F, a silicon oxide film having a thickness of 3000 Å is formed as an interlayer insulator 217 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and aluminum is formed. Wiring / electrode 2
18, 219, 220 and 221 were formed. Through the above steps, a semiconductor integrated circuit in which the N-channel TFT is the LDD type is completed. Although not shown in the figure, at the portion where the second-layer wiring crosses over the gate wiring, almost no disconnection was observed as in Example 1, although the interlayer insulating material was not so thick.

As in this embodiment, the N-channel TFT is set to L
The DD structure is provided to prevent deterioration due to hot carriers. However, since the LDD region is a parasitic resistance inserted in series with the source / drain, there is a problem that the operation speed is reduced. Therefore, it is desirable that the LDD does not exist in the P-channel TFT, which has low mobility and is less deteriorated by hot carriers, as in this embodiment. Although the doping impurities are activated by laser irradiation in each doping step in this embodiment, they may be collectively performed just before forming the interlayer insulator after all the doping steps are completed.

[Embodiment 3] This embodiment will be described with reference to FIG. The present example shows an example in which the degree of etching for forming the sidewall is variously changed in the first example. First, the one shown in FIG. 3A will be described. The TFT region 301 and the gate wiring 302 are shown in the figure. A manufacturing process for obtaining such a structure is similar to that described in Embodiment 1 with reference to FIGS. However, in this embodiment, the sidewall 30
In the process of anisotropic etching for forming 4,
Since the etching was performed slightly overetching, the sidewall 304 is located slightly below the upper surface of the gate electrode / wiring. In addition, the gate insulating film 303
It will be etched up to.

In this embodiment, the etching rate of the material forming the side wall 304 is about twice that of the gate insulating film 303. Therefore, even under the same etching conditions, the etching depth of the gate insulating film was about half that of the sidewalls. In this example, the gate insulating film was etched to about half the initial thickness. On the other hand, the thickness of the gate insulating film 303 'existing below the sidewall 304 and the gate electrode / wiring is the same as the initial thickness. Further, since the gate electrode / wiring was covered with the anodic oxide, it was hardly damaged even in the anisotropic etching process for forming the sidewall.

In such a state, the interlayer insulator 30
5 was formed on the entire surface. The sidewall 304 is the first embodiment.
Although it is located at a position slightly lower than the gate wiring 302, unlike the conventional case, since the step near the gate wiring 302 is gentle, the interlayer insulating material is sufficient for the gate wiring crossover portion 308.
Was covered. After that, the second layer wiring 306, 307
However, since the interlayer insulator 305 is gently undulated at the gate overpassing portion 308, there was no disconnection at that portion.

FIG. 3B shows a case where the etching rate of the material forming the sidewall 354 is almost the same as that of the gate insulating film 353. Therefore, under the same etching conditions, the gate insulating film and the sidewalls were etched in almost the same manner. In this example, the gate insulating film was completely etched, and the active layer of the TFT was exposed.
Also in this case, the undulation of the inter-layer insulator 355 is gentle at the gate-over portion, so that the second-layer wiring 35
There was no disconnection in that part of 6, 357. Generally, it is difficult to leave only half the gate insulating film as shown in FIG. 3A, and it is easier to leave the gate insulating film completely as shown in FIG. 1 or FIG. Is.

[Embodiment 4] Using the present invention, an active matrix circuit and its peripheral drive circuit, and further a CP
An example in which circuits such as U are also formed on the same glass substrate is shown.
A block diagram of the entire circuit is shown in FIG. All the TFTs forming these circuits are formed on the same substrate 14.
In FIG. 6, 11 is a TFT provided in one pixel of the active matrix circuit, 12 is a pixel electrode, and 1 is a pixel electrode.
3 is an auxiliary capacitor. In the configuration shown in FIG. 6, T formed in each pixel of the active matrix circuit
In addition to FT11, TF that further configures the circuit of input port, correction memory, memory, CPU, XY branch, X decoder / driver, Y decoder / driver
All Ts are formed on the same substrate. (Fig. 6)

In FIG. 6, an input port is a panel for reading a signal input from the outside and converting it into an image signal, and a correction memory is a panel for correcting the input signal and the like in accordance with the characteristics of the active matrix panel. It is a unique memory. In particular, this correction memory has information unique to each pixel as a non-volatile memory and is used for individual correction. That is, when a pixel of the electro-optical device has a point defect, a signal corrected accordingly is sent to the pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when the pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so that the pixel has the same brightness as the surrounding pixels.

The CPU and the memory have the same functions as those of an ordinary computer, and in particular, the memory has an image memory corresponding to each pixel as a RAM. Further, the backlight for irradiating the substrate from the back side can be changed according to the image information. A schematic cross section of such a circuit is shown in FIG. The circuit is roughly divided into an active matrix circuit (pixel circuit) region and a region other than the active matrix circuit, such as a peripheral drive circuit, a CPU, and a memory. In this embodiment, a complementary circuit including an N-channel TFT 15 and a P-channel TFT 16 is used in the area other than the active matrix circuit. The manufacturing method is the same as that shown in Example 2 and FIG. Also, in the active matrix circuit, TF
A P-channel type TFT 11 was used as T, and its production was carried out at the same time as the production of the P-channel type TFT in the complementary circuit. (Fig. 5)

[Embodiment 5] FIG. 7 shows the present embodiment. This embodiment is an example in which an LDD-type N-channel TFT and a normal P-channel TFT are formed on the same substrate as in the second embodiment. The left side of FIG. 7 is a sectional view of the manufacturing process of the N-channel TFT, and the right side of the figure is the P-channel TFT.
The manufacturing process sectional drawing of is shown. First, the substrate (Corning 70
59) A base oxide film 702, an island-shaped silicon semiconductor region, and a silicon oxide film 703 functioning as a gate oxide film on 701.
And the gate electrodes 704, 70 of an aluminum film (thickness 5000 Å) whose surface is covered with anodic oxide.
5 was formed.

Further, the gate oxide film in the N-channel type TFT portion was selectively removed by using the gate electrode 704 as a mask to expose the semiconductor layer. Then, phosphorus is implanted by an ion doping method using the gate electrode portion as a mask to form a low concentration N-type impurity region 706.
Dose amount is 1 × 10 ¹³ atoms / cm ² , accelerating voltage is 20k
It was set to eV. In this doping step, phosphorus was not doped in the island-shaped region 707 of the P-channel TFT covered with the gate oxide film 703 because the acceleration voltage was low. (Figure 7 (A))

After that, the region of the N-channel TFT was masked with a photoresist 708, and in this state, high-concentration boron was doped by an ion doping method. The dose amount was 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 65 kV. As a result, a P-type impurity region 709 was formed in the island region 707. (FIG. 7 (B)) In the present embodiment, high-concentration boron partial selective doping was carried out after low-concentration phosphorus overall doping, but this step may be reversed. After removing the photoresist mask 708, a silicon oxide film 710 having a thickness of 4000 to 8000 Å was deposited by a plasma CVD method.
(Fig. 7 (C))

Then, as in Example 2, by anisotropic etching, sidewalls 711 and 712 of silicon oxide were formed on the side surfaces of the gate electrode. (FIG. 7D) After that, phosphorus was introduced again by the ion doping method. In this case, the dose amount is preferably 1 to 3 digits larger than the dose amount in the step of FIG. In this embodiment, the dose of the first phosphorus doping is 200 times 2 ×.
It was set to 10 ¹⁵ atoms / cm ² . The acceleration voltage was 20 kV. As a result, a region (source /
A drain) 713 was formed, and a low concentration impurity region (LDD) 714 was left below the sidewall. On the other hand, in the P-channel type region, since the gate oxide film exists, phosphorus ions were not implanted. In the second embodiment, phosphorus and boron are implanted at a high concentration in the P-channel TFT, so that the dose amount is limited, but in the present embodiment, the dose amount is not limited. However, regarding the accelerating voltage, it is necessary to lower phosphorus and increase boron as described above. (Fig. 7 (E))

After the doping step, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. Laser energy density is 200 ~ 400mJ /
cm ^2, and a preferably suitably 250~300mJ / cm ^2. Finally, as shown in FIG. 7F, a silicon oxide film with a thickness of 5000 Å is formed as an interlayer insulator 715 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and an aluminum wiring / electrode is formed. 71
6, 717, 718, and 719 were formed. Through the above steps, a semiconductor integrated circuit in which the N-channel TFT is the LDD type is completed.

In this embodiment, as compared with the second embodiment, N
An additional photolithography process and etching process are required to remove the gate oxide film in the channel TFT portion. However, since N-type impurities are not substantially introduced into the P-channel TFT,
There is also an advantage that the doses of the P-type and P-type impurities can be relatively arbitrarily changed. In addition, phosphorus injected into the vicinity of the surface of the gate oxide film 703 of the P-channel TFT is effective in forming phosphorus glass and preventing entry of mobile ions such as sodium in the subsequent laser irradiation step.

[Sixth Embodiment] FIG. 8 shows a sixth embodiment. This embodiment relates to a method for manufacturing an active matrix liquid crystal display, which will be described with reference to FIG. T on the left side of FIG.
The two FTs are LDD-type N-channel TFs, respectively.
T is a normal P-channel TFT, and shows a logic circuit used for peripheral circuits and the like. Further, the TFT on the right side is a switching transistor used in the active matrix array, which is an offset P-channel TFT. First, a base oxide film, an island-shaped silicon semiconductor region (the island-shaped region 8 for a peripheral circuit) on a substrate (Corning 7059).
01, island-shaped region 80 for active matrix circuit
2), a silicon oxide film 803 that functions as a gate oxide film is formed, and further, a gate electrode 80 of an aluminum film (thickness 5000Å) whose surface is covered with anodic oxide.
4, 805 (for peripheral circuits) and 806 (for active matrix circuits) were formed.

Further, the gate oxide film in the P-channel type TFT portion for the peripheral circuit and the active matrix circuit was selectively removed by using the gate electrodes 804 and 806 as masks to expose the semiconductor layer. Further, the active matrix circuit area was masked with a photoresist 807. Then, boron is implanted by an ion doping method using the gate electrode portion as a mask to form a high concentration P-type impurity region 808. The dose amount was 1 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 20 keV. In this doping step, since the acceleration voltage is low, the region of the N-channel TFT covered with the gate oxide film 803 was not doped with boron. (Figure 8 (A))

After that, low-concentration phosphorus was doped by the ion doping method. Dose amount is 1 × 10
^{It was 13} atoms / cm ² and the acceleration voltage was 80 kV. As a result, a low concentration N-type impurity region 809 was formed in the N-channel TFT region. (FIG. 8B) Although the photoresist mask 806 is removed in the drawing for doping, the doping may be performed with the photoresist still attached. Since the accelerating voltage of phosphorus is high, if doping is performed with the photoresist left, phosphorus is not injected into the active matrix circuit region, so an ideal offset P-channel TFT can be obtained. The resist may be carbonized and it may take time to remove it.

Even when the photoresist is removed, the phosphorus concentration is high, so that the phosphorus concentration has a peak below the island-shaped semiconductor region. However, there is no guarantee that phosphorus is not completely doped, and a small amount of phosphorus is formed in the semiconductor region. However, in this case, even if phosphorus is doped, its concentration is low, and P ⁺ (source) / N ⁻ / I (channel) / N ⁻ / P ⁺ (drain)
This structure is suitable as a TFT for an active matrix circuit that needs to reduce a leak current. After that, a silicon oxide film 710 having a thickness of 4000 to 8000 Å is deposited by plasma CVD method, and by anisotropic etching as in the second embodiment, sidewalls 810 and 81 of silicon oxide are formed on the side surfaces of the gate electrode.
1, 812 was formed. (Fig. 8 (C))

Then, again, boron was introduced by the ion doping method. The dose amount in this case is shown in FIG.
It is desirable that the dose amount is approximately the same as the dose amount in the step (A). In this embodiment, the dose amount is 1 × 10 ¹⁵ atoms / c
m ² and the acceleration voltage were 20 keV. Since the accelerating voltage is low, the N-channel type TFT in which the gate oxide film 803 exists
Region is not doped with boron, and is mainly used in the P channel type T of the peripheral circuit and the active matrix circuit.
The FT source / drain was doped. As a result, the source / drain 813 of the TFT of the active matrix circuit was formed. This TFT has an offset structure in which the gate electrode and the source / drain are separated.
(Figure 8 (D))

Next, phosphorus was doped. In this case, the first phosphorus doping step, as shown in FIG.
It is preferable that the dose amount is larger than that of (B) by 1 to 3 digits. In this embodiment, the dose is set to 5 × 10 ¹⁴ atoms / cm ^{2, which} is 50 times the dose of the first phosphorus doping. Accelerating voltage is 8
It was set to 0 kV. As a result, a region (source / drain) 814 in which a high concentration of phosphorus is introduced is formed, and a low concentration impurity region (LDD) 815 is formed under the sidewall.
Was left. On the other hand, in the P-channel type TFT region, most of the phosphorus ions were implanted into the base film and did not significantly affect the conductivity type. (Fig. 8 (E))

After the doping step, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. Laser energy density is 200 ~ 400mJ /
cm ^2, and a preferably suitably 250~300mJ / cm ^2.

Then, as the first interlayer insulator 816, a silicon nitride film having a thickness of 5000 Å is formed by the CVD method, contact holes are formed in the source / drain of the TFT, and aluminum wirings / electrodes 817, 818, 81 are formed.
9, 820 were formed. The peripheral circuit region is formed by the above steps. (FIG. 8F) Further, as the second interlayer insulator 821, a silicon oxide film having a thickness of 3000 Å is formed by the CVD method, and this is etched to form a contact hole, which is transparent to the TFT of the active matrix circuit. By the conductive film, the pixel electrode 8
22 was formed. In this way, an active matrix type liquid crystal display substrate was produced. (Fig. 8 (G))

[0053]

As described above, according to the present invention, it is possible to reduce the disconnection of the second layer wiring in the gate wiring crossover portion. In particular, an integrated circuit is composed of a large number of elements and wirings, but if any one of them is defective, the entire circuit may become unusable. Needless to say, the fact that the number of such defects can be significantly reduced by the present invention has a very great effect in increasing the yield rate of integrated circuits.

Further, according to the present invention, the thickness of the second layer wiring can be set to the same degree as that of the gate electrode / wiring, specifically, the gate electrode / wiring ± 1000 [Å]. This has a great effect, and it is suitable for an active matrix circuit of a liquid crystal display, which is required to have less unevenness on the substrate surface. In addition, the merit obtained by using the present invention is “action”.
As described in section. Thus, the present invention is a TFT
It is of great benefit in improving the yield of integrated circuits.

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a TFT circuit according to a first embodiment.

FIG. 2 shows a method of manufacturing a TFT circuit according to a second embodiment.

FIG. 3 shows a method for manufacturing a TFT circuit according to a third embodiment.

FIG. 4 shows a method of manufacturing a TFT by a conventional method.

FIG. 5 shows a cross-sectional view of a TFT circuit according to a fourth embodiment.

FIG. 6 shows a block diagram of a TFT circuit according to a fourth embodiment.

FIG. 7 shows a method of manufacturing a TFT circuit according to a fifth embodiment.

FIG. 8 shows a method for manufacturing a TFT circuit according to a sixth embodiment.

[Explanation of symbols]

101 glass substrate 102 Underlayer oxide film (silicon oxide) 103 island-shaped silicon region (active layer) 104 Gate insulation film 105, 106 Gate electrode (aluminum) 107, 108 Anodic oxide (aluminum oxide) 109 Weak N-type impurity region 110 Insulator coating (silicon oxide) 111,112 Sidewall 113 LDD (low concentration impurity region) 114 source / drain 115 Interlayer insulation film (silicon oxide) 116, 117 Metal wiring / electrode (aluminum)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-1-119066 (JP, A) JP-A-2-2149 (JP, A) JP-A-5-232515 (JP, A) JP-A-61- 125165 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/3205

Claims (11)

(57) [Claims] 1. A P-channel thin film transistor and N
In the method for manufacturing a semiconductor integrated circuit having a channel thin film transistor, forming the island-shaped semiconductor layer, a gate insulating film covering the semiconductor layer, and the gate electrode on the gate insulating film, a gate wiring, the gate electrode And each of the above gate wirings with anodic acid
By reduction, the gate electrode and the oxide film formed on at least the upper surface of each of the gate lines, wherein the gate electrode and the oxide film as a mask, a self-aligning manner a first N-type impurity, P-channel type thin film transistor And N-channel thin film transistors are formed in the semiconductor layer, and the region where the N-channel thin film transistors are formed is masked with a resist, using the resist, the gate electrode, and the oxide film as a mask to self-align. A P-type impurity is introduced into the semiconductor layer in a region where a P-channel thin film transistor is to be formed, the resist is removed, an insulator is formed to cover the gate electrode, the gate wiring and the oxide film. Etching the insulator by etching, And a substantially triangular insulator is formed on each side surface of the gate wiring, and the second N-type impurity is self-aligned to the P-channel thin film transistor using the gate electrode and the substantially triangular insulator as a mask. And a method for manufacturing a semiconductor integrated circuit which is introduced into the semiconductor layer in a region where the N-channel thin film transistor is formed, wherein a dose amount of the second N-type impurity to be introduced is the first
The method for manufacturing a semiconductor integrated circuit is characterized in that it is one to three orders of magnitude larger than the dose amount of the N-type impurity and is 1/10 to 2/3 of the dose amount of the P-type impurity. 2. A P-channel thin film transistor and N
In the method for manufacturing a semiconductor integrated circuit having a channel thin film transistor, forming the island-shaped semiconductor layer, a gate insulating film covering the semiconductor layer, and the gate electrode on the gate insulating film, a gate wiring, the gate electrode And each of the above gate wirings with anodic acid
By reduction, the forming the gate electrode and the gate interconnects each of the at least upper surface oxide film, is masked with a resist region for forming the N-channel thin film transistor, the resist, the gate electrode and the oxide film as a mask, A P-type impurity is introduced in a self-aligning manner into the semiconductor layer in a region where a P-channel thin film transistor is formed, the resist is removed, and the first N-type is self-aligned using the gate electrode and the oxide film as a mask. Type impurities are introduced into the semiconductor layer in the regions where the P-channel type thin film transistor and the N-channel type thin film transistor are respectively formed, an insulator is formed to cover the gate electrode, the gate wiring and the oxide film, and anisotropic etching is performed. By etching the insulating material, A substantially triangular insulator is formed on each side surface of the gate wiring, and the second N-type impurity is self-aligned to the P-channel thin film transistor by using the gate electrode and the substantially triangular insulator as a mask. A method of manufacturing a semiconductor integrated circuit, which is introduced into the semiconductor layer in a region where each of the N-channel thin film transistors is formed, wherein a dose amount of the second N-type impurity to be introduced is the first
The method for manufacturing a semiconductor integrated circuit is characterized in that it is one to three orders of magnitude larger than the dose amount of the N-type impurity and is 1/10 to 2/3 of the dose amount of the P-type impurity. 3. A method for manufacturing a semiconductor integrated circuit having a P-channel type thin film transistor and an N-channel type thin film transistor on an insulating surface, comprising: an island-shaped semiconductor layer, a gate insulating film covering the semiconductor layer, and the gate insulating film. A gate electrode and a gate wiring are formed on the gate electrode, and the gate electrode and the gate wiring are respectively anodized.
By reduction, the gate electrode and the oxide film on at least the upper surface of each of the gate line is formed, the gate insulating film provided on the island-shaped semiconductor layer to form the N-channel thin film transistor, said gate electrode Selectively removed as a mask, and using the gate insulating film, the gate electrode, and the oxide film as a mask, the first N-type impurity is introduced in a self-aligned manner into the semiconductor layer in a region where an N-channel thin film transistor is formed. , A region for forming an N-channel type thin film transistor is masked with a resist, P-type impurities are self-aligned with the resist, the gate electrode and the oxide film as a mask, and the gate insulation of a region for forming a P-channel type thin film transistor is performed. It is introduced into the semiconductor layer through the film, the resist is removed, and the gate electrode is removed. Forming an insulator covering the gate wiring and the oxide film, and etching the insulator by performing anisotropic etching to form a substantially triangular insulator on each side surface of the gate electrode and the gate wiring. A semiconductor that is formed and introduces a second N-type impurity into the semiconductor layer in a region for forming an N-channel thin film transistor in a self-aligned manner by using the gate insulating film, the gate electrode, and the substantially triangular insulator as a mask. A method of manufacturing an integrated circuit, wherein the concentration of the second N-type impurity to be introduced is equal to that of the first N-type impurity.
A method of manufacturing a semiconductor integrated circuit, wherein the concentration of the impurity is higher than that of the impurity. 4. A method of manufacturing a semiconductor integrated circuit having a P-channel thin film transistor and an N-channel thin film transistor on an insulating surface, comprising: an island-shaped semiconductor layer, a gate insulating film covering the semiconductor layer, and the gate insulating film. A gate electrode and a gate wiring are formed on the gate electrode, and the gate electrode and the gate wiring are respectively anodized.
By reduction, the gate electrode and the oxide film on at least the upper surface of each of the gate line is formed, the gate insulating film provided on the island-shaped semiconductor layer to form the N-channel thin film transistor, said gate electrode A region for forming an N-channel type thin film transistor is selectively removed as a mask, and a region for forming an N-channel type thin film transistor is masked with a resist. It is introduced into the semiconductor layer through the gate insulating film in the region to be formed, the resist is removed, and the first N-type is self-aligned using the gate insulating film, the gate electrode, and the oxide film as a mask. Impurities are introduced into the semiconductor layer in the region where an N-channel thin film transistor is formed, Forming an insulator covering the gate wiring and the oxide film, and etching the insulator by performing anisotropic etching to form a substantially triangular insulator on each side surface of the gate electrode and the gate wiring. A semiconductor that is formed and introduces a second N-type impurity into the semiconductor layer in a region for forming an N-channel thin film transistor in a self-aligned manner by using the gate insulating film, the gate electrode, and the substantially triangular insulator as a mask. A method of manufacturing an integrated circuit, wherein the concentration of the second N-type impurity to be introduced is equal to that of the first N-type impurity.
A method of manufacturing a semiconductor integrated circuit, wherein the concentration of the impurity is higher than that of the impurity. 5. A method of manufacturing a semiconductor integrated circuit having a P-channel thin film transistor and an N-channel thin film transistor on an insulating surface, comprising: an island-shaped semiconductor layer, a gate insulating film covering the semiconductor layer, and the gate insulating film. A gate electrode and a gate wiring are formed on the gate electrode, and the gate electrode and the gate wiring are respectively anodized.
By reduction, the gate electrode and the oxide film on at least the upper surface of each of the gate line is formed, the gate insulating film provided on the island-shaped semiconductor layer to form a P-channel thin film transistor, said gate electrode Selectively removed as a mask, P-type impurities are introduced into the semiconductor layer of the P-channel type thin film transistor in a self-aligning manner by using the gate insulating film, the gate electrode and the oxide film as a mask. Using the oxide film as a mask, the first N-type impurity is introduced in a self-aligned manner into the semiconductor layer through the gate insulating film in the region where the N-channel thin film transistor is formed, and the gate electrode, the gate wiring, and Etch the insulator by forming an insulator over the oxide film and performing anisotropic etching. Forming a substantially triangular insulator on each side surface of the gate electrode and the gate wiring, and using the gate electrode and the substantially triangular insulator as a mask to self-align the second N-type impurity. A method of manufacturing a semiconductor integrated circuit, which is introduced into the semiconductor layer by passing through the gate insulating film in a region for forming an N-channel thin film transistor, wherein the concentration of the second N-type impurity to be introduced is the first N
A method of manufacturing a semiconductor integrated circuit, wherein the concentration of the impurity is higher than that of the impurity. 6. The method according to any one of claims 1 to 5 ,
A method for manufacturing a semiconductor integrated circuit, wherein part of a circuit of a CPU is formed by the P-channel thin film transistor and the N-channel thin film transistor, and the CPU is formed over a glass substrate. 7. An N-channel thin film transistor and P
In a semiconductor integrated circuit having a channel type thin film transistor, a gate wiring, an island-shaped first semiconductor layer in a region where a P channel type thin film transistor is formed, a first gate insulating film covering the first semiconductor layer, and the first gate A first gate electrode formed on the insulating film; an island-shaped second semiconductor layer in a region where an N-channel thin film transistor is formed; a second gate electrode formed on the second semiconductor layer; A second gate insulating film formed between the gate electrode and the second semiconductor layer; and an oxide film formed by anodic oxidation on the upper surfaces of the first gate electrode, the second gate electrode and the gate wiring, respectively. P-type impurities are formed in the first semiconductor layer and pass through the first gate insulating film in a self-aligned manner using the first gate electrode and the oxide film as a mask. And input source and drain regions, formed in said second semiconductor layer, the first gate insulating film,
A low-concentration impurity region in which the first N-type impurity is introduced in a self-aligning manner using the first gate electrode, the second gate electrode, and the oxide film as a mask, and the first gate electrode in contact with the oxide film , The second
A substantially triangular insulator provided on each side surface of the gate electrode and the gate wiring; and the first gate insulating film formed on the second semiconductor layer,
A first gate electrode, a second gate electrode, and a source region and a drain region in which the second N-type impurity is introduced in a self-aligned manner using the substantially triangular insulator as a mask; A semiconductor integrated circuit, wherein the layer is not covered with the second gate insulating film. 8. An N-channel thin film transistor and P
In a semiconductor integrated circuit having a channel type thin film transistor, a gate wiring, an island-shaped first semiconductor layer in a region where an N channel type thin film transistor is formed, a first gate insulating film covering the first semiconductor layer, and the first gate. A first gate electrode formed on the insulating film; an island-shaped second semiconductor layer in a region for forming a P-channel thin film transistor; a second gate electrode formed on the second semiconductor layer; A second gate insulating film formed between the gate electrode and the second semiconductor layer; and an oxide film formed by anodic oxidation on the upper surfaces of the first gate electrode, the second gate electrode and the gate wiring, respectively. A first gate insulating film formed on the second semiconductor layer,
A source region and a drain region in which P-type impurities are introduced in a self-aligned manner using the first gate electrode, the second gate electrode, and the oxide film as a mask, and the first gate electrode formed in the first semiconductor layer. A low-concentration impurity region in which the first N-type impurity is introduced through the first gate insulating film in a self-aligning manner using the second gate electrode and the oxide film as a mask, and is in contact with the oxide film, The first gate electrode, the second
A substantially triangular insulator provided on each side surface of the gate electrode and the gate wiring, and the first gate electrode, the second gate electrode and the generally triangular insulator formed on the first semiconductor layer. The mask has a source region and a drain region in which the second N-type impurity is introduced through the first gate insulating film in a self-aligning manner as a mask, and the second semiconductor layer is covered with the second gate insulating film. A semiconductor integrated circuit characterized by not being exposed. 9. The thickness of a wiring connected to the source region and the drain region according to claim 7,
[Å], where y−Å is the thickness of the first gate electrode, the second gate electrode, and the gate wiring, y−1000 ≦ x ≦ y + 1000. 10. The circuit according to claim 7 , wherein a part of a circuit of a CPU is formed by the P-channel type thin film transistor and the N-channel type thin film transistor, and the CPU is formed on a glass substrate. A semiconductor integrated circuit characterized in that 11. The pixel according to claim 7 , further comprising a pixel having a thin film transistor, and a drive circuit for driving the pixel, wherein the drive circuit includes the P channel type thin film transistor and the N channel type thin film transistor. A semiconductor integrated circuit having.