JPH07111334A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a channel forming region and a source/drain electrode to be lessened in gap and resistance between them by a method wherein a triangular insulator is provided adjacent to an insulating layer located on the side face of a gate electrode, a silicide layer is formed on a part of a source/ drain region, and no silicide layer is provided to the source/drain region under the insulator. CONSTITUTION:A ground oxide film 102, a source/drain region 103, a channel forming region 104, a gate insulating film 105, and a gate electrode 106 are formed on a substrate 101, and an oxide film 107 is formed surrounding the gate electrode 106, then, an insulating film 108 is formed, the surface of the source/drain region 103 is exposed by anisotropical etching, and a triangular insulator 9 is left unremoved on the side wall of the gate electrode 106. Next, a metal film 110 is formed over all the surface of the substrate 101 and made to react with silicon contained in the source/drain region 103 to form a silicide layer 111 by annealing. At this point, an active region under the insulator 109 is of impurity semiconductor and serves as a source/drain region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention refers to an insulating substrate (in this specification, refers to the entire object having an insulating surface, and unless otherwise specified, not only on an insulating material such as glass but also on a material such as a semiconductor or a metal. It also means that an insulating layer is formed on the insulating gate type semiconductor device and a method for forming an integrated circuit in which a large number of them are formed. A semiconductor device according to the present invention is a thin film transistor (TF) in a drive circuit such as an active matrix such as a liquid crystal display or an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor memory or the like).
It is used as T).

[0002]

2. Description of the Related Art Heretofore, there has been widely known a structure in which a TFT (thin film transistor) is used in a device integrated on a glass substrate such as an active matrix type liquid crystal display device or an image sensor. FIG. 3 shows an outline of a cross section of a conventional TFT and an example of a manufacturing process. FIG. 3 shows an insulating gate type field effect transistor (hereinafter simply referred to as a TFT) using a thin film silicon semiconductor provided on a glass substrate.
That is). The manufacturing process will be briefly described below. In FIG. 3A, 301 is a glass substrate,
On this glass substrate 301, an underlying silicon oxide film 302 (2
(Thickness of about 000Å) is formed, and an island-shaped active layer 303 formed of a silicon semiconductor film is further formed thereon. This silicon semiconductor film has a thickness of about 500 to 2000 liters and has an amorphous property or a crystalline property (polycrystal, microcrystal, etc.). A silicon oxide film 304 forming a gate insulating film is formed on the active layer in an amount of 1000 to 15
It is formed with a thickness of about 00Å.

Next, a gate electrode 305 is formed of doped polycrystalline silicon, tantalum, titanium, aluminum or the like. (FIG. 3B) Furthermore, using the gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by means such as ion doping, and the source / drain regions (impurity regions) 306 are self-aligned to form the active layer 303. Is formed. The active layer region below the gate electrode into which the impurities have not been introduced becomes the channel formation region 307. (FIG. 3C) Further, the doped impurities are activated by a heat source such as a laser or a flash lamp.
(Fig. 3 (D))

Next, a silicon oxide film is formed by means of plasma CVD, APCVD or the like, and this is used as an interlayer insulator 30.
7 Further, a contact hole is formed in the source / drain region through the interlayer insulator, and a wiring / electrode 308 connected to the source / drain is formed by a metal material such as aluminum. (Fig. 3 (E))

In such a conventional TFT, characteristics (especially electric field mobility and subthreshold characteristics (S
In order to improve (value)), it was necessary to reduce the sheet resistance of the source / drain regions. For that purpose, the doping amount (concentration) of impurities is increased. Energize enough (energy of laser and flash lamp). The distance between the channel formation region 307 and the metal electrode 308 (indicated as z in the figure) is shortened. Three things have been considered.

However, with respect to the above, there is a problem that if the doping amount is increased, the processing time is increased, the throughput is lowered, and the active layer and the gate insulating film 304 are greatly damaged. In particular, when using a method (ion doping method or plasma doping method) of making a gas containing a doping element into a plasma and accelerating and injecting it as an impurity introduction means, mass productivity is excellent, but the acceleration A large number of hydrogen and other elements are contained in the generated ions, and there is a problem that the substrate is easily heated. In particular, this problem became remarkable when the density of plasma was increased.

The problem is that the element is heated and damaged during doping, or if a photoresist is used as a doping mask, it is carbonized and its removal becomes extremely difficult. It was

Also, with respect to the above, when the energy is large, the active layer and the gate electrode are peeled off, which causes a reduction in the yield of the TFT. Also, the throughput was reduced. For example, when a laser is used, the energy of the laser itself cannot be changed significantly, so it is necessary to increase the beam focusing degree and increase the energy density. This inevitably reduces the area of the beam, increasing the time required to process the same area.

Further, as for the above, it is determined by the accuracy of the mask alignment, and an extreme improvement cannot be expected. In particular, when a glass substrate is used as the substrate, shrinkage of the glass substrate in the heating step (which requires various annealing steps) poses a serious problem in mask alignment. For example, for a glass substrate of 10 cm square or more, 5
When a heat treatment of about 00 ° C. is applied, it shrinks easily by about several μm. Therefore, at present, the distance z is set to about 20 μm to provide a margin. Moreover, when z is small, the gate electrode 305 and the source / drain electrode 30
The parasitic capacitance between the TFTs 8 and 8 was increased, which adversely affected the characteristics of the TFT.

Further, when forming a contact hole in the source / drain region 306, it is required to perform etching with a slight overshoot in order to surely form the contact hole. Therefore, the distance indicated by z is required. It cannot be shortened indiscriminately. As described above, in the conventional TFT, it is extremely difficult to further reduce the parasitic resistance of the source / drain regions.

[0011]

SUMMARY OF THE INVENTION The present invention solves the above problems, and substantially eliminates the problem of the channel forming region and the source / source region.
By reducing the distance between the drain electrode and the drain electrode and decreasing the resistance between the drain electrode and the drain electrode, it is possible to obtain high characteristics.
The task is to obtain T. Furthermore, it aims at achieving the above-mentioned subject while being excellent in mass productivity.

[0012]

In the present invention, an oxide film is formed by oxidizing the gate electrode on at least the side surface, preferably the side surface and the upper surface of the gate electrode. It is preferable that this oxide film has excellent insulating properties. Then, a substantially triangular insulator is formed further outside the oxide of the gate electrode. The width of the substantially triangular insulator is preferably 1 μm or less. Then, a silicide is formed in close contact with the source / drain regions (in a self-aligned manner) so as to match the substantially triangular insulator. Since this silicide has a much smaller specific resistance than the doped polycrystalline silicon, the resistance is sufficiently small even if it is very thin.

In the present invention, it is desirable that the metal material forming the silicide is a material that enables the silicide to form a low-resistance contact with the silicon semiconductor, which is ohmic or near ohmic. In particular,
Molybdenum (Mo), tungsten (W), platinum (platinum, Pt), chromium (Cr), titanium (Ti), cobalt (Co) are suitable. In order to carry out the present invention,
At least one of these metals is reacted with silicon to form a silicide.

FIG. 1 shows an example embodying the above technical idea.
A process for obtaining the TFT having the above structure is also shown. The present invention will be described using this. On the substrate 101, the underlying oxide film 102, the source / drain regions 103, the channel forming regions 104, the gate insulating film 10 are formed by known means.
5 and a gate electrode 106 containing a metal or alloy such as aluminum, titanium or tantalum as a main component is formed. The oxide layer 107 of the gate electrode is formed around the gate electrode.
Is formed. Thermal oxidation or anodic oxidation is suitable for forming the oxide layer. In particular, when a metal or alloy mainly containing aluminum, titanium or tantalum is used for the gate electrode, it is desirable to obtain the oxide layer by the anodic oxidation method. Since the doping of impurities is performed in self-alignment with the oxide layer 107, the source / drain regions and the gate electrode are in an offset state. (Fig. 1
(A))

When the anodic oxidation method is adopted in the present invention, it is important to select the material of the gate electrode because it also determines the type of anodic oxide. In the present invention, the gate electrode may be a pure metal such as aluminum, titanium, tantalum, or silicon, or an alloy obtained by adding a small amount of additive thereto (for example, 1 to 3% of aluminum).
Alloy with added silicon or 1000ppm to silicon
˜5% phosphorus added), conductive silicides such as tungsten silicide (WSi ₂ ) and molybdenum silicide (MoSi ₂ ), and conductive nitrides typified by titanium nitride can be used. In the present specification, unless otherwise specified, for example, aluminum includes not only pure aluminum but also those containing 10% or less of an additive. The same is true for silicon and other materials.

In the present invention, a single-layered gate electrode using these materials alone may be used, or these may be used as the gate electrode.
A multi-layered gate electrode in which more layers are stacked may be used. For example, it has a two-layer structure in which tungsten silicide is stacked on aluminum and a two-layer structure in which aluminum is stacked on titanium nitride. The thickness of each layer may be determined by a practitioner according to the required device characteristics.

Next, an insulating film 108 is formed. It is important that this coating has excellent coverage on the side surface of the gate electrode. (FIG. 1 (B)) Then, this insulating film is anisotropically etched by a method such as a dry etching method. That is, only the vertical direction is selectively etched. As a result, the surface of the source / drain region is exposed, and a substantially triangular insulator 109 is formed on the side surface of the gate electrode (including the surrounding oxide layer 107).
Remains. (Fig. 1 (C))

The dimensions of this substantially triangular insulator 109,
In particular, the width is determined by the thickness of the insulating film 108 formed in advance, the etching conditions, the gate electrode (the surrounding oxide layer 1
(Including the thickness of the oxide layer 107 in this case). The value of the insulating coating 108 is generally about 2000 to 20000Å,
It may be determined according to the embodiment. The shape of the obtained insulator 109 is not limited to the triangular shape, and the shape changes depending on the step coverage and the film thickness of the insulating coating 108. For example, when the film thickness is small, the shape is rectangular. However, for the sake of simplicity, in the following description, the insulator 109 is referred to as a substantially triangular insulator as shown in the drawing. Next, a coating 110 of a suitable metal such as titanium, molybdenum, tungsten, platinum, palladium or the like is formed on the front surface of the substrate.
(Fig. 1 (D))

Then, a silicide layer is formed by reacting the metal film with silicon in the source / drain regions by annealing at an appropriate temperature, annealing with a laser or a flash lamp, or the like. The metal film remains in a metal state without reacting with other materials such as silicon oxide or silicon nitride, or aluminum oxide, titanium oxide, tantalum oxide, or the like which forms the oxide layer 107 of the gate electrode. Thus, the silicide and the metal film are simultaneously present on the substrate, but with an appropriate etchant,
Only the metal film can be selectively etched. At this time, it is important that the oxide layer 107 exists on the upper surface of the gate electrode. This is because the metal layer 110 and the gate electrode 106 do not directly react with each other due to this oxide layer. In this way, only the silicide layer 111 is left in close contact with the source / drain regions. (Fig. 1
(E))

When the metal film is irradiated with intense light such as laser light and reacted with the underlying silicon semiconductor film to form a silicide, a pulsed laser is preferable.
Since the irradiation time of the continuous wave laser is long, there is a risk that the object to be irradiated expands due to heat and peels off.

Regarding the pulse laser, Nd: YAG
Infrared laser such as laser (preferably Q-switch pulse oscillation) or visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl and ArF can be used, but when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select the laser light that passes through the underlying silicon semiconductor film.

Although the silicide layer 111 is drawn thinner than the active layer in the drawing, the silicide layer 111 may have the same thickness as the active layer as shown in FIG. Needless to say. However, the silicide layer 1
Whatever the thickness of 11 is, the active layer region under the insulator 109 is an impurity semiconductor and is a source / drain region. The types of silicide used in the silicide layer 110 include Ti using TiSi, TiSi ₂ , and Mo using MoSi.
₂ , W using WSi ₂ , W (SiAl) ₂ , TiSi ₂ using Ti ₇ Si
Pd ₄ SiAl ₃ can be used with ₁₂ Al ₅ and Pd ₂ Si. However, it is preferable to use TiSi or TiSi ₂ instead of Ti in terms of processing temperature, contact resistance, and sheet resistance.

After that, an interlayer insulator 112 is deposited, a contact hole is formed in the silicide layer 111, a metal electrode / wiring 113 is formed, and the TFT is completed.
(FIG. 1F) As described above, in the TFT of the present invention, the silicide layer 111
The resistance between the channel forming region and the metal electrode may be substantially determined by the distance denoted by x in FIG. And x is
Since it is preferably 1 μm or less, the resistance is remarkably reduced. Of course, the distance between the contact hole and the gate electrode may be unchanged.

The above-mentioned offset (denoted by y in the figure) has the effect of reducing the leak current of the TFT.
Still another preferred embodiment of the present invention is shown in FIG.
Also in this example, the base oxide film 20 is formed on the substrate 201.
2. Source / drain region 203 and channel forming region 2
The active layer having 04, the gate insulating film 205, the gate electrode 206 and the surrounding oxide layer 207 are formed in the same manner as in FIG. (Fig. 2 (A))

After that, the gate insulating film 205 is self-alignedly etched using the gate electrode and the oxide layer 107 around the gate electrode as a mask. For example, when the oxide layer 107 is mainly composed of aluminum oxide and the gate insulating film is mainly composed of silicon oxide, a fluorine-based (eg, NF ₃ , SF ₆ ) etching gas is used. ,
Dry etching may be performed. With these etching gases, the gate insulating film made of silicon oxide is quickly etched, but the etching rate of aluminum oxide is sufficiently small that selective etching is possible. Then, an insulating coating 208 is deposited on the front surface. (Fig. 2
(B))

Further, this is etched by anisotropic etching as in the case of FIG. 1 to leave a substantially triangular insulator 209 on the side surface of the gate electrode. Then, a suitable metal film 210 is deposited. (FIG. 2C) This is reacted with silicon by appropriate heat treatment, laser irradiation or the like to obtain a silicide layer 211. (Fig. 2
(D) After that, the interlayer insulator 212 and the metal electrode / wiring 213 are formed. (Fig. 2 (E))

By appropriately controlling the reaction of the silicide, the silicide layer 211 can be formed with the surface of the active layer as the center, as shown in FIGS. 2D and 2E. As described above, it is optional to use the entire active layer as the silicide layer 211. Further, in any case, the resistance between the channel forming region and the source / drain electrodes is sufficiently small, as in the case of FIG.

[0028]

The function of the present invention is to substantially shorten the distance between the channel forming region and the source / drain electrodes and reduce the resistance therebetween, as shown in the above example, thereby reducing the TFT.
Is to improve the characteristics of. However, the operation of the present invention is not limited to this. That is, since the above resistance can be sufficiently reduced, the amount of impurity doping into the source / drain regions can be reduced. For example, typically 1x10
A dose of ¹⁵ to 8 × 10 ¹⁵ cm ⁻² is required, which is reduced by one digit or more by the present invention to 5 × 10 ¹³ to 1.
It can be set to × 10 ¹⁵ cm ^-2 . Thus, even with a small amount of doping, the characteristics are improved as compared with the conventional case. Therefore, the doping time can be simply shortened to 1/10.

Further, with such a low concentration doping, the damage at the boundary between the channel forming region and the source / drain region is small. In particular, when impurities are activated by means such as laser annealing, the gate electrode and the like are shadowed, and the activation of the boundary between the channel formation region and the source / drain region tends to be insufficient, resulting in a large amount of impurities. The deterioration of characteristics due to doping has been a problem.

Next, the active layer can be thinned. That is, since the sheet resistance of the source / drain was large in the conventional method, the thickness of the active layer is 1000 Å or less, particularly 500 Å ~
It was difficult to set it to 50Å. However, the present invention removes such constraints. That is, since the silicide layer has a low specific resistance of 10 ⁻³ to 10 ⁻⁵ Ωcm,
Even if the thickness is 100Å, the sheet resistance is 1
It is 0Ω to 1 kΩ. The fact that the active layer is thin means that the film formation time of the active layer can be shortened and that the leakage current and disconnection (step breakage) due to poor step coverage of the gate insulating film and the gate electrode can be suppressed. That is, it contributes to the improvement of the yield.

The silicide layer in the present invention is, for example,
It is advantageous in forming a contact when it is formed in a region including a PN junction. That is, when the wiring is drawn from the P-type region and the N-type region having the PN junction, whether the contact holes are formed in both the P-type region and the N-type region,
Either method was needed. That is, if the contact is formed only in the P-type region or the N-type region, the signal cannot be taken out from the other region by the PN junction. The former method requires two contact holes, and the latter method reduces the allowable deviation of contact holes. In any case, it was a big obstacle in terms of circuit miniaturization. On the other hand, when the silicide layer is formed in the PN junction, the contact only needs to be provided at one place somewhere in the silicide layer, and the allowable deviation of the contact hole becomes considerably large. As a result, it is advantageous in miniaturizing the circuit.

[0032]

【Example】

Example 1 FIG. 1 shows this example. First, the substrate (Corning 7059, 300 mm x 400 mm or 1
A silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 102 on (00 mm × 100 mm) 101.
As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to improve mass productivity,
A film obtained by decomposing / depositing TEOS by the plasma CVD method is used.
You may anneal at 0-650 degreeC.

After that, an amorphous silicon film of 30 to 500 n is formed by plasma CVD or LPCVD.
m, preferably 50-100 nm, which is 55
It was left to stand in a reducing atmosphere at 0 to 600 ° C. for 24 hours for crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this way was patterned to form island regions. further,
A silicon oxide film 105 having a thickness of 70 to 150 nm was formed on this by a sputtering method.

After that, aluminum having a thickness of 100 nm to 3 μm (1 wt% Si, or 0.1 to 0.3 wt) is used.
% Sc (scandium) film is formed by an electron beam evaporation method, and this is patterned to form a gate electrode 106, which is further anodized by applying an electric current in an electrolytic solution to form an anode having a thickness of 50 to 250 nm. The oxide 107 was formed. Regarding conditions for anodic oxidation, etc., see JP-A 5-2
The one shown in 67667 was used.

After that, by the ion doping method, impurities are self-alignedly implanted into the island-shaped silicon film of each TFT by using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) as a mask. Source / drain regions (impurity regions) 103 were formed as shown in A).
To form an NMOS TFT, a phosphine (P
Phosphorus is injected using H ₃ ) as a doping gas, and boron can be injected using diborane (B ₂ H ₆ ) as a doping gas to form a PMOS TFT. Dose is 2
8 × 10 ¹⁴ cm ^-2 , acceleration energy is 10 to 90 keV
And Then, a thickness of 400 is obtained by the plasma CVD method.
nm-1.5 μm, for example 900 nm of silicon oxide film 10
8 was deposited. (Fig. 1 (B))

Next, the silicon oxide film 108 is formed by performing anisotropic dry etching by the known RIE method.
Was etched. At this time, the height is 900
On the side surface of the gate electrode 106 having a thickness of nm, the thickness in the height direction is approximately twice the film thickness (which is 900 nm of the silicon oxide film). At this time, the silicon oxide film 105, which is the gate insulating film, is also continuously etched,
The source / drain region 103 is exposed. Through the above steps, the substantially triangular insulator 109 remained on the side surface of the gate electrode. (Fig. 1 (C))

After that, as shown in FIG.
A tungsten film 110 having a thickness of ˜50 nm was formed by the sputtering method. Then, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to react tungsten with silicon to form a tungsten silicide region 111 on the impurity region (source / drain). Laser energy density is 200 ~ 400mJ /
cm ^2, and a preferably suitably 250~300mJ / cm ^2. Much of the laser light was absorbed by the tungsten film and thus was barely utilized to restore the crystallinity of the underlying silicon impurity region, which was significantly damaged by previous ion doping. However, tungsten silicide is 30 to 100 μΩ · c
Since the resistivity was as low as m, the sheet resistance of the substantial source and drain regions (region 108 and the impurity region thereunder) was 10Ω / □ or less.

Of course. Immediately after the step of introducing impurities, the crystallinity deteriorated by introducing impurities may be restored by laser irradiation, thermal annealing, or the like. Then, Figure 1
As shown in (E), the unreacted tungsten film was etched to leave only the tungsten silicide. As an etching method at this time, for example, when reactive etching is performed in a fluorocarbon atmosphere, tungsten is converted into tungsten hexafluoride, which can be evaporated and removed.

Finally, an interlayer insulator 112 is formed on the entire surface.
A silicon oxide film having a thickness of 300 nm was formed by the CVD method. A contact hole was formed in the source / drain of the TFT, and an aluminum wiring / electrode 113 was formed. By the above, the TFT was completed. Hydrogen activation may be further performed at 200 to 400 ° C. to activate the impurity regions.

[Second Embodiment] FIG. 2 shows the present embodiment. First, a base oxide film 202, an island-shaped silicon semiconductor region, and a silicon oxide film 205 functioning as a gate oxide film are formed on a substrate (Corning 7059) 201 as in the first embodiment.
A gate electrode 206 was formed from an aluminum film (thickness: 200 nm to 5 μm). After that, the anodic oxide 207 was formed around the gate electrode (side surface and upper surface) by anodic oxidation in the same manner as in Example 1. Then, using the gate electrode as a mask, impurities are implanted by an ion doping method to form impurity regions 203. Dose is 1-5
It was set to × 10 ¹⁴ cm ^-3 .

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . (Fig. 2 (A))

This activation may be performed by lamp annealing by irradiation with infrared light. Alternatively, known heating may be used. However, annealing with infrared rays (for example, infrared rays of 1.2 μm) does not heat the glass substrate so much because the infrared rays are selectively absorbed by the silicon semiconductor, and the heating time for the glass substrate is shortened by shortening the irradiation time once. It can be suppressed and is extremely useful. Then, the gate oxide film was etched by the dry etching method using the anodic oxide 207 as a mask. For example, if CF ₄ is used as the etching gas, the anodic oxide is not etched, but only the gate insulating film 205 made of silicon oxide is etched. Then, a silicon oxide film 208 having a thickness of 400 nm to 1.5 μm was deposited by the plasma CVD method.

Then, similar to Example 1, anisotropic etching was used to form a substantially triangular insulator 209 of silicon oxide on the side surface of the gate electrode. After that, as shown in FIG. 2C, a titanium film 210 having a thickness of 5 to 50 nm was formed by a sputtering method. Next, this is 250-450 ℃
Then, titanium and silicon are reacted with each other to form a titanium silicide region 211 on the impurity region (source / drain). At this time, it is desirable that the heating is performed at a temperature at which hillocks are not generated on the gate electrode or the like.

This annealing may be performed by infrared lamp annealing. When performing lamp annealing, it is advisable to perform lamp irradiation so that the surface to be irradiated has a temperature of about 600 to 1000 ° C., and for example, at 600 ° C. for several minutes and at 1000 ° C. for several seconds. Further, since aluminum is used for the gate electrode here, the thermal annealing after forming the titanium film is performed up to 450 ° C. However, when the gate electrode containing silicon as a main component is used,
You may perform at the temperature of 00 degreeC or more.

After that, the Ti film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at 5: 2: 2. At this time, since the silicide layer 211 was not etched, it could be left. Finally, Figure 2
As shown in (E), as an interlayer insulator 212 on the entire surface,
A silicon oxide film having a thickness of 300 nm is formed by the CVD method,
A contact hole was formed in the source / drain of the TFT, and an aluminum wiring / electrode 213 was formed. The TFT was completed by the above steps.

[Embodiment 3] FIG. 4 shows the present embodiment. This example relates to a process of manufacturing an active matrix type liquid crystal display substrate. First, as shown in FIG. 4A, a base oxide film 402, an island-shaped silicon semiconductor region, and a silicon oxide film 405 functioning as a gate oxide film are formed on a substrate (Corning 7059) 401 as in the first embodiment. , An aluminum film (thickness: 200 nm to 5 μm) and a gate electrode 407 and a wiring (first layer wiring) 406 in the same layer were formed. Then, anodic oxides 408 and 409 were formed around the gate electrode (side surface and upper surface) by anodic oxidation as in Example 1. Then, impurities are introduced by ion doping, and the impurity regions 40
Formed 3. Furthermore, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² .

Then, as shown in FIG. 4B, a silicon oxide film 410 was deposited. Then, similar to Example 1, anisotropic etching was performed to form substantially triangular insulators 411 and 412 on the side surfaces of the gate electrode and the first layer wiring. Also, the source / drain regions were exposed. Then, a titanium film having a thickness of 5 to 50 nm was formed by a sputtering method. Since the substrate temperature during the film formation was 200 to 450 ° C., preferably 200 to 300 ° C., titanium and silicon reacted during the film formation to form a silicide layer 413 on the surface of the source / drain regions.

After that, as shown in FIG. 4C, the titanium film which did not react was etched. Then, a silicon oxide film having a thickness of 600 nm was formed as the interlayer insulator 414 on the entire surface by a CVD method. Further, an ITO film having a thickness of 50 to 100 nm was deposited by a sputtering method and patterned to form a pixel electrode 415. Finally, Figure 4
As shown in (D), contact holes were formed in the source / drain of the TFT, a multilayer film of titanium nitride and aluminum was deposited, and this was patterned to form a second layer wiring / electrode 416. The thicknesses of titanium nitride and aluminum were 80 nm and 500 nm, respectively. Through the above steps, the active matrix substrate was completed.

FIG. 4E shows a circuit of one pixel in the active matrix manufactured in this embodiment. In this embodiment, the source / drain electrode 416 and the gate electrode 40
Even if 7 is sufficiently separated, the sheet resistance of the source / drain does not matter, and since the gate electrode is an offset gate, the parasitic capacitance C _P between the gate electrode and the source / drain region (or source / drain electrode) is Is small enough, ideal for an active matrix. Therefore, the storage capacitor C _{S formed} in parallel with the pixel capacitor may be sufficiently small or may not be provided at all. Therefore, the aperture ratio of the pixel is improved.

The intersecting portions of the first-layer aluminum wiring 406 and the second-layer wiring 416 are shown in FIGS. 4D and 4E.
Is a region indicated by 417. This intersection 41
In Example 7, the presence of the insulator 412 made the step uneven, and the probability of disconnection of the wiring 416 was significantly reduced.

Although the peripheral circuit provided for driving the active trix can be manufactured by using the TFT of this embodiment, the anodic oxide 409 is made thinner than in the case of this embodiment (pixel TFT). Or may not be provided at all. This is because the pixel TFT needs to reduce the influence of the parasitic capacitance C _P , while the TFT in the peripheral circuit needs less.

[Fourth Embodiment] FIGS. 5 and 6 show the present embodiment. FIG. 5 is a block diagram of a monolithic circuit in which an active matrix region and a peripheral circuit region for driving the active matrix region are formed on the same substrate. Depending on how the peripheral circuits are arranged, two types of cases as shown in FIG. 5 or other cases can be considered. Where 53,
Reference numeral 58 denotes an active matrix area, which includes 51, 52,
Reference numerals 54 to 57 are peripheral circuit areas. Further, 50 and 59 are substrates.

A point to be noted in constructing such a monolithic circuit is that the TFT required in the active matrix region and the TFT required in the peripheral circuit region have different characteristics. That is, the former needs to hold the charge accumulated in the pixel electrode or the like, and therefore requires a small leak current (off current). On the other hand, the latter has excellent high-speed operation characteristics,
That is, a large on-current is required. However, these characteristics are contradictory, and it is difficult to manufacture a TFT that satisfies both characteristics at the same time.

In order to solve such a problem, the TFTs in the peripheral circuit area and the TFTs in the active matrix area are made suitable for their respective characteristics, as shown in this embodiment or Embodiments 5 to 8. Is desirable. The manufacturing process of this example will be briefly described below.

Crystalline silicon regions 603 and 604 were formed on the substrate 601 and the underlying film 602 thereon. Here, the region 603 is a silicon region used for the TFT in the peripheral circuit region, and the region 604 is a silicon region used for the TFT in the active matrix circuit region. The region 604 may contain oxygen, carbon, or nitrogen at 5 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ . As a result, the leak current of the TFT in the active matrix region can be further reduced. Ion implantation or the like may be used to introduce oxygen, nitrogen, carbon, or the like. After the formation of the crystalline silicon region, a gate oxide film 605 is formed, and a gate electrode 606 to
608 was formed. (Fig. 6 (A))

Then, only the gate electrode 608 was energized in the electrolytic solution to form the anodic oxide layer 609 on the side surface and the upper surface of the gate electrode 608. Then, impurities are introduced by means such as ion doping, and the P-type region 610,
N-type regions 611 and 612 were formed. Further, the impurities were activated by irradiation with laser light. As a result, in the TFT in the active matrix region, the gate electrode is in an offset state with the source / drain by the distance indicated by y. As y, for example, 1500 to 35
It was set to 00Å. (Fig. 6 (B))

After that, an insulating layer 613 of silicon oxide is formed on the entire surface.
Was formed. (FIG. 6C) Then, the peripheral circuit region is masked to expose the active matrix region, and as shown in FIG.
By anisotropic etching, a substantially triangular insulator 614 was formed on the side surface of the gate electrode of the TFT. Then, in this state, a titanium film was formed and reacted with the exposed silicon film of the TFT in the active matrix region to form a silicide layer 615. (Figure 6 (D))

After that, an interlayer insulator 616 was formed on the entire surface, an ITO film was further formed, and this was patterned to form a pixel electrode 617. And the interlayer insulator 61
6, a contact hole is opened, and metal electrodes 618 to 62
Formed 2. By the above, a monolithic active matrix circuit could be manufactured. (Fig. 6 (E))

[Embodiment 5] This embodiment is shown in FIG. This embodiment also relates to a monolithic circuit in which an active matrix region and a peripheral circuit region for driving the same are formed on the same substrate as in the fourth embodiment. Crystalline silicon regions 703 and 704 were formed on the substrate 701 and the underlying film 702 thereon. Here, the region 703 is a silicon region used for the TFT in the peripheral circuit region, and the region 704 is a silicon region used for the TFT in the active matrix circuit region.

After the formation of the crystalline silicon region, a gate oxide film 705 is formed, and the gate electrodes 706 to 706 are made of a metal material (for example, aluminum) which can be anodized.
708 was formed. (FIG. 7 (A)) Then, the gate electrodes 706 to 708 are energized in an electrolytic solution to form the anodic oxide layer 70 on the side surface and the upper surface of the gate electrode.
9-711 was formed. At this time, the time for energizing the gate electrodes 706 and 707 was set shorter than the time for energizing the gate electrode 708. As a result, the anodic oxide layer 70
The thickness of 9, 710 is thinner than that of the anodic oxide layer 711. Therefore, the offset distance y ′ of the TFT in the peripheral circuit region is smaller than the offset distance y of the active matrix region. For example, y is 2000 to 350
0Å and y ′ were set to 500 to 1500Å.

In this way, the T of the active matrix region is
By anodizing not only the gate electrode of the FT but also the gate electrode of the TFT in the peripheral circuit region, it is possible to prevent the gate electrode / wiring from being damaged by subsequent heat treatment or laser irradiation. In particular, when a metal material containing aluminum as a main component is used as a material for the gate electrode / wiring, hillocks are generated at a high temperature of 300 ° C. or higher. However, if an anodic oxide film having such a thickness is formed, Hillock was prevented. After that, impurities are introduced by means such as ion doping, and the P-type region 712 and the N-type region 71 are
3, 714 was formed. Further, the impurities were activated by irradiation with laser light. (Fig. 7 (B))

After that, an insulating layer 715 of silicon oxide is formed on the entire surface.
Was formed. (FIG. 7C) Then, the peripheral circuit region is masked to expose the active matrix region, and as shown in FIG.
By anisotropic etching, a substantially triangular insulator 716 was formed on the side surface of the gate electrode of the TFT. Then, a titanium film was formed in this state, and this was reacted with the silicon film of the TFT in the exposed active matrix region to form a silicide layer 718. (Figure 7 (D))

After that, an interlayer insulator 719 was formed on the entire surface, an ITO film was further formed, and this was patterned to form a pixel electrode 720. And the interlayer insulator 71
9. Contact holes are opened in 9 and metal electrodes 721 to 72
5 was formed. By the above, a monolithic active matrix circuit could be manufactured. (Fig. 7 (E))

[Sixth Embodiment] FIG. 8 shows a sixth embodiment. This embodiment also relates to a monolithic circuit in which an active matrix region and a peripheral circuit region for driving the same are formed on the same substrate as in the fourth embodiment. Crystalline silicon regions 803 and 804 were formed on the substrate 801 and the underlying film 802 thereon. Here, the region 803 is a silicon region used for the TFT in the peripheral circuit region, and the region 804 is a silicon region used for the TFT in the active matrix circuit region. After forming the crystalline silicon region, a gate oxide film 805 is formed, and further gate electrodes 806 to 808 are formed by using an anodizable metal material (for example, tantalum). (Fig. 8
(A))

Then, the gate electrode 808 was energized in an electrolytic solution to form an anodic oxide layer 809 on the side surface and the upper surface of the gate electrode. After that, impurities are introduced by means such as ion doping, and the P-type region 810 and the N-type region 8
11, 812 were formed. Further, the impurities were activated by irradiation with laser light. (FIG. 8B) After that, an insulating layer 813 of silicon oxide was formed on the entire surface.
(FIG. 8C) Then, as shown in FIG. 1C of Example 1, anisotropic triangular etching was performed to form substantially triangular insulators 814 to 816 on the side surfaces of the gate electrode of the TFT. Then, a titanium film was formed in this state, and this was reacted with the exposed silicon film of the TFT to form silicide layers 817 to 820. (Figure 8 (D))

After that, an interlayer insulator 821 was formed on the entire surface, contact holes were opened in the interlayer insulator 821, and metal electrodes 822 to 826 were formed. By the above, a monolithic active matrix circuit could be manufactured.
(FIG. 8 (E)) Regarding formation of contact holes, FIG.
As shown in (A), the source / drain may be formed to be protruded, and the metal wirings 822 to 826 may be provided. As a result, the circuit design becomes advantageous, and particularly in the active matrix circuit region, it contributes to the improvement of the aperture ratio.
FIG. 11A shows the circuit having the structure shown in FIG. 8E, and FIG. 11B shows the circuit having the structure shown in FIG. Show. As is apparent from the figure, the method of FIG. 10A is advantageous in that the area occupied by the active layer can be saved.

As described above, when the contact hole is formed in the region other than the active layer, the base film 902 is formed as follows.
If a material with a smaller etching rate than the interlayer insulator is used, the substrate will not be over-etched,
preferable. For example, when silicon oxide is used as the interlayer insulator, the base film is formed as a film containing aluminum oxide or aluminum nitride as a main component, or a multilayer film of such a film and a silicon oxide film, and is overetched. Even if this happens, it is advisable to stop the etching with such a film having a high etching rate.

In this embodiment, similar to the fourth embodiment (FIG. 6), the P-channel type TFT and the N-channel type TFT are formed on the same active layer 803, but the metal connected to the drains of both TFTs is used. Unlike the fourth embodiment (FIG. 6), the wiring 823 is connected to the silicide layer 818. on the other hand,
In FIG. 6, the equivalent metal wiring 619 is the P-type region 61.
It must be provided so as to contact both the 0 and N type regions 611. FIG. 11C shows the state of the circuit of FIG. 6E seen from above. As a result, the contact hole is necessarily large. Also, if the position of the contact hole is displaced so that only one of the N-type region and the P-type region is contacted, the other TFT cannot conduct,
It becomes defective. For this reason, the center of the contact hole is required to be within the range shown by b in FIG. 11C, and a large decrease in yield is unavoidable due to the mask shift accompanying the miniaturization of the circuit.

On the other hand, in the present embodiment, the above difficulties are solved. That is, since the silicide layer 818 is a metal region and is connected to both the P-type region 810 and the N-type region 811, it is only necessary to provide a contact at any part of the silicide layer 818 after all. Become. Therefore, the contact hole may be small, and the center of the contact hole should be in the region indicated by a in FIG. 11A, which is advantageous in both improvement of yield and miniaturization of a circuit. It was

Seventh Embodiment FIG. 9 shows this embodiment. This embodiment also relates to a monolithic circuit in which an active matrix region and a peripheral circuit region for driving the same are formed on the same substrate as in the fourth embodiment. Crystalline silicon regions 903 and 904 were formed on the substrate 901 and the underlying film 902 thereon. Here, the region 903 is a silicon region used for the TFT in the peripheral circuit region, and the region 904 is a silicon region used for the TFT in the active matrix circuit region. After forming the crystalline silicon region, a gate oxide film 905 is formed, and further gate electrodes 906 to 908 are formed by using an anodizable metal material (for example, tantalum). (Fig. 9
(A))

Then, the gate electrodes 906 to 908 were energized in an electrolytic solution to form anodic oxide layers 909 to 911 on the side surfaces and the upper surface of the gate electrodes. At this time, the time for energizing the gate electrodes 906 and 907 is set to the gate electrode 9
It was set shorter than the time for energizing 08. As a result, the thickness of the anodic oxide layers 909 and 910 is smaller than that of the anodic oxide layer 911, and therefore the offset distance y ′ of the TFT in the peripheral circuit region is smaller than the offset distance y of the active matrix region. It was

After that, impurities are introduced by means such as ion doping, and P type region 912, N type region 913,
914 was formed. Further, the impurities were activated by irradiation with laser light. (FIG. 9B) After that, an insulating layer 913 of silicon oxide was formed on the entire surface.
(FIG. 9C) Then, as shown in FIG. 1C of Example 1, anisotropic triangular etching was performed to form substantially triangular insulators 916 to 918 on the side surfaces of the gate electrode of the TFT. Then, a titanium film was formed in this state, and this was reacted with the exposed silicon film of the TFT to form silicide layers 919 to 922. (Fig. 9 (D))

After that, an interlayer insulator 923 was formed on the entire surface, contact holes were opened in the interlayer insulator 923, and metal electrodes 924 to 928 were formed. By the above, a monolithic active matrix circuit could be manufactured.
(FIG. 9 (E)) Also in this embodiment, in forming the source / drain contact holes, as shown in FIG. 10 (B),
The metal wiring 9 is formed so as to protrude from the source / drain.
24-928 may be provided. As a result, the circuit design becomes advantageous and the circuit can be miniaturized.

[Embodiment 8] FIG. 12 shows the present embodiment.
This embodiment also relates to a monolithic circuit in which an active matrix region and a peripheral circuit region for driving the same are formed on the same substrate as in the fourth embodiment. A crystalline silicon region 903 is formed on the substrate 1 and the underlying film 2 on the substrate 1.
And 904 were formed. The base film was composed of a silicon oxide film having a thickness of 1000Å on an aluminum nitride film having a thickness of 500Å. Further, both the aluminum nitride film and the silicon oxide film were formed by the sputtering method. Further, the region 3 is a silicon region used for the TFT in the peripheral circuit region, and the region 4 is a silicon region used for the TFT in the active matrix circuit region. After the formation of the crystalline silicon region, the gate oxide film 5 was formed, and further, the gate electrodes 6 to 8 were formed by using an anodizable metal material (eg, tantalum). An anodic oxide layer was formed on the upper and side surfaces of the gate electrode. At this time, the peripheral circuits and the active matrix circuit are anodized so that the thickness of the anodic oxide is different. In this embodiment, the thickness of the anodic oxide of the gate electrodes 6 and 8 (peripheral circuit) is 500 Å, The thickness of the anodic oxide of the electrode 8 (active matrix circuit) was 2500 Å. (Fig. 10 (A))

After that, impurities were introduced by means such as ion doping to form N-type regions 9 and P-type regions 10 and 11. Further, the impurities were activated by irradiation with laser light. Furthermore, an insulating layer 12 of silicon oxide is formed on the entire surface.
Was formed. (FIG. 10 (B)) Then, as shown in FIG. 1 (C) of Example 1, anisotropic triangular etching was performed to form substantially triangular insulators 13 to 15 on the side surfaces of the gate electrode of the TFT. Then, the titanium film 16 was formed in this state. Then, the titanium film in the active matrix circuit was etched to leave the titanium film 16 only in the peripheral circuit region. (Fig. 10
(C))

Next, the titanium film was reacted with the exposed silicon film of the TFT by thermal annealing at 350 ° C. to form silicide layers 17-19. As a matter of course, no silicide was generated in the active matrix circuit in which the titanium film was not present. Then, the unreacted titanium film was removed. (FIG. 10D) Next, the first interlayer insulator 20 is formed on the entire surface, contact holes are opened in the interlayer insulator 20, and the metal electrodes 21 to 2 are formed.
4 was formed. At this time, in this embodiment, the contact hole was designed to protrude from the active layer. (Fig. 10
(E))

Then, the second interlayer insulator 25 was formed. Then, contact holes were opened in the first and second interlayer insulators, an ITO film was selectively formed, and the pixel electrodes 26 of the active matrix circuit were formed. Through the above steps, a monolithic active matrix circuit used for a liquid crystal display was obtained. In the monolithic active matrix circuit obtained in this example, a TFT having silicide was formed in the peripheral circuit region, and in the active matrix circuit, an offset gate type TFT having an offset width of 2500Å was formed.

[0078]

According to the present invention, the substantial resistance between the source and the drain can be remarkably reduced. In the present invention, by forming a silicide film on the surface of the silicon semiconductor (source / drain), the sheet resistance can be significantly reduced, typically to 100Ω / □ or less. In the present invention, a metal film must be formed to obtain this silicide film, but the film formation time is short and there are few problems in mass production.

In the present invention, the impurity region of the silicon semiconductor under the silicide layer may or may not be provided with a step (activation step) for recovering the crystallinity after the ion implantation. For example, when the impurity implantation is performed by the ion doping method, 10 ¹⁵ cm
^When heavy doping of ^-2 or more is performed, a sheet resistance of about 10 kΩ / □ can be obtained without providing an activation process, and a low-resistance silicide layer is formed close to the impurity region as in the present invention. If so, the substantial source or drain sheet resistance is sufficiently low.

However, many defects are present in the silicon semiconductor that has not been subjected to the activation step, which may be unfavorable from the viewpoint of reliability for some purposes. For such a purpose, activation of the impurity region should be performed. However, when laser irradiation is used as the activation step in this case, the purpose is not to optimize the sheet resistance of the impurity region, so it is possible to apply milder conditions than in the conventional case. it can.

Other merits obtained as a result of using the present invention are as described in the section "Operation". As described above, the present invention is remarkably beneficial in improving the characteristics of the TFT and improving the yield thereof.

[Brief description of drawings]

FIG. 1 shows a method of manufacturing a TFT according to a first embodiment.

FIG. 2 shows a method of manufacturing a TFT according to a second embodiment.

FIG. 3 shows a method of manufacturing a TFT by a conventional method.

FIG. 4 shows a method for manufacturing an active matrix substrate according to a third embodiment.

FIG. 5 shows an arrangement example of a monolithic active matrix circuit.

FIG. 6 shows a method for manufacturing an active matrix substrate according to a fourth embodiment.

FIG. 7 shows a method for manufacturing an active matrix substrate according to a fifth embodiment.

FIG. 8 shows a method for manufacturing an active matrix substrate according to a sixth embodiment.

FIG. 9 shows a method for manufacturing an active matrix substrate according to a seventh embodiment.

FIG. 10 shows a structure of an active matrix substrate according to Examples 6 and 7.

FIG. 11 shows an arrangement example of peripheral circuits according to a sixth embodiment.

FIG. 12 shows a method for manufacturing an active matrix substrate according to Example 8.

[Explanation of symbols]

101 Insulating Substrate 102 Base Oxide Film (Silicon Oxide) 103 Source / Drain Region (Impurity Silicon Region) 104 Channel Forming Region 105 Gate Insulating Film (Silicon Oxide) 106 Gate Electrode (Aluminum) 107 Anodic Oxide (Aluminum Oxide) 108 Insulating Property Coating film (silicon oxide) 109 Insulator having substantially triangular shape (silicon oxide) 110 Metal film (tungsten) 111 Silicide layer (tungsten silicide) 112 Interlayer insulating film (silicon oxide) 113 Metal wiring / electrode (aluminum)

Claims (13)

[Claims] 1. In a thin film transistor, a second insulating material having a substantially triangular shape is provided in close contact with a first insulating layer on a side surface of a gate electrode, and a silicide layer is formed on at least a part of a source / drain region. A semiconductor device characterized in that a silicide layer is not substantially formed in the source / drain regions existing under the second insulator. 2. The semiconductor device according to claim 1, wherein the gate electrode contains aluminum as a main component, and the first insulating layer is mainly composed of an oxide of aluminum. 3. The semiconductor device according to claim 1, wherein the silicide contains titanium. 4. The semiconductor device according to claim 1, wherein silicide is not substantially present on the upper surface of the gate electrode. 5. The semiconductor device according to claim 1, wherein the silicide is present on substantially the entire side surface of the end portion of the source / drain region. 6. The semiconductor device according to claim 1, wherein a contact hole for forming an electrode provided on at least one of the source and the drain is protruded from the active layer. 7. A step of selectively forming a first insulator containing an element forming a gate electrode on at least a side surface of the gate electrode, and covering the gate electrode and the first insulator on the surface thereof, The step of forming the second insulating material, and the step of etching the second insulating material by performing anisotropic etching to leave the substantially triangular insulating material on the side surface of the gate electrode, and the step of forming the source region and the drain region. A method for manufacturing a semiconductor device, comprising: exposing a surface of the insulator to a substantially triangular shape; and forming a silicide layer on the exposed surface of the source / drain region. 8. An electronic circuit having an active matrix region and a peripheral circuit region for driving the same on the same substrate, wherein a thin film transistor used in the active matrix region has at least an upper surface of a gate electrode and an anode of the gate electrode. A semiconductor device having an oxide layer and a silicide layer formed on at least a part of the source / drain regions. 9. The channel region of a thin film transistor used in the active matrix region according to claim 8, contains at least one element of oxygen, nitrogen and carbon in an amount of 5 × 10 ^{19 to} 5 × 10 ²¹ cm ^−3. A semiconductor device characterized in that 10. In an electronic circuit having an active matrix region and a peripheral circuit region for driving the same on the same substrate, a thin film transistor used in the peripheral circuit has a silicide layer in at least a part of a source / drain region. A semiconductor device characterized by being formed. 11. An electro-optical device comprising the semiconductor device according to claim 10. 12. The semiconductor device according to claim 10, wherein the peripheral circuit region is divided into three regions. 13. At least two gate electrodes are present on one thin film semiconductor region having a P-type region and an N-type region, and an anodic oxide layer of the gate electrode is present on at least an upper surface of the gate electrode. And between the P-type region and the N-type region or between the P-type region and the N-type region
A semiconductor device characterized in that a silicide layer exists on the boundary of the type region, and the silicide layer is provided with a contact with another wiring.