JP4657361B2 - Semiconductor device - Google Patents

Description

The present invention relates to an insulating gate type transistor (hereinafter referred to as TFT) formed on an insulating surface such as an insulating material such as glass or a material in which an insulating film such as silicon oxide is formed on a silicon wafer, and a manufacturing method thereof. The present invention is particularly effective for a TFT formed on a glass substrate having a glass transition point (also referred to as strain temperature or strain point) of 750 ° C. or lower. The semiconductor device according to the present invention is used for an active matrix such as a liquid crystal display, a driving circuit such as an image sensor, or a three-dimensional integrated circuit.

Conventionally, it is widely known that a TFT is formed for the purpose of driving an active matrix type liquid crystal display device or an image sensor. In particular, recently, due to the necessity of high-speed operation, a crystalline silicon TFT having higher electric field mobility has been developed in place of an amorphous silicon TFT using amorphous silicon as an active layer. However, when more advanced characteristics and high durability are required, a high-resistance impurity region (high-resistance drain (HRD) or low-concentration drain (LDD)) as used in semiconductor integrated circuit technology is included. It was needed. However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular, since the element is formed on the insulating surface and reactive ion anisotropic etching cannot be performed sufficiently, there is a great restriction that a fine pattern cannot be formed.

FIG. 6 shows a cross-sectional view of a typical process for manufacturing an HRD used to date. First, a base film 602 is formed over a substrate 601 and an active layer is formed using crystalline silicon 603. Then, an insulating film 604 is formed on the active layer with a material such as silicon oxide. (Fig. 6 (A))

Next, the gate electrode 605 is formed of polycrystalline silicon (doped with an impurity such as phosphorus), tantalum, titanium, aluminum or the like. Furthermore, using this gate electrode as a mask,
Impurity elements (phosphorus and boron) are introduced by means such as ion doping, and high resistance impurity regions (HRD) 606 and 607 with a small amount of doping are formed in the active layer 603 in a self-aligned manner. The active layer region under the gate electrode into which no impurity has been introduced becomes a channel formation region. The doped impurities are activated by a heat source such as a laser or a flash lamp. (Fig. 6 (B))

Next, an insulating film 608 such as silicon oxide is formed by means such as plasma CVD or APCVD (FIG. 6C), and this is anisotropically etched, so that the side wall 609 is formed adjacent to the side surface of the gate electrode. Form. (Fig. 6 (D))
Then, an impurity element is introduced again by means such as ion doping, and the gate electrode 6
Highly doped impurity regions (low resistance impurity regions, source / drain regions) 610 and 611 are formed in the active layer 603 in a self-aligning manner using the 05 and the side wall 609 as a mask. The doped impurities are activated by a heat source such as a laser or a flash lamp. (Fig. 6 (E))

Finally, an interlayer insulator 612 is formed, contact holes are formed in the source / drain regions through the interlayer insulator, and wiring / electrodes 613 and 614 connected to the source / drain are formed by a metal material such as aluminum. To do. (Fig. 6 (F))

The above method follows the LDD manufacturing process in the conventional semiconductor integrated circuit as it is, and is a process that is difficult to apply as it is to the TFT manufacturing process on the glass substrate or is not preferable in terms of productivity. There is.

First, the activation of impurities by irradiation with a laser or the like is required twice. For this reason, productivity falls. In conventional semiconductor integrated circuits, activation of impurity elements has been performed by thermal annealing. For this reason, the activation of impurities was performed collectively after the introduction of impurities was completed.

However, especially for TFTs on glass substrates, it is difficult to perform thermal annealing due to substrate temperature constraints.
TA or RTP). However, in these methods, since the irradiated surface is selectively annealed, for example, a portion under the side wall 609 is not annealed. Therefore, annealing is required for every impurity doping.

The second is the difficulty in forming the side wall. The insulating film 608 has a thickness of 0.5 to 2 μm. Usually, since the thickness of the base film 602 provided on the substrate is 100 to 300 nm, the base film is often mistakenly etched in this etching process, and the substrate is often exposed, resulting in a decrease in yield. . Since the substrate used for manufacturing the TFT contains many elements harmful to the silicon semiconductor, it is necessary to avoid such defects as much as possible. Also,
It was also difficult to finish the side walls uniformly. This is reactive ion etching (
This is because, during plasma dry etching such as RIE, unlike the silicon substrate used in a semiconductor integrated circuit, the substrate surface is insulative, and thus it is difficult to delicately control the plasma.

Since the drain of the high-resistance impurity region has high resistance, it is necessary to make its width as narrow as possible, but it is difficult to mass-produce due to the above-mentioned variation, and this self-aligned (ie, without using a photolithography method) The challenge was how to make the process easy to control. Further, in the conventional method, doping is required at least twice, but reducing the number of doping is also a problem to be solved.

The present invention solves the above-described problems, further simplifies the process, and forms a high-resistance impurity region, and a high-resistance impurity region (high-resistance drain, H
RD). Here, the term “high resistance drain (HRD)” refers to a drain whose impurity concentration is relatively high in addition to a drain whose resistance is increased by low impurity concentration, but carbon, oxygen, nitrogen or the like is added to add impurities. This is because it also includes a drain that hinders activation and consequently has a high resistance.

In forming the high resistance region, the present invention is characterized in that an oxide layer formed by means such as anodic oxidation of the gate electrode is positively used. In particular, the thickness of the anodic oxide can be precisely controlled, and the thickness of the anodic oxide is wide from a thin one having a thickness of 100 nm or less to a thick one having a thickness of 500 nm or more. It is preferable as a material to replace the side wall by anisotropic etching.

In particular, a so-called barrier type anodic oxide is not etched unless it is a hydrofluoric acid-based etchant, whereas a porous anodic oxide is selectively etched by an etchant such as phosphoric acid. For this reason, it can be processed without giving any damage (damage) to other materials constituting the TFT, for example, silicon and silicon oxide. In addition, both the barrier type and the porous type are extremely difficult to be etched by dry etching. In particular, the etching ratio with silicon oxide is also characterized by a sufficiently high selectivity.
The present invention is characterized in that a TFT is manufactured by the following manufacturing process. By adopting this process, the HRD can be configured more reliably and the mass productivity can be improved.

FIG. 1 shows the basic steps of the present invention. First, the base insulating film 102 is formed over the substrate 101, and the active layer 103 is further formed of a crystalline semiconductor (in the present invention, a semiconductor in which crystals are mixed, such as single crystal, polycrystal, and semi-amorphous, is called a crystalline semiconductor. ).
Then, an insulating film 104 is formed from a material such as silicon oxide so as to cover it, and a film is formed from a material that can be anodized. As the material of this film, anodizable aluminum, tantalum, titanium, silicon and the like are preferable. In the present invention, a gate electrode having a single layer structure using these materials alone may be used, or a gate electrode having a multilayer structure in which two or more of these materials are stacked may be used. For example, a two-layer structure in which titanium silicide is stacked on aluminum or a two-layer structure in which aluminum is stacked on titanium nitride. The practitioner may determine the thickness of each layer according to the required device characteristics.

Further, a film serving as a mask in anodic oxidation is formed so as to cover the film, and both are patterned and etched simultaneously to form a gate electrode 105 and a mask film 106 thereon. As a material of the mask film, a photoresist used in a normal photolithography process, a photosensitive polyimide, or a material that can be etched with a normal polyimide may be used. (Fig. 1 (A))

Next, a porous anodic oxide 107 is formed on the side surface of the gate electrode by applying a voltage to the gate electrode 105 in an electrolytic solution. This anodizing step is performed using 3 to 20% of an acidic aqueous solution such as citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like. The hydrogen ion concentration pH of the solution is desirably less than 2. The optimum pH depends on the type of the electrolytic solution, but in the case of oxalic acid, it is 0.9 to 1.0. In this case, a thick anodic oxide of 0.5 μm or more can be formed at a low voltage of about 10 to 30V. (Fig. 1 (B))

Then, the insulating film 104 is etched by a dry etching method, a wet etching method, or the like. The etching depth is arbitrary, and etching may be performed until the underlying active layer is exposed, or may be stopped during the etching. However, from the viewpoint of mass productivity, yield, and uniformity, it is desirable to perform etching up to the active layer. In this case, the anodic oxide 107 is used.
The insulating film having the original thickness is left in the insulating film (gate insulating film) on the lower side of the region covered with the gate electrode 105. In the case where the gate electrode is mainly composed of aluminum, tantalum, and titanium, while the insulating film 104 is composed mainly of silicon oxide, when a dry etching method is used, fluorine-based (for example, NF ₃ , SF ₆ ) When the dry etching is performed using this etching gas, the insulating film 104 made of silicon oxide is quickly etched, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently low, so the insulating film 104 is selectively selected. Can be etched.

In wet etching, a hydrofluoric acid-based etchant such as 1/100 hydrofluoric acid may be used. In this case as well, the insulating film 104 made of silicon oxide is etched quickly, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently small, so that the insulating film 104 can be selectively etched. (Figure 1 (C))

Thereafter, the anodic oxide 107 is removed. As the etchant, a phosphoric acid solution, for example, a mixed acid of phosphoric acid, acetic acid, and nitric acid is preferable. However, for example, when the gate electrode is aluminum, if a phosphoric acid-based etchant is used, the gate electrode is also etched at the same time. Therefore, in the present invention, by applying a voltage in an ethylene glycol solution containing 3 to 10% tartaric acid, boric acid and nitric acid in the gate electrode in the previous step, the side surface of the gate electrode and A barrier-type anodic oxide 108 is preferably provided on the upper surface. In this anodic oxidation step, the pH of the electrolytic solution is 2 or more, preferably 3 or more, more preferably 6.9.
It is good to set to -7.1. In order to obtain such a solution, it is preferable to neutralize with an alkaline solution such as ammonia. The thickness of the anodic oxide thus obtained is determined by the magnitude of the voltage applied between the gate electrode 105 and the opposing electrode.

It should be noted that, despite the fact that barrier type anodic oxidation is a later process, the barrier type anodic oxide 108 is not formed on the outside of the porous anodic oxide. It is formed between the porous anodic oxide 107 and the gate electrode 105. In the phosphoric acid-based etchant, the etching rate of the porous anodic oxide is 10 times or more that of the barrier type anodic oxide. Therefore, the barrier type anodic oxide 108 is
Since the phosphoric acid-based etchant is not substantially etched, the inner gate electrode can be protected. (Fig. 1 (D), (E))

Through the above steps, a structure in which a part of the insulating film 104 (hereinafter referred to as a gate insulating film) is selectively left under the gate electrode can be obtained. Since the gate insulating film 104 ′ originally existed under the porous anodic oxide 107, not only the gate electrode 105 and the barrier anodic oxide 108 but also the barrier anodic oxide 10.
It exists in the position which is only the distance of y from 8 and the width | variety y is determined by the self-alignment. In other words, a region where the gate insulating film 104 ′ exists and a region where the gate insulating film 104 ′ does not exist are formed in a self-aligned manner outside the channel formation region under the gate electrode in the active layer 103.

When ions of N-type or P-type impurities accelerated in this structure are implanted into the active layer, many ions are implanted in a region where the insulating film 104 does not exist (or is thin), and (relatively) high-concentration impurities. Regions (low resistance impurity regions) 110 and 113 are formed. On the other hand, in the region where the gate insulating film 104 ′ is present, ions are implanted into the gate insulating film, and only ions that have passed through the gate insulating film are implanted into the semiconductor. Low concentration impurity regions (high resistance impurity regions) 111 and 112 are formed. Low concentration impurity region 1
11 and 112 and the impurity concentration difference between the high-concentration impurity regions 110 and 113 are as follows.
Although it varies depending on the thickness of 4, etc., the former is usually smaller by 0.5 to 3 digits. Further, impurities are not substantially implanted into the region under the gate electrode, and the intrinsic or substantially intrinsic state is maintained, that is, a channel formation region. After the impurity implantation, the impurity may be activated by irradiating a laser or a strong light equivalent to the laser, but it is needless to say that this step is substantially sufficient once. (Figure 1 (E))

As described above, the present invention is characterized in that the width of the high resistance impurity region is controlled in a self-aligned manner by the thickness y of the anodic oxide 107. Further, the end 10 of the gate insulating film 104 ′
9 and the end portion 117 of the high resistance region (HRD) 112 can be substantially matched. In the conventional method shown in FIG. 6, it is very difficult to control the width of the side wall that plays such a role. In the present invention, the width of the anodic oxide 107 is determined by the anodic oxidation current (charge amount). Therefore, very delicate control is possible.

Further, as is clear from the above process, the low resistance region and the high resistance region can be formed even if the impurity doping process is substantially performed once, and the subsequent activation process is performed once. Processing is enough. Thus, in the present invention, mass productivity can be enhanced by reducing the steps of doping and activation. Conventionally, HRD has a large resistance, so that it is difficult to make ohmic contact with the electrode, and the drain voltage is lowered due to this resistance. However, on the other hand, the presence of the HRD has the advantage that generation of hot carriers can be suppressed and high reliability can be obtained. The present invention solves this contradictory problem all at once, and can obtain an ohmic contact with a 0.1 to 1 μm wide HRD formed in a self-aligned manner and the source / drain electrodes.

In the present invention, the positional relationship between the end portion of the gate electrode and the impurity region can be arbitrarily changed by appropriately utilizing the thickness of the anodic oxide 108 in FIG. An example of this is shown in FIG.
For example, in a method in which ions are implanted without being substantially mass-separated, such as an ion doping method (also referred to as plasma doping), since the angle of entry of ions varies, there is also considerable lateral spread of impurities, That is, the spread in the lateral direction of the degree of ion addition is expected. In the following example, the thickness of the active layer 404 is 80 nm.

Therefore, as shown in FIG. 4A, the anodic oxide 4 is formed outside the metal gate electrode 401.
02 (corresponding to FIGS. 1 and 108) (for example, 80 nm) is almost the same as that of the active layer 404, the end portion 405 of the gate electrode 401 and the end portion 406 of the high-resistance impurity region 407 are almost the same.
Will not overlap and will not be separated. When the thickness of the anodic oxide 402 is larger than, for example, 300 nm and the thickness of the active layer 80 nm as shown in FIG. 4B, the end 405 of the gate electrode and the end 406 of the high resistance impurity region are separated from each other. An offset state is entered. Conversely, FIG. 4 (C
If the thickness of the anodic oxide 402 is reduced as in (), the gate electrode and the high resistance impurity region overlap each other. This overlap becomes maximum when no anodic oxide exists around the gate electrode 401 as shown in FIG.

In general, in the offset state, the reverse leakage current is reduced and the on / off ratio is improved. For example, a leakage current such as a TFT (pixel TFT) used for controlling a pixel of an active matrix liquid crystal display is used. Suitable for applications that require a small amount of However, it also has a disadvantage that the hot carriers generated at the end of the HRD are deteriorated by being trapped by the anodic oxide.

In the overlap state, the deterioration due to trapping of hot carriers as described above is reduced, and the on-current is increased, but there is a disadvantage that the leakage current is increased. For this reason, it is suitable for applications requiring a large current driving capability, for example, a TFT (driver TFT) used in a peripheral circuit of a monolithic active matrix. T actually used
Whether the FT is any of those shown in FIGS. 4A to 4D may be determined depending on the use of the TFT.

According to the present invention, a high resistance impurity region (HRD) can be formed by an activation process such as one doping, one laser annealing, and RTA. This shortening of the process increases mass productivity and is effective in reducing the amount of investment in the TFT production line. Further, in the present invention, the width of the HRD is formed with extremely high accuracy, so that the yield and uniformity are excellent.
FT is obtained.

In the present invention, in order to improve the characteristics, more doping, laser annealing, and RTA may be performed, and the number of doping, laser annealing, and RTA are not necessarily limited to one. .
It goes without saying that the TFT of the present invention is similarly formed when a three-dimensional integrated circuit is formed on a substrate on which a semiconductor integrated circuit is formed, or when it is formed on glass or an organic resin. Is formed on an insulating surface in any case. In particular, the effect of the present invention is remarkable for an electro-optical device such as a monolithic active matrix circuit having peripheral circuits on the same substrate.

In the present invention, in addition to ion implantation or ion doping of P or N type impurities, carbon, oxygen, and nitrogen may be added simultaneously. As a result, the reverse leakage current is reduced and the breakdown voltage is also improved. For example, it is effective when used as a pixel TFT of an active matrix circuit. In this case, the thickness of the anodic oxide layer of TFT 3 in FIG.
It can be the same thickness as T2.

FIG. 6 shows a method for manufacturing a TFT according to Example 1; FIG. 6 shows a method for manufacturing a TFT according to Example 2; FIG. 9 shows a method for manufacturing a TFT according to Example 3; The figure shown about the relationship between offset and overlap in this invention. FIG. 6 is a diagram showing an example of an integrated circuit of TFTs obtained in Examples 1 and 2. 10A and 10B illustrate a method for manufacturing a TFT according to a conventional method.

  Hereinafter, embodiments of the present invention will be described based on examples.

FIG. 1 shows this embodiment. First, a substrate oxide film 102 having a thickness of 100 to 300 is formed on a substrate (Corning 7059, 300 mm × 400 mm or 100 mm × 100 mm) 101.
A silicon oxide film of nm was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further increase mass productivity, a film obtained by decomposing and depositing TEOS by plasma CVD may be used.

Thereafter, an amorphous silicon film is formed in a thickness of 30 to 500 nm by plasma CVD or LPCVD.
Preferably, 50 to 100 nm was deposited, and this was left to stand in a reducing atmosphere at 550 to 600 ° C. for 24 hours for crystallization. This step may be performed by laser irradiation. Then, the island film 103 was formed by patterning the silicon film crystallized in this manner.
Further, a silicon oxide film 104 having a thickness of 70 to 150 nm was formed thereon by sputtering.

Thereafter, aluminum having a thickness of 100 nm to 3 μm (1 wt% Si, or 0.1 to
A film containing 0.3 wt% Sc (scandium) was formed by electron beam evaporation or sputtering. And a photoresist (for example, OFPR800 / 3, manufactured by Tokyo Ohka Kogyo Co., Ltd.)
0 cp) was formed by spin coating. If an aluminum oxide film having a thickness of 10 to 100 nm is formed on the surface by anodic oxidation before the formation of the photoresist, the adhesion with the photoresist is good and current leakage from the photoresist is suppressed. Thus, it was effective in forming the porous anodic oxide only on the side surface in the subsequent anodic oxidation step. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a gate electrode 105 mask film 106. (Fig. 1 (A))

Furthermore, this is anodized through an electric current in an electrolytic solution, and a thickness of 300 to 600 nm, for example,
An anodic oxide 107 having a thickness of 500 nm was formed. Anodization is performed using 3 to 20% of an acidic aqueous solution such as citric acid or succinic acid, phosphoric acid, chromic acid, sulfuric acid, etc., and a constant current of 10 to 30 V may be applied to the gate electrode. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.) having a pH of 0.9 to 1.0, and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (Fig. 1 (B))

Thereafter, the silicon oxide film 104 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selection ratio between silicon and silicon oxide. For example, if CF ₄ is used as an etching gas, the anodic oxide is not etched and only the silicon oxide film 104 is etched. In addition, the silicon oxide film 10 under the porous anodic oxide 107
4 'remained unetched. (Figure 1 (C))

Next, an electric current was applied to the gate electrode again in the electrolytic solution. This time, an ethylene glycol ammonia solution having a pH of 6.9 to 7.1 containing 3 to 10% tartaric acid, boric acid and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature of around 10 ° C. For this reason, the barrier type anodic oxide 108 was formed on the upper surface and the side surface of the gate electrode. The thickness of the anodic oxide 108 was proportional to the applied voltage, and an anodic oxide of 200 nm was formed at an applied voltage of 150V. The thickness of the anodic oxide 108 is the required offset as shown in FIG.
Although it was determined by the size of the overlap, a high voltage of 250 V or higher is necessary to obtain an anodic oxide with a thickness of 300 nm or more, which adversely affects the characteristics of the TFT.
The following thickness is preferred. In this embodiment, the voltage is raised to 80 to 150 V, and the voltage is selected according to the required thickness of the anodic oxide film 108. (Figure 1 (D))

Thereafter, the anodic oxide 107 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 107 is etched, and the etching rate is about 60 nm /
Minutes. The underlying gate insulating film 104 ′ remains as it is. Then, by ion doping, impurities are implanted into the active layer 103 of the TFT in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as a mask, and a low-resistance impurity region ( Source / drain regions) 110, 113, high resistance impurity regions 111, 11
2 was formed. Since phosphine (PH ₃ ) was used as the doping gas, it became an N-type impurity region. In order to form a P-type impurity region, diborane (B ₂ H ₆ ) may be used as a doping gas. The dose amount was 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² , and the acceleration energy was 10 to 30 keV. Thereafter, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to activate impurity ions introduced into the active layer.

According to the results of SIMS (secondary ion mass spectrometry), the impurity concentration of the regions 110 and 113 is 1 × 10 ²⁰ to 2 × 10 ²¹ cm ⁻³ , and the regions 111 and 112 are 1 × 10 ¹⁷ to 2 × 10 ¹⁸ cm.
^-3 . In dose conversion, the former is 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² , and the latter is 2 × 10.
^{13 to} 5 × 10 ¹⁴ cm ⁻² . This difference is caused by the presence / absence of the gate insulating film 104 ′. In general, the impurity concentration in the low-resistance irregular region 鵜 region is 0.5 to 3 orders of magnitude higher than that in the high-resistance impurity region. . (Figure 1 (E))

Finally, a silicon oxide film having a thickness of 300 n is formed on the entire surface as an interlayer insulator 114 by a CVD method.
m formed. Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 115 and 116 were formed. Further, hydrogen annealing was performed at 200 to 400 ° C. Thus, the TFT was completed. (Fig. 1 (F))

FIG. 5A shows an example in which a plurality of TFTs are formed over one substrate using the method shown in FIG. In this example, three TFTs 1 to 3 were formed. TFTs 1 and 2 are used as driver TFTs, and oxides 501, 5 corresponding to the anodic oxide 108 in FIG.
The thickness of 02 was 20 to 100 nm, for example, 50 nm, so that the gate electrode and the high resistance region (HRD) slightly overlapped. The figure shows an example in which the drain of TFT1 and the source of TFT2 are connected to each other, the source of TFT1 is grounded, and the drain of TFT2 is connected to a power source so as to be a CMOS inverter. There are various other peripheral circuits, but such a CMOS circuit may be used in accordance with each specification.

On the other hand, the TFT 3 is used as a pixel TFT, and the anodic oxide 503 is changed to 200.
The thickness was increased to nm, and an offset state (corresponding to FIG. 4B) was set to suppress leakage current. T
One of the source / drain electrodes of the FT 3 is connected to the ITO pixel electrode 501. In order to change the thickness of the anodic oxide in this way, it is only necessary to separate the voltage of the gate electrode of each TFT so that it can be controlled independently. TFT1 and TFT3 are N channel type TF.
T and TFT2 are P-channel TFTs.

FIG. 2 shows this embodiment. First, a substrate having an insulating surface (for example, Corning 7059) 2
01, the base oxide film 202, the island-like silicon semiconductor region (for example, crystalline silicon semiconductor) 203, the gate insulating film 204, the aluminum film (thickness) using the steps (A) to (C) of the first embodiment. 200 nm to 1 μm), and a porous anodic oxide (thickness 300 nm to 1 μm, for example, 500 nm) 206 was formed on the side surface of the gate electrode 205 and the gate electrode. (Fig. 2 (A))
In the same manner as in Example 1, a barrier type anodic oxide 207 having a thickness of 100 to 250 nm was formed. (Fig. 2 (B))

Further, using this barrier type anodic oxide film 207 as a mask, the porous anodic oxide film 206 was removed by etching. Thereafter, impurities are implanted by ion doping using the gate electrode portions (205, 207) and the gate insulating film 204 as a mask, and the low resistance impurity region 20
8, 211 and high resistance impurity regions 209 and 210 were formed. Dose amount is 1-5 × 10 ¹⁴ c
m ⁻² and the acceleration voltage were 30 to 90 kV. Phosphorus was used as the impurity. (Fig. 2 (C))

Furthermore, a suitable metal on the entire surface, such as titanium, nickel, molybdenum, tungsten,
A film of platinum, palladium, or the like, for example, a titanium film 212 having a thickness of 5 to 50 nm was formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 212 was formed in close contact with the low resistance impurity regions 208 and 211. (Fig. 2 (D))

Then, KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is irradiated to activate the doped impurities and react the metal film (here, titanium) with silicon in the active layer to form metal silicide (here, silicide). Titanium) regions 213 and 214 were formed.
The energy density of the laser is 200 to 400 mJ / cm ² , preferably 250 to 300 m.
J / cm ² was appropriate. Further, when the substrate was heated to 200 to 500 ° C. during laser irradiation, it was possible to suppress the peeling of the titanium film.

In this embodiment, the excimer laser is used as described above, but it goes without saying that other lasers may be used. However, when using a laser, a pulsed laser is preferable. Since the continuous wave laser has a long irradiation time, there is a danger that the irradiated object is peeled off due to the expansion of the irradiated object due to the heat.

Regarding pulse lasers, infrared lasers such as Nd: YAG lasers (preferably Q-switched pulse oscillation) and visible light such as second harmonics thereof, KrF, XeCl, ArF
Various ultraviolet lasers using excimers such as the above can be used, but when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Moreover, you may irradiate a laser beam from the board | substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

The annealing may be performed by lamp annealing by irradiation with visible light or near infrared light. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several tens of seconds at 1000 ° C. so that the surface to be irradiated has a temperature of about 600 to 1000 ° C. Annealing with near-infrared rays (for example, 1.2 μm infrared rays) selectively absorbs near-infrared rays into the silicon semiconductor, does not heat the glass substrate so much, and shortens the irradiation time once, thereby heating the glass substrate. This is extremely useful.

Thereafter, the Ti film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film (for example, the titanium film existing on the gate insulating film 204 and the anodic oxide film 207) other than the portion in contact with the exposed active layer remains in the metal state as it is, but can be removed by this etching. On the other hand, titanium silicides 213 and 214, which are metal silicides, are not etched and can remain. (Figure 2 (E))

Finally, as shown in FIG. 2 (F), a silicon oxide film having a thickness of 200 nm to 1 μm, for example, 300 nm is formed as an interlayer insulator 217 on the entire surface by CVD, and contact holes are formed in the source / drain of the TFT. 200n aluminum wiring / electrodes 218, 219
The film was formed to a thickness of m to 1 μm, for example, 500 nm. In this embodiment, the portion where the aluminum wiring contacts is titanium silicide, and the stability of the interface with aluminum is better than that of silicon, so that a highly reliable contact was obtained. Further, for example, when titanium nitride is formed as a barrier metal between the aluminum electrodes 218 and 219 and the silicide regions 213 and 214, the reliability can be further improved. In this example, the sheet resistance in the silicide region was 10 to 50Ω / □. On the other hand, the high resistance impurity regions 209 and 210 are 10 to 100 kΩ / □, and as a result, a TFT having good frequency characteristics and low hot carrier deterioration even at a high drain voltage can be manufactured.

In this example, the low resistance impurity region 211 and the metal silicide region could be roughly matched. In particular, the end 215 of the gate insulating film 204, the boundary 216 between the high resistance impurity region 210 and the low resistance impurity region 211 are approximately matched, and at the same time, the end 215 and the end of the metal silicide region 214 are approximately aligned. It will be apparent that the low resistance impurity regions in FIGS. 4A to 4D may be replaced with metal silicide regions.

FIG. 5B shows an example in which a plurality of TFTs are formed on one substrate using the method shown in FIG. In this example, three TFTs 1 to 3 were formed. TFTs 1 and 2 are configured as CMOSs as driver TFTs, here used as an inverter configuration.
The thicknesses of the oxides 505 and 506 corresponding to the anodic oxide 207 were made as thin as 20 to 100 nm, for example 50 nm, so that they slightly overlapped. On the other hand, the TFT 3 is used as a pixel TFT, and the anodic oxide 503 is made as thick as 200 nm to be in an offset state, thereby suppressing a leakage current. One of the source / drain electrodes of TFT3 is IT
The pixel electrode 502 is connected to the O pixel electrode 502. In order to change the thickness of the anodic oxide in this way, it is only necessary to separate the voltage of the gate electrode of each TFT so that it can be controlled independently. In addition,
TFT1 and TFT3 are N-channel TFTs, and TFT2 is a P-channel TFT.

In this embodiment, the titanium film forming step is arranged after the ion doping step, but this order may be reversed. In this case, since the titanium film covers the entire surface at the time of ion irradiation, the effect is great in preventing abnormal charging (charge-up) which has been a problem in the insulating substrate. Alternatively, after ion doping, annealing may be performed with a laser or the like, a titanium film may be formed, and titanium silicide may be formed by irradiation with a laser or the like or thermal annealing.

FIG. 3 shows this embodiment. First, on the substrate (Corning 7059) 301, (A
) To (C), the gate electrode 305 and the gate electrode made of the base oxide film 302, the island-like crystalline semiconductor region, for example, the silicon semiconductor region 303, the gate insulating film 304, the aluminum film (thickness 200 nm to 1 μm). A porous anodic oxide (thickness 600 nm) 306 was formed on the side surface of the substrate. (Fig. 3 (A))
In the same manner as in Example 1, a barrier type anodic oxide 307 having a thickness of 100 to 250 nm was formed. (Fig. 3 (B))

Further, the porous anodic oxide 306 was selectively etched to expose a part of the gate insulating film 304. Thereafter, an appropriate metal, for example, a titanium film 3 having a thickness of 5 to 50 nm is formed on the entire surface.
08 was formed on the entire surface by sputtering. (Figure 3 (C))
Then, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to react titanium and silicon of the active layer, thereby forming titanium silicide regions 309 and 310. The energy density of the laser is 200 to 400 mJ / cm ² , preferably 250 to 300 mJ.
/ Cm ² was appropriate. Further, when the substrate was heated to 200 to 500 ° C. during laser irradiation, it was possible to suppress the peeling of the titanium film. This step may be performed by lamp annealing by irradiation with visible light or near infrared light.

Thereafter, the Ti film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film other than the part in contact with the exposed active layer (for example, the titanium film existing on the gate insulating film 304 or the anodic oxide film 307) remains in the metal state as it is, but can be removed by this etching. On the other hand, the titanium silicides 309 and 310 are not etched and can remain. (Fig. 3 (D))

Thereafter, impurity implantation is performed by ion doping using the gate electrode portion and the gate insulating film 304 as a mask, and low resistance impurity regions (≈titanium silicide regions) 311, 314,
High resistance impurity regions 312 and 313 were formed. The dose was 1-5 × 10 ¹⁴ cm ⁻² and the acceleration voltage was 30-90 kV. Phosphorus was used as the impurity. (Figure 3 (E))

Then, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed again to activate the doped impurities. This step may be performed by lamp annealing by irradiation with visible light or near infrared light. Finally, the gate electrode (
The gate insulating film 304 was etched using 305 and 307) as a mask. This was done to avoid instability due to impurities doped in the gate insulating film 304. As a result, the gate insulating film 304 ′ remained only under the gate electrode portion.

Then, as shown in FIG. 3F, a silicon oxide film having a thickness of 600 nm is formed as an interlayer insulator 315 over the entire surface by CVD, a contact hole is formed in the source / drain of the TFT, and an aluminum wiring / electrode 316 is formed. 317 was formed.
The TFT was completed through the above steps.

101 Insulating substrate 102 Base oxide film (silicon oxide)
103 Active layer (crystalline silicon)
104 Insulating film (silicon oxide)
104 'Gate insulation film 105 Gate electrode (aluminum)
106 Mask film (photoresist)
107 Anodic oxide (porous aluminum oxide)
108 Anodic oxide (barrier type aluminum oxide)
109 End of gate insulating film 110, 113 Low resistance impurity region 111, 112 High resistance impurity region (HRD)
114 Interlayer insulating film (silicon oxide)
115,116 Metal wiring and electrodes (aluminum)
117 Boundary between low resistance impurity region and high resistance impurity region

Claims (3)

Having an insulated gate type transistor on a silicon oxide film on a silicon wafer;
The insulated gate transistor is
Has an island-like silicon film, a gate insulating film formed on the inner side than the end portion of the island-like silicon film, and a gate electrode formed on said gate insulating film,
The island-shaped silicon film has a channel formation region, a pair of high resistance impurity regions provided so as to sandwich the channel formation region, and the channel formation region interposed between the pair of high resistance impurity regions. A pair of metal silicide regions provided,
An oxide layer obtained by oxidizing the gate electrode is provided on at least a side surface of the gate electrode ,
The pair of high resistance impurity regions are provided so as to overlap the oxide layer and to overlap a part of the gate electrode,
The pair of metal silicide regions are provided so as not to overlap the gate insulating film;
Carbon, oxygen, and nitrogen are added to the pair of metal silicide regions and the pair of high-resistance impurity regions together with N-type or P-type impurities, and the pair of high-resistance impurity regions is more than the pair of metal silicide regions. A semiconductor device characterized in that the impurity concentration is low. Having an insulated gate type transistor on a silicon oxide film on a silicon wafer;
The insulated gate transistor is
Has an island-like silicon film, a gate insulating film formed on the inner side than the end portion of the island-like silicon film, and a gate electrode formed on said gate insulating film,
The island-shaped silicon film has a channel formation region, a pair of high resistance impurity regions provided so as to sandwich the channel formation region, and the channel formation region interposed between the pair of high resistance impurity regions. A pair of metal silicide regions provided;
An oxide layer obtained by oxidizing the gate electrode is provided on at least a side surface of the gate electrode ,
The pair of high resistance impurity regions are provided so as to overlap with the oxide layer and not to overlap with part of the gate electrode,
The pair of metal silicide regions are provided so as not to overlap the gate insulating film;
Carbon, oxygen, and nitrogen are added to the pair of metal silicide regions and the pair of high-resistance impurity regions together with N-type or P-type impurities, and the pair of high-resistance impurity regions is more than the pair of metal silicide regions. A semiconductor device characterized in that the impurity concentration is low. In claim 1 or 2 ,
The pair of metal silicide regions is formed of a silicide of titanium, nickel, molybdenum, tungsten, platinum, or palladium.

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