JP2003023014A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a pixel part and a peripheral circuit for driving the pixel part are integrated on the same substrate. SOLUTION: In an N-channel type thin-film transistor in the peripheral circuit, a gate electrode and a high resistance impurity region are overlapped to suppress the deterioration due to a hot carrier and increase an ON-state current. In a thin-film transistor in the pixel part, the high-resistance impurity region and the gate electrode do not overlap to suppress a leak current and to improve the ratio between the ON-state current and OFF-state current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate transistor (TFT) formed on an insulating surface such as an insulating material such as glass, or a material such as a silicon wafer on which an insulating coating film such as silicon oxide is formed, and a TFT thereof. It relates to a manufacturing method.
The present invention particularly relates to a TFT formed on a glass substrate having a glass transition point (also called strain temperature or strain point) of 750 ° C. or lower.
Is effective for. The semiconductor device according to the present invention is used in an active matrix such as a liquid crystal display, a drive circuit such as an image sensor, or a three-dimensional integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a TF has been used for the purpose of driving an active matrix type liquid crystal display device or an image sensor.
It is widely known to form a T (thin film transistor). In particular, recently, because of the need for high-speed operation, a crystalline silicon TFT having a higher electric field mobility has been developed in place of the amorphous silicon TFT using amorphous silicon in the active layer. However, when higher characteristics and higher durability are required, a high resistance impurity region (high resistance drain (HRD) or low concentration drain (LDD)) as used in semiconductor integrated circuit technology is provided. Was needed. However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular,
Since the device is formed on the insulating surface and the reactive ion anisotropic etching cannot be sufficiently performed, there is a large restriction that a fine pattern cannot be formed.

FIG. 6 shows an HRD that has been used up to now.
6A to 6D are cross-sectional views of a typical process for manufacturing the. First, a base film 602 is formed over a substrate 601, and an active layer is formed using crystalline silicon 603. Then, an insulating coating 604 is formed on the active layer with a material such as silicon oxide. (Fig. 6 (A))

Next, a gate electrode 605 is formed of polycrystalline silicon (doped with impurities such as phosphorus), tantalum, titanium, aluminum or the like. Further, by using this gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by means such as ion doping, and a self-aligned high-resistance impurity region (HRD) with a small doping amount is introduced.
606 and 607 are formed in the active layer 603. The active layer region below the gate electrode into which the impurities have not been introduced becomes a channel formation region. Then, the doped impurities are activated by a heat source such as a laser or a flash lamp. (Fig. 6 (B))

Next, an insulating film 608 of silicon oxide or the like is formed by means of plasma CVD, APCVD or the like (see FIG. 6).
(C)) and anisotropically etch it to form a sidewall 609 adjacent to the side surface of the gate electrode. (FIG. 6D) Then, again, the impurity element is introduced by means such as ion doping, and the gate electrode 60 is formed.
5 and the side wall 609 as a mask, impurity regions (low resistance impurity regions, source / drain regions) 610 and 611 having a sufficiently high concentration are formed in the active layer 603 in a self-aligning manner. Then, the doped impurities are activated by a heat source such as a laser or a flash lamp. (Fig. 6 (E))

Finally, an interlayer insulator 612 is formed, a contact hole is formed in the source / drain region through the interlayer insulator, and a wiring / electrode 613 connected to the source / drain is formed by a metal material such as aluminum.
614 is formed. (Fig. 6 (F))

[0007]

The above method follows the LDD manufacturing process in the conventional semiconductor integrated circuit as it is, and it is difficult to directly apply it to the TFT manufacturing process on the glass substrate. Alternatively, there are processes that are not preferable in terms of productivity.

First, the activation of impurities by irradiation with a laser or the like is required twice. This reduces productivity. In the conventional semiconductor integrated circuit, activation of the impurity element has been performed by thermal annealing. for that reason,
The activation of impurities was performed collectively after the introduction of all impurities was completed.

However, especially on a TFT on a glass substrate
In this case, it is difficult to perform thermal annealing due to the temperature limitation of the substrate, and it is unavoidable to rely on laser annealing or flash lamp annealing (RTA or RTP). However, in these methods, the surface to be irradiated is selectively annealed, so that, for example, the portion below the sidewall 609 is not annealed. Therefore, annealing is required every time impurity doping is performed.

The second problem is the difficulty of forming the side wall. The thickness of the insulating film 608 is 0.5 to 2 μm. Usually, the thickness of the base film 602 provided on the substrate is 1000 to 3000Å
Therefore, in this etching process, the base film is often mistakenly etched to expose the substrate, and the yield is lowered. Since the substrate used for manufacturing the TFT contains many elements harmful to the silicon semiconductor, it is necessary to avoid such defects as much as possible. It was also difficult to finish the width of the side wall uniformly. This is reactive ion etching (RIE)
This is because, in plasma dry etching such as the above, unlike the silicon substrate used in the semiconductor integrated circuit, it is difficult to finely control the plasma because the surface of the substrate is insulative.

Since the drain of the high resistance impurity region has a high resistance, it is necessary to make its width as narrow as possible, but it is difficult to mass-produce it due to the above variations, and this self-alignment (that is, the photolithography method is used). The challenge was how to make the process easier to control). Further, in the conventional method, doping was required at least twice, but reducing the number of times of doping was also a problem to be solved.

The present invention solves the above problems and further simplifies the process to form a high resistance impurity region, and a high resistance impurity region (high resistance drain, HRD) thus formed. With respect to the TFT.
Here, the term “high resistance drain (HRD)” means that the impurity concentration is relatively high in addition to the drain having a low impurity concentration and a high resistance, but carbon, oxygen, nitrogen or the like is added to remove the impurities. It also includes a drain which has a high resistance as a result of hindering activation.

[0013]

In forming a high resistance region, the present invention is characterized by positively using an oxide layer formed by means such as anodic oxidation of a gate electrode. In particular, the thickness of anodic oxide can be precisely controlled, and the thickness is as low as 1000 Å or less.
Since it has a feature that it can be formed uniformly over a wide range up to a thickness of 000 Å or more, it is preferable as a material replacing the side wall by conventional anisotropic etching.

In particular, the so-called barrier type anodic oxide is not etched unless it is a hydrofluoric acid type etchant, whereas the porous type anodic oxide is selectively etched by an etchant such as phosphoric acid. Therefore, the TFT
It is characterized in that it can be processed without giving any damage (damage) to other materials constituting, for example, silicon and silicon oxide. Further, in both the barrier type and the porous type, anodic oxide is extremely difficult to be etched by dry etching. In particular, the feature is that the selection ratio is sufficiently large in etching with silicon oxide. The present invention is characterized in that a TFT is manufactured by the following manufacturing process. By adopting this process, the HRD can be more surely configured and mass productivity can be improved.

[0015]

DETAILED DESCRIPTION OF THE INVENTION FIG. 1 illustrates the basic steps of the present invention. First, the base insulating film 102 is formed on the substrate 101, and the active layer 103 is further made of a crystalline semiconductor (in the present invention, a semiconductor in which crystals are mixed as much as possible, such as single crystal, polycrystal, or semi-amorphous) is called a crystalline semiconductor. ). Then, an insulating film 104 is formed so as to cover the insulating film 104 with a material such as silicon oxide, and a film is formed with a material capable of anodizing. As the material of this coating, aluminum, tantalum, titanium, silicon or the like which can be anodized is preferable. In the present invention, a gate electrode having a single layer structure using these materials alone may be used, or a gate electrode having a multilayer structure in which two or more layers of these materials are stacked may be used. For example, it has a two-layer structure in which titanium silicide is overlaid on aluminum and a two-layer structure in which aluminum is overlaid on titanium nitride.
The thickness of each layer may be determined by a practitioner according to the required device characteristics.

Further, a film serving as a mask in anodic oxidation is formed so as to cover the film, and both are simultaneously patterned and etched to form a gate electrode 105 and a mask film 106 thereon. As a material for the mask film, a photoresist used in a normal photolithography process, a photosensitive polyimide, or a material that can be etched with a normal polyimide may be used.
(Fig. 1 (A))

Next, a current is applied to the gate electrode 105 in an electrolytic solution to form a porous anodic oxide 107 on the side surface of the gate electrode. This anodic oxidation process is 3
It is carried out using an acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc. of -20%. The hydrogen ion concentration pH of the solution is preferably less than 2. The optimum pH depends on the type of electrolytic solution, but is 0.9 to 1.0 for oxalic acid. In this case, 10-30
It is possible to form a thick anodic oxide of 0.5 μm or more at a voltage as low as V. (Fig. 1 (B))

Then, the insulating film 104 is etched by a dry etching method, a wet etching method or the like.
This etching depth is arbitrary, and etching may be performed until the underlying active layer is exposed, or may be stopped midway. However, from the viewpoint of mass productivity, yield, and uniformity, it is desirable to etch up to the active layer. At this time, the anodic oxide 107 and the gate electrode 10
The insulating film having the original thickness is left on the insulating film (gate insulating film) below the region covered with 5. In the case where the gate electrode contains aluminum, tantalum, and titanium as the main components, while the insulating film 104 contains silicon oxide as the main component, when a dry etching method is used, a fluorine-based material (eg, NF ₃ , SF ₆ ) is used. When the dry etching is performed using the etching gas described above, the insulating film 104 made of silicon oxide is quickly etched. However, since the etching rates of aluminum oxide, tantalum oxide, and titanium oxide are sufficiently small, the insulating film 104 is selectively etched. Can be etched.

In wet etching, 1
A hydrofluoric acid-based etchant such as / 100 hydrofluoric acid may be used. In this case as well, the insulating film 104 made of silicon oxide is etched quickly, but since the etching rates of aluminum oxide, tantalum oxide, and titanium oxide are sufficiently small, the insulating film 104 can be selectively etched. (Fig. 1
(D))

After that, the anodic oxide 107 is removed. As the etchant, a phosphoric acid-based solution, for example, a mixed acid of phosphoric acid, acetic acid, nitric acid, or the like is preferable. However, if a phosphoric acid-based etchant is used, for example, when the gate electrode is aluminum, the gate electrode is also etched at the same time. Therefore, in the present invention, by applying an electric current in an ethylene glycol solution containing 3 to 10% of tartar solution, boric acid and nitric acid to the gate electrode in the previous step, the side surface of the gate electrode and A barrier type anodic oxide 108 may be provided on the upper surface. In this anodic oxidation step, the pH of the electrolytic solution may be 2 or higher, preferably 3 or higher, more preferably 6.9 to 7.1. In order to obtain such a solution, it is preferable to neutralize it with an alkaline solution such as ammonia. The thickness of the obtained anodic oxide is determined by the magnitude of the voltage applied between the gate electrode 105 and the opposite electrode.

It should be noted that, although barrier type anodization is a later step, it does not mean that barrier type anodization is formed outside the porous anodization, but rather barrier type anodization. The object 108 is to be formed between the porous anodic oxide 107 and the gate electrode 105. In the phosphoric acid-based etchant, the etching rate of the porous anodic oxide is 10 times or more that of the barrier type anodic oxide. Therefore, the barrier type anodic oxide 108 is not substantially etched by the phosphoric acid-based etchant, so that the inner gate electrode can be protected. (Fig. 1 (C), (E))

Through the above steps, it is possible to obtain a structure in which a part of the insulating film 104 (hereinafter referred to as a gate insulating film) remains selectively under the gate electrode. Since the gate insulating film 104 ′ originally existed below the porous anodic oxide 107, not only the gate electrode 105 and the barrier anodic oxide 108 but also the barrier anodic oxide 108. Is present at a position separated by a distance of from y to y, and its width y is characterized by being determined in a self-aligned manner. In other words, a region where the gate insulating film 104 ′ is present and a region where it is not present are formed in a self-aligned manner outside the channel formation region under the gate electrode in the active layer 103.

When ions of N-type or P-type impurities accelerated by this structure are implanted into the active layer, a large number of ions are implanted into a region where the insulating film 104 does not exist (or is thin), and (relatively) high. Concentration impurity regions (low resistance impurity regions) 110 and 113 are formed. On the other hand, in the region where the gate insulating film 104 ′ is present, ions are implanted into this gate insulating film and only the ions that have passed through are implanted into the semiconductor, so the amount of ion implantation is relatively reduced, Low concentration impurity region (high resistance impurity region) 111,
112 is formed. Low concentration impurity regions 111 and 11
The difference in the impurity concentration between the high impurity concentration regions 110 and 113 and the impurity concentration in the high concentration impurity regions 110 and 113 varies depending on the thickness of the insulating film 104 and the like, but is usually 0.5 to 3 digits, which is smaller in the former case. Further, impurities are not substantially implanted into the region under the gate electrode, and the intrinsic or substantially intrinsic state is maintained, that is, the channel forming region is formed. After the impurities are injected, the impurities may be activated by irradiating a laser or strong light equivalent thereto, but needless to say, this step is substantially sufficient once. (Fig. 1 (E))

As described above, the present invention is characterized in that the width of the high resistance impurity region is controlled in a self-aligned manner by the thickness y of the anodic oxide 107. Then, the end portion 109 of the gate insulating film 104 ′ and the high resistance region (HRD) 112 are further formed.
The ends 117 of the can be approximately matched. In the conventional method shown in FIG. 6, it is extremely difficult to control the width of the side wall which plays such a role, but in the present invention, the width of the anodic oxide 107 is determined by the anodic oxidation current (charge amount). Therefore, extremely delicate control is possible.

Further, as is clear from the above steps, the low resistance region and the high resistance region can be formed even if the impurity doping step is substantially performed once, and the subsequent activation step is also performed. It only needs to be processed once. As described above, according to the present invention, mass productivity can be improved by reducing the steps of doping and activation. Conventionally, since the HRD has a large resistance, it has been difficult to make an ohmic contact with the electrode, and this resistance causes a decrease in the drain voltage. However, on the other hand, the presence of HRD also has the advantage that hot carrier generation can be suppressed and high reliability can be obtained. The present invention can solve these contradictory problems all at once, and can obtain ohmic contact with the HRD having a width of 0.1 to 1 μm formed in a self-aligned manner and the source / drain electrodes.

Further, in the present invention, by appropriately utilizing the thickness of the anodic oxide 108 of FIG. 1, the positional relationship between the end portion of the gate electrode and the impurity region can be arbitrarily changed.
An example of this is shown in FIG. For example, in a method in which ions are injected without being substantially mass-separated, such as an ion doping method (also referred to as plasma doping), the angle of entry of the ions is different, so there is a considerable spread of impurities in the lateral direction. In other words, it is expected that the ions will spread laterally to the extent of the penetration depth. In the following example, the active layer 40
The thickness of 4 is 800Å.

Therefore, as shown in FIG. 4A, the thickness (for example, 800 Å) of the anodic oxide 402 (corresponding to FIGS. 1 and 108) outside the metal gate electrode 401 is similar to that of the active layer 404. If the thickness is almost 4
01 end 405 and the high resistance impurity region 407 end 40
6 does not overlap and does not separate, resulting in a matched state. Figure 4
As in (B), the thickness of the anodic oxide 402 is, for example, 30
If the thickness is greater than 00Å and the thickness of the active layer is greater than 800Å, the end 405 of the gate electrode and the end 406 of the high resistance impurity region
Are separated from each other by offset. On the contrary, when the thickness of the anodic oxide 402 is reduced as shown in FIG. 4C, the gate electrode and the high resistance impurity region overlap with each other. This overlap becomes maximum when no anodic oxide is present around the gate electrode 401 as shown in FIG.

Generally, in the offset state, the reverse leak current is reduced and the on / off ratio is improved. For example, as in a TFT (pixel TFT) used for controlling pixels of an active matrix liquid crystal display, It is suitable for applications that require low leakage current. However, the hot carriers generated at the edges of the HRD are trapped in the anodic oxide,
It also has the drawback of deterioration.

In the overlapped state, deterioration due to hot carrier traps as described above is reduced, and the on-current increases, but the leak current increases. Therefore, a TFT (driver TF) which is used in a peripheral circuit of a monolithic type active matrix, for example, which requires a large current driving capability.
Suitable for T). The TFT actually used is shown in FIG.
Which of (D) to (D) should be determined depending on the application of the TFT.

[0030]

[Embodiment] [Embodiment 1] FIG. 1 shows the present embodiment. First, the substrate (Corning 7059, 300 mm x 400 m
m or 100 mm × 100 mm) 101, a silicon oxide film having a thickness of 1000 to 3000 Å was formed as a base oxide film 102. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, a film obtained by decomposing / depositing TEOS by the plasma CVD method may be used.

Thereafter, an amorphous silicon film is deposited by plasma CVD or LPCVD to a thickness of 300 to 5000 Å, preferably 500 to 1000 Å, which is deposited at 550 to 600.
It was left to stand in a reducing atmosphere at 0 ° C. for 24 hours for crystallization.
This step may be performed by laser irradiation.
Then, the silicon film crystallized in this manner was patterned to form the island regions 103. Further, a silicon oxide film 104 having a thickness of 700 to 1500 Å was formed thereon by a sputtering method.

Thereafter, aluminum having a thickness of 1000Å to 3 μm (1 wt% Si, or 0.1 to 0.3 wt) is used.
% Sc (scandium) -containing film was formed by an electron beam evaporation method or a sputtering method. Then, a photoresist (for example, OFPR800 / 3 manufactured by Tokyo Ohka)
0 cp) was formed by spin coating. Before forming the photoresist, the thickness of 100 to 1 is formed by the anodic oxidation method.
If a 000Å aluminum oxide film is formed on the surface, the adhesion to the photoresist is good, and the leakage of current from the photoresist is suppressed, so that the porous anodic oxide is used in the subsequent anodic oxidation process. It was effective in forming only on the side surface. After that, the photoresist and the aluminum film are patterned and etched together with the aluminum film to form the gate electrode 105 mask film 10
It was set to 6. (Fig. 1 (A))

Further, current is anodized in the electrolytic solution by applying an electric current to obtain a thickness of 3000 to 6000Å, for example, a thickness of 50.
A 00Å anodized oxide 107 was formed. Anodic oxidation is 3
~ 30% using an acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc.
A constant current of V may be applied to the gate electrode. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.) having a pH of 0.9 to 1.0, and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (Fig. 1 (B))

Next, the mask was removed, and a current was applied to the gate electrode again in the electrolytic solution. This time, 3-1
PH = 6.9 containing 0% tartar solution, boric acid and nitric acid
An ethylene glycol ammonia solution of 7.1 was used.
A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. Therefore, barrier type anodic oxide 108 was formed on the upper surface and the side surface of the gate electrode. The thickness of the anodic oxide 108 is proportional to the applied voltage, and the applied voltage is 150
2000 V of anodic oxide was formed. The thickness of the anodic oxide 108 was determined by the size of the required offset, overlap, as shown in FIG.
250V to obtain anodic oxide with a thickness of 3000Å or more
Since the above high voltage is required and the characteristics of the TFT are adversely affected, the thickness is preferably 3000 Å or less.
In this example, the voltage was raised to 80 to 150 V and the voltage was selected according to the required thickness of the anodic oxide film 108. (Fig. 1 (C))

After that, the silicon oxide film 104 was etched by the dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being deeply etched by sufficiently increasing the selection ratio of silicon and silicon oxide. For example, if CF ₄ is used as the etching gas, the anodic oxide is not etched, but only the silicon oxide film 104 is etched. Also,
The silicon oxide film 104 'under the porous anodic oxide 107 remained without being etched. (Fig. 1 (D))

After that, the anodic oxide 107 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 107 was etched, and the etching rate was about 600 Å / min. The underlying gate insulating film 104 'remained as it was. Then, by the ion doping method, impurities are injected into the active layer 103 of the TFT in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) and the gate insulating film as a mask, and the low resistance impurity region ( Source / drain region) 11
0, 113 and high resistance impurity regions 111, 112 were formed. Since phosphine (PH ₃ ) was used as the doping gas, it became an N-type impurity region. To form the P type impurity region, diborane (B ₂ H ₆ ) may be used as a doping gas. Dose amount is 5 × 10 ^{14 to} 5 × 1
The acceleration energy was 0 ¹⁵ cm ^-2 and the acceleration energy was 10 to 30 keV. After that, a KrF excimer laser (wavelength 248n
m, pulse width 20 nsec) to activate the impurity ions introduced into the active layer.

Results of SIMS (Secondary Ion Mass Spectroscopy)
According to this, the impurity concentration of the regions 110 and 113 is 1 × 10.
²⁰~ 2 x 10^{twenty one}cm^-3, 1 × 1 in areas 111 and 112
0¹⁷~ 2 x 10¹⁸cm^-3Met. In dose conversion,
The former is 5 × 10¹⁴~ 5 x 10 ¹⁵cm^-2, The latter is 2 × 10
¹³~ 5 x 10¹⁴cm^-2Met. This difference is gate insulation
The presence or absence of the membrane 104 ',
Generally, the impurity concentration in the low resistance impurity region is high
It is 0.5 to 3 orders of magnitude larger than that in the pure region. (Fig. 1
(E))

Finally, the inter-layer insulator 114 is formed on the entire surface.
A silicon oxide film having a thickness of 3000 Å was formed by the CVD method. Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 115 and 116 were formed. Further, hydrogen annealing was performed at 200 to 400 ° C. By the above, the TFT was completed. (Fig. 1
(F))

An example in which a plurality of TFTs are formed on one substrate by using the method shown in FIG. 1 is shown in FIG. In this example, three TFTs, TFT1 to TFT3, are formed. TFT
1 and 2 are used as driver TFTs, and an oxide 501 corresponding to the anodic oxide 108 in FIG.
The thickness of 502 is 200 to 1000 Å, for example, 500 Å, and the gate electrode and high resistance region (HR
D) was made to overlap. In the figure, TF
Connect the drain of T1 and the source of TFT2 to each other,
In addition, an example is shown in which the source of the TFT1 is grounded and the drain of the TFT2 is connected to the power source so as to form a CMOS inverter. As the peripheral circuit, there are various other circuits, but such a CMOS type circuit may be used according to the specifications of each circuit.

On the other hand, the TFT 3 is used as a pixel TFT, and the anodic oxide 503 is thickened to 2000 Å to make it in an offset state (corresponding to FIG. 4B) to suppress the leak current. One of the source / drain electrodes of the TFT 3 is connected to the ITO pixel electrode 501. To change the thickness of anodic oxide in this way,
It may be separated so that the voltage of the gate electrode of T can be independently controlled. Note that TFT1 and TFT3 are N-channel TFTs, and TFT2 is a P-channel TFT.

Example 2 FIG. 2 shows this example. First, a substrate having an insulating surface (eg Corning 705)
9) The underlying oxide film 202, the island-shaped silicon semiconductor region (for example, crystalline silicon semiconductor) 203, the silicon oxide film 204, and the aluminum film (on the surface of 201 by using the steps (A) and (B) of Example 1 ( A gate electrode 205 having a thickness of 200 nm to 1 μm) and a porous anodic oxide (thickness 3000 Å to 1 μm, for example 5000 Å) 206 were formed on the side surfaces of the gate electrode 205. (FIG. 2 (A)) Then, similarly to Example 1, a barrier type anodic oxide 207 having a thickness of 1000 to 2500 Å was formed. (Fig. 2 (B))

Further, the porous anodic oxide 206 is masked.
As a result, the silicon oxide film 204 is etched to form a gate insulating film.
A film 204 'was formed. After that, the barrier type anodic oxide film 2
Etching the porous anodic oxide film 206 using 07 as a mask
Removed. Then, the gate electrode portion (205, 20
7) and the gate insulating film 204 'as a mask
Impurity injection is performed by the doping method, and low resistance
Pure regions 208, 211, high resistance impurity regions 209, 2
Formed 10. Dose amount is 1-5 × 10¹⁴cm ^-2, Addition
The fast voltage was 30 to 90 kV. Phosphorus is used as an impurity
I was there. (Fig. 2 (C))

Further, a film of an appropriate metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium or the like, for example, a titanium film 212 having a thickness of 50 to 500 Å is formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 212 was formed in close contact with the low resistance impurity regions 208 and 211. (Fig. 2
(D))

Then, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is irradiated to activate the doped impurities, and at the same time react the metal film (titanium in this case) with silicon in the active layer to form a metal silicide ( Here, regions 213 and 214 of titanium silicide) are formed.
Laser energy density is 200-400 mJ / cm
² , preferably 250-300 mJ / cm ² . Also, the substrate is 200 to 500 ° C. during laser irradiation.
When heated to above, peeling of the titanium film could be suppressed.

In this embodiment, the excimer laser is used as described above, but it goes without saying that another laser may be used. However, when using a laser, a pulsed laser is preferable. Since the irradiation time of the continuous wave laser is long, there is a risk that the object to be irradiated expands due to heat and peels off.

Regarding the pulse laser, Nd: YAG
Infrared laser such as laser (preferably Q-switch pulse oscillation) or visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl and ArF can be used, but when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select the laser light that passes through the underlying silicon semiconductor film.

The annealing may be lamp annealing by irradiation with visible light or near infrared light.
When performing lamp annealing, the surface to be irradiated is 600
The lamp irradiation is performed at 600 ° C. for several minutes, and at 1000 ° C. for several tens of seconds so that the temperature becomes about 1000 ° C. In annealing with near infrared rays (for example, infrared rays of 1.2 μm), the near infrared rays are selectively absorbed by the silicon semiconductor, do not heat the glass substrate so much, and shorten the irradiation time once, thereby heating the glass substrate. It can be suppressed and is extremely useful.

After that, the Ti film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at 5: 2: 2. The titanium film (for example, the titanium film existing on the gate insulating film 204 and the anodic oxide film 207) other than the portion in contact with the exposed active layer remains in the metal state as it is, but can be removed by this etching. On the other hand, the titanium silicides 213 and 214, which are metal silicides, are not etched and can be left. (Fig. 2 (E))

Finally, as shown in FIG. 2F, a silicon oxide film having a thickness of 2000 Å to 1 μm, for example 3000 Å, is formed as an interlayer insulator 217 on the entire surface by a CVD method to make contact with the source / drain of the TFT. A hole is formed and the aluminum wiring / electrodes 218, 219 are set to 200
It was formed to a thickness of 0Å to 1 μm, for example, 5000Å. In this example, the contact portion of the aluminum wiring was made of titanium silicide, and the stability of the interface with aluminum was better than that of silicon, so a highly reliable contact was obtained. In addition, this aluminum electrode 21
8 and 219 and the silicide regions 213 and 214, for example, titanium nitride is further formed as a barrier metal,
The reliability can be improved. In this example, the sheet resistance in the silicide region was 10 to 50 Ω / □. On the other hand, in the high resistance impurity regions 209 and 210, 10 to 100
kΩ / □, resulting in good frequency characteristics and
TF with little hot carrier deterioration even at high drain voltage
It was possible to make T.

In this embodiment, the low resistance impurity region 211 and the metal silicide region could be made to substantially coincide with each other. In particular, the end portion 215 of the gate insulating film 204 ′ and the high resistance impurity region 2
10 and the boundary 216 between the low-resistance impurity region 211 and the end portion 215 and the metal silicide region 214 at the same time.
4 (A) to (D) as a result of making the ends of FIG.
It will be clear that the low resistance impurity regions in ## EQU3 ## can be replaced by metal silicide regions.

An example in which a plurality of TFTs are formed on one substrate by using the method shown in FIG. 2 is shown in FIG. In this example, three TFTs, TFT1 to TFT3, are formed. TFT
1 and 2 are CMOS-configured driver TFTs, which are used here as inverter configurations.
The thickness of the oxides 505 and 506 corresponding to the anodic oxide 207 was set to a thin thickness of 200 to 1000 Å, for example, 500 Å, so that they slightly overlap each other. on the other hand,
The TFT 3 is used as a pixel TFT, and the thickness of the anodic oxide 503 was set to 2000 Å to make it an offset state to suppress the leak current. One of the source / drain electrodes of the TFT 3 is connected to the pixel electrode 502 of ITO. In order to change the thickness of the anodic oxide in this way, it is sufficient to separate the voltage of the gate electrode of each TFT so that it can be controlled independently. Note that TFT1 and TF
T3 is an N-channel type TFT, TFT2 is a P-channel type T
It is FT.

In this embodiment, the titanium film forming step is arranged after the ion doping step, but the order may be reversed. In this case, since the titanium film covers the entire surface at the time of ion irradiation, it is very effective in preventing abnormal charge (charge-up) which has been a problem in the insulating substrate. Alternatively, after the ion doping, annealing may be performed with a laser or the like, a titanium film may be formed, and then titanium silicide may be formed by irradiation with a laser or the like or thermal annealing.

[Third Embodiment] FIG. 3 shows the present embodiment. First, a base oxide film 302, an island-shaped crystalline semiconductor region, for example, a silicon semiconductor region 303, a silicon oxide film 304, is formed on a substrate (Corning 7059) 301 by using the steps (A) and (B) of Example 1. Aluminum film (thickness 2000Å ~ 1
A porous anodic oxide (thickness 6000Å) 306 was formed on the side surface of the gate electrode 305 and the gate electrode 305 (μm). (FIG. 3 (A)) Then, in the same manner as in Example 1, a barrier type anodic oxide 307 having a thickness of 1000 to 2500 Å was formed. (Fig. 3 (B))

Further, using the porous anodic oxide 306 as a mask, the silicon oxide film 304 was etched to form a gate insulating film 304 '. Then, the porous anodic oxide 30
6 was selectively etched to expose a part of the gate insulating film 304 '. After that, an appropriate metal, for example, a titanium film 308 having a thickness of 50 to 500 Å was formed on the entire surface by sputtering. (Figure 3 (C)) And K
rF excimer laser (wavelength 248 nm, pulse width 2
For 0 nsec) to react titanium with silicon in the active layer to form titanium silicide regions 309 and 310. The energy density of the laser is 200 to 400 mJ / cm ² ,
250 to 300 mJ / cm ² was suitable. Also, the substrate is 200 to 500 ° C. during laser irradiation.
When heated to above, peeling of the titanium film could be suppressed. This step may be performed by lamp annealing by irradiation with visible light or near infrared light.

After that, the Ti film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at 5: 2: 2. The titanium film (for example, the titanium film existing on the gate insulating film 304 ′ and the anodic oxide film 307) other than the portion in contact with the exposed active layer remains in the metal state as it is, but can be removed by this etching. On the other hand, titanium silicide 3
Since 09 and 310 are not etched, they can be left. (Fig. 3 (D))

After that, impurities are implanted by an ion doping method using the gate electrode portion and the gate insulating film 304 as a mask to form low resistance impurity regions (≈titanium silicide regions) 311, 314 and high resistance impurity regions 312, 313.
Was formed. The dose amount was 1 to 5 × 10 ¹⁴ cm ^-2 , and the acceleration voltage was 30 to 90 kV. Phosphorus was used as an impurity. (Fig. 3 (E))

Then, the KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated again to activate the doped impurities. This step may be performed by lamp annealing by irradiation with visible light or near infrared light. Finally, the gate insulating film 30 is formed using the gate electrode portions (305, 307) as a mask.
4'was etched. This was done in order to avoid instability due to impurities doped in the gate insulating film 304 '. As a result, the gate insulating film 304 ″ remained only under the gate electrode portion.

Then, as shown in FIG. 3F, a silicon oxide film having a thickness of 6000Å is formed as an interlayer insulator 315 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and an aluminum wiring is formed.・ Electrode 3
16 and 317 were formed. Through the above steps, TFT
Was completed.

[0059]

According to the present invention, the high resistance impurity region (HRD) can be formed by substantially one-time doping and one-time laser annealing, and an activation process such as RTA. This shortening of the process improves mass productivity and
This is effective in reducing the amount of investment in the T manufacturing line.
Further, in the present invention, since the width of the HRD is formed with extremely high accuracy, a TFT having excellent yield and uniformity can be obtained.

In the present invention, in order to further improve the characteristics, more doping, laser annealing or RTA may be performed, and the number of times of doping or laser annealing or RTA is not limited to once. Not a thing. Needless to say, the TFT of the present invention is formed in the same manner whether a three-dimensional integrated circuit is formed on a substrate on which a semiconductor integrated circuit is formed or when it is formed on glass, organic resin, or the like. Is formed on the insulating surface in any case. In particular, the effect of the present invention is remarkable for an electro-optical device such as a monolithic active matrix circuit having peripheral circuits on the same substrate.

In the present invention, in addition to ion implantation or ion doping of P or N type impurities, carbon,
Oxygen and nitrogen may be added at the same time. By doing so, the reverse leakage current is reduced and the breakdown voltage is also improved. For example, it is effective when used as a pixel TFT of an active matrix circuit. In this case, the thickness of the anodic oxide layer of the TFT 3 shown in FIG. 5 can be the same as that of the TFT 1 and the TFT 2.

[Brief description of drawings]

FIG. 1 shows a method of manufacturing a TFT according to a first embodiment.

FIG. 2 shows a method of manufacturing a TFT according to a second embodiment.

FIG. 3 shows a method of manufacturing a TFT according to a third embodiment.

FIG. 4 shows the relationship between offset and overlap in the present invention.

FIG. 5 shows an example of an integrated circuit of TFTs obtained in Examples 1 and 2.

FIG. 6 shows a method of manufacturing a TFT by a conventional method.

[Explanation of symbols]

101 Insulating Substrate 102 Base Oxide Film (Silicon Oxide) 103 Active Layer (Crystalline Silicon) 104 Insulating Film (Silicon Oxide) 104 ′ Gate Insulating Film 105 Gate Electrode (Aluminum) 106 Mask Film (Photoresist) 107 Anodic Oxide (Porous) Aluminum oxide) 108 Anodic oxide (barrier type aluminum oxide) 109 Gate insulating film end portions 110, 113 Low resistance impurity regions 111, 112 High resistance impurity region (HRD) 114 Interlayer insulating film (silicon oxide) 115, 116 Metal wiring・ Electrode (aluminum) 117 Boundary between low resistance impurity region and high resistance impurity region

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideto Onuma             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Inventor Naoaki Yamaguchi             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Inventor Hideomi Suzawa             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Inventor Hideki Uochi             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory (72) Inventor Yasuhiko Takemura             398 Hase, Atsugi City, Kanagawa Prefecture, Ltd.             Conductor Energy Laboratory F-term (reference) 2H092 GA59 JA24 JA28 JA40 KA04                       KA07 KA10 MA08 MA17 MA24                       MA27 MA29 MA41 NA22 NA27                       NA29                 5F110 AA01 AA06 AA14 AA16 BB02                       BB04 BB10 BB11 CC02 DD01                       DD02 DD07 DD13 EE01 EE03                       EE04 EE05 EE06 EE09 EE14                       EE34 EE43 EE44 FF02 FF28                       GG02 GG13 GG25 GG35 GG45                       GG47 HJ01 HJ02 HJ04 HJ12                       HJ13 HJ18 HJ23 HK05 HK33                       HK40 HK42 HL01 HL03 HL07                       HL11 HM13 HM14 HM15 NN02                       NN04 NN23 NN35 NN72 NN78                       PP03 PP10 PP13 PP40 QQ08                       QQ11 QQ24

Claims (7)

[Claims] 1. A semiconductor device in which a pixel electrode, a pixel portion having a plurality of pixels provided with thin film transistors connected to the pixel electrode, and a peripheral circuit including a plurality of thin film transistors are provided on the same substrate. The semiconductor film of the thin film transistor of the pixel section has a semiconductor film provided with a channel formation region, a gate insulating film on the semiconductor film, and a gate electrode on the gate insulating film. The film is further provided with a high resistance impurity region and a low resistance impurity region,
The gate electrode does not overlap with the high resistance impurity region, the peripheral circuit has a semiconductor film provided with a channel formation region, a high resistance impurity region and a low resistance impurity region, and a gate insulating film on the semiconductor film, A semiconductor device comprising: an N-channel thin film transistor having a gate electrode on the gate insulating film, wherein the N-channel thin film transistor has the gate electrode overlapping with the high resistance impurity region. 2. A semiconductor device in which a pixel electrode, a pixel portion having a plurality of pixels provided with thin film transistors connected to the pixel electrode, and a peripheral circuit including a plurality of thin film transistors are provided on the same substrate. The semiconductor film of the thin film transistor of the pixel section has a semiconductor film provided with a channel formation region, a gate insulating film on the semiconductor film, and a gate electrode on the gate insulating film. The film is further provided with a high resistance impurity region and a low resistance impurity region,
A side surface of the gate electrode coincides with an end portion of the high resistance impurity region on the low resistance impurity region side, and the peripheral circuit includes a semiconductor film provided with a channel formation region, a high resistance impurity region and a low resistance impurity region. An N-channel thin film transistor having a gate insulating film on the semiconductor film and a gate electrode on the gate insulating film, wherein the N-channel thin film transistor has the gate electrode overlapping with the high resistance impurity region. A semiconductor device characterized in that 3. A semiconductor device in which a pixel electrode, a pixel portion having a plurality of pixels provided with thin film transistors connected to the pixel electrode, and a peripheral circuit including a plurality of thin film transistors are provided on the same substrate. The semiconductor film of the thin film transistor of the pixel section has a semiconductor film provided with a channel formation region, a gate insulating film on the semiconductor film, and a gate electrode on the gate insulating film. The film is further provided with a high resistance impurity region and a low resistance impurity region,
The gate electrode is offset from the high resistance impurity region, and the peripheral circuit includes a semiconductor film provided with a channel formation region, a high resistance impurity region and a low resistance impurity region, and a gate insulating film on the semiconductor film. And a gate electrode on the gate insulating film, wherein the gate electrode of the N-channel thin film transistor overlaps the high resistance impurity region. 4. The N-channel thin film transistor of the peripheral circuit has a phosphorus concentration of 1 in the low resistance impurity region.
× 10 is ²⁰ to 2 × 10 ²¹ cm ^-3, the concentration of phosphorus of the high resistance impurity region, 1 × 10 ¹⁷ to 2 × 10 ¹⁸ cm of claims 1 to 3, characterized in that a ^-3 The semiconductor device according to claim 1. 5. The thin film transistor of the pixel portion is an N-channel thin film transistor, wherein the low resistance impurity region has a phosphorus concentration of 1 × 10 ²⁰ to 2 × 10 ²¹ cm ⁻³ , and the high resistance impurity is The phosphorus concentration in the region is 1 × 10 ¹⁷ to
The semiconductor device according to claim 1, wherein the semiconductor device has a size of 2 × 10 ¹⁸ cm ⁻³ . 6. The semiconductor device according to claim 1, wherein the N-channel thin film transistor of the peripheral circuit is used in a CMOS circuit. 7. The N-channel thin film transistor of the peripheral circuit is used in a CMOS circuit, and the P-channel thin film transistor of the CMOS circuit is
A semiconductor film provided with a channel formation region and a P-type impurity region, a gate insulating film on the semiconductor film, and a gate insulating film on the gate insulating film, wherein the gate electrode is the P-type impurity. The semiconductor device according to claim 1, wherein the semiconductor device overlaps the region.