JP4073672B2 - Method for manufacturing thin film transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulating gate type transistor (TFT) formed on an insulating surface such as an insulating material such as glass or a material in which an insulating film such as silicon oxide is formed on a silicon wafer, and a method for manufacturing the same. The present invention is particularly effective for a TFT formed on a glass substrate having a glass transition point (also referred to as strain temperature or strain point) of 750 ° C. or lower. The semiconductor device according to the present invention is used for an active matrix such as a liquid crystal display, a driving circuit such as an image sensor, or a three-dimensional integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, it is widely known that a TFT (Thin Film Transistor) is formed for the purpose of driving an active matrix type liquid crystal display device or an image sensor. In particular, recently, due to the necessity of high-speed operation, a crystalline silicon TFT having higher electric field mobility has been developed in place of an amorphous silicon TFT using amorphous silicon as an active layer. However, when more advanced characteristics and higher durability are required, a high resistance region (a drain having an offset gate without addition of impurities or a low impurity concentration drain (LDD) as used in semiconductor integrated circuit technology is used. )). However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular, since the element is formed on the insulating surface and reactive ion anisotropic etching cannot be performed sufficiently, there is a great restriction that a fine pattern cannot be formed.
[0003]
FIG. 3 shows a cross-sectional view of a typical process for manufacturing an HRD used up to now. First, a base film 302 is formed over a substrate 301 and an active layer is formed using crystalline silicon 303. Then, an insulating film 304 is formed on the active layer with a material such as silicon oxide (FIG. 3A).
[0004]
  Next, the gate electrode 305 is formed of polycrystalline silicon (phosphorus or other impurities).IsOr tantalum, titanium, aluminum or the like. Further, impurity elements (phosphorus and boron) are introduced by means such as ion doping using the gate electrode as a mask, and high resistance regions (HRD) 306 and 307 having a small doping amount are formed in the active layer 303 in a self-aligned manner. The The active layer region under the gate electrode into which no impurity is introduced becomes a channel formation region (FIG. 3B).
[0005]
The doped impurities are activated by a heat source such as a laser or a flash lamp. Next, an insulating film 308 such as silicon oxide is formed by means such as plasma CVD or APCVD (FIG. 3C), and this is anisotropically etched, so that the side wall 309 is adjacent to the side surface of the gate electrode. It is formed (FIG. 3D).
Then, again, an impurity element is introduced by means such as ion doping, and sufficient high concentration impurity regions (low resistance impurity regions, source / drain regions) 310 and 311 are formed in a self-aligning manner using the gate electrode 305 and the side wall 309 as a mask. Is formed in the active layer 303. That is, two independent impurities are implanted into the drain, and there is an anisotropic etching step between the implantation steps (FIG. 3E).
[0006]
The doped impurities are activated by a heat source such as a laser or a flash lamp. Finally, an interlayer insulator 312 is formed, contact holes are formed in the source / drain regions through the interlayer insulator, and wiring / electrodes 313 and 314 connected to the source / drain are formed by a metal material such as aluminum. (FIG. 3F).
[0007]
[Problems to be solved by the invention]
The above method follows the LDD manufacturing process in the conventional semiconductor integrated circuit as it is, and is a process that is difficult to apply as it is to the TFT manufacturing process on the glass substrate or is not preferable in terms of productivity. There is.
[0008]
First, the impurity implantation step and the activation of impurities by laser irradiation or the like are required at least twice. Moreover, there is a process such as anisotropic etching between these processes, and it is necessary to take out the substrate from the vacuum chamber each time. This lowered productivity. In particular, with regard to the activation of impurities, in the conventional semiconductor integrated circuit, the activation of the impurity element is performed by thermal annealing. Therefore, the activation of the impurities is performed after the introduction of the impurities is completed (that is, FIG. ) After the process of) was completed).
[0009]
However, especially for TFTs on glass substrates, it is difficult to perform thermal annealing due to temperature restrictions of the substrate, and there is no choice but to rely on laser annealing or flash lamp annealing (RTA or RTP). However, since these methods selectively anneal the irradiated surface, for example, a portion under the side wall 309 is not annealed. Therefore, annealing is required for every impurity doping.
[0010]
The second is the difficulty in forming the side wall. The thickness of the insulating film 308 is 0.5-2 μm. Usually, since the thickness of the base film 302 provided on the substrate is 1000 to 3000 mm, the base film is often mistakenly etched in this etching process, so that the substrate is often exposed and the yield is lowered. . Since the substrate used for manufacturing the TFT contains many elements harmful to the silicon semiconductor, it is necessary to avoid overetching reaching the substrate as much as possible. In addition, it is difficult to finish the width of the side wall uniformly. This is because, in plasma dry etching such as reactive ion etching (RIE), unlike the silicon substrate used in the semiconductor integrated circuit, the substrate surface is insulative, so that it is difficult to delicately control the plasma. It is.
[0011]
  Since the high resistance drain has high resistance, it is necessary to make its width as narrow as possible. However, due to the above variation, mass production is difficult.GThe problem was how to easily control the process (which determines the position without using a lithography method).
[0012]
The present invention relates to a method for forming a high-resistance impurity region by solving the above-described problems and further simplifying the process, and a TFT having a high-resistance region (high-resistance drain, HRD) formed as described above. . Here, the high resistance drain (HRD) means that, in addition to the drain having a high impurity concentration and a high resistance, carbon, oxygen, nitrogen or the like is added to prevent activation of the impurity regardless of the impurity concentration, As a result, the drain having a high resistance is included.
[0013]
[Means for Solving the Problems]
In forming the high resistance region, the present invention is characterized in that an oxide layer formed by means such as anodic oxidation of the gate electrode is positively used. In particular, the thickness of the anodic oxide can be precisely controlled, and the thickness of the anodic oxide is wide from a thin one of 1000 mm or less to a thick one of 5000 mm or more and can be uniformly formed. It is preferable as a material to replace the side wall by anisotropic etching.
[0014]
In particular, a so-called barrier type anodic oxide is not etched unless it is a hydrofluoric acid-based etchant, whereas a porous anodic oxide is selectively etched by an etchant such as phosphoric acid. For this reason, it can be processed without giving any damage (damage) to other materials constituting the TFT, for example, silicon and silicon oxide. In addition, both the barrier type and the porous type are extremely difficult to be etched by dry etching. In particular, the etching ratio with silicon oxide is also characterized by a sufficiently high selectivity.
The present invention is characterized in that a TFT is manufactured by the following manufacturing process. By adopting this process, the HRD can be configured more reliably and the mass productivity can be improved.
[0015]
FIG. 1 shows the basic steps of the present invention. First, the base insulating film 102 is formed over the substrate 101, and the active layer 103 is further formed of a crystalline semiconductor (in the present invention, a semiconductor in which crystals are mixed, such as single crystal, polycrystal, and semi-amorphous, is called a crystalline semiconductor. ). Then, an insulating film 104 is formed from a material such as silicon oxide so as to cover it, and a film is formed from a material that can be anodized. As the material of this film, anodizable aluminum, tantalum, titanium, silicon and the like are preferable. In the present invention, a gate electrode having a single layer structure using these materials alone may be used, or a gate electrode having a multilayer structure in which two or more of these materials are stacked may be used. For example, a two-layer structure in which titanium silicide is stacked on aluminum or a two-layer structure in which aluminum is stacked on titanium nitride. The practitioner may determine the thickness of each layer according to the required device characteristics.
[0016]
Further, a film serving as a mask in anodic oxidation is formed so as to cover the film, and both are patterned and etched simultaneously to form a gate electrode 105 and a mask film 106 thereon. As a material for the mask film, a photoresist used in a normal photolithography process, a photosensitive polyimide, or a material that can be etched with a normal polyimide may be used (FIG. 1A).
[0017]
Next, a porous anodic oxide 107 is formed on the side surface of the gate electrode by applying a current to the gate electrode 105 in an electrolytic solution. This anodizing step is performed using 3 to 20% of an acidic aqueous solution such as citric acid or succinic acid, phosphoric acid, chromic acid, sulfuric acid or the like. In this case, a thick anodic oxide of 0.5 μm or more can be formed at a low voltage of about 5 to 30 V (FIG. 1B).
[0018]
  Then, the insulating film 104 is etched by a dry etching method, a wet etching method, or the like. The etching depth is arbitrary, and etching may be performed until the underlying active layer is exposed, or may be stopped during the etching. However, from the viewpoint of mass productivity, yield, and uniformity, it is desirable to perform etching up to the active layer. At this time, the insulating film having the original thickness is left in the insulating film (gate insulating film) on the lower side of the region covered with the anodic oxide 107 and the gate electrode 105. The gate electrode is aluminum or tantalum.TheIn the case where the main component is tantalum and the insulating film 104 is mainly composed of silicon oxide, when a dry etching method is used, fluorine-based (for example, NF₃, SF₆If the dry etching is performed using the etching gas (1), the insulating film 104 made of silicon oxide is etched quickly, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently low, so that the insulating film 104 is selectively used. Can be etched.
[0019]
In wet etching, a hydrofluoric acid-based etchant such as 1/100 hydrofluoric acid may be used. In this case as well, the insulating film 104 made of silicon oxide is etched quickly, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently small, so that the insulating film 104 can be selectively etched (FIG. 1D). .
[0020]
Thereafter, the anodic oxide 107 is removed. As the etchant, a phosphoric acid solution, for example, a mixed acid of phosphoric acid, acetic acid, and nitric acid is preferable. However, for example, when the gate electrode is aluminum, if a phosphoric acid-based etchant is used, the gate electrode is also etched at the same time. In such a case, an electric current is applied in an ethylene glycol solution containing 3 to 10% tartaric acid, boric acid and nitric acid in the gate electrode in the previous step (FIG. 1C). Therefore, it is preferable to provide the barrier type anodic oxide 108 on the side surface and the upper surface of the gate electrode. In this anodic oxidation step, the thickness of the obtained anodic oxide is determined by the magnitude of the voltage applied between the gate electrode 105 and the opposing electrode.
[0021]
It should be noted that, despite the fact that barrier type anodic oxidation is a later process, the barrier type anodic oxide 108 is not formed on the outside of the porous anodic oxide. It is formed between the porous anodic oxide 107 and the gate electrode 105. In the phosphoric acid-based etchant, the etching rate of the porous anodic oxide is 10 times or more that of the barrier type anodic oxide. Accordingly, the barrier-type anodic oxide 108 having an appropriate thickness is not substantially etched by the phosphoric acid-based etchant, so that the inner gate electrode can be protected. Of course, if the gate electrode is not etched by the etchant used for etching the porous anodic oxide, it goes without saying that such a barrier type anodic oxide need not be provided (FIGS. 1C and 1C). E)).
[0022]
Through the above steps, a structure in which a part of the insulating film 104 (hereinafter referred to as a gate insulating film) is selectively left under the gate electrode can be obtained. Since the gate insulating film 104 ′ originally existed under the porous anodic oxide 107, not only the gate electrode 105 and the barrier anodic oxide 108 but also the barrier anodic oxide 108. It is a feature that the width y is determined in a self-aligned manner (without using a photolithography process). In other words, the region where the gate insulating film 104 ′ is present and the region where it is not present are formed in a self-aligned manner outside the channel formation region under the gate electrode in the active layer 103.
[0023]
N-type or P-type impurity ions accelerated by this structure are implanted into the active layer. Of course, the active layer under the gate electrode 105 (and the surrounding anodic oxide 108) is not substantially implanted. In the present invention, at least two acceleration conditions for impurity ions are used. For example, two types of acceleration conditions are set, such as ions having high acceleration energy (fast ions) and ions having low acceleration energy (slow ions). Then, when low-speed ions are first implanted, this cannot reach the regions 111 and 112 covered with the gate insulating film 104 ′ in the active layer, and mainly the regions 110 and 113 not covered with the gate insulating film. Injected into. Next, fast ions are implanted. It is assumed that the energy at this time is enough to pass through the gate insulating film 104 '. In this case, ions are also implanted into the regions 111 and 112 through the gate insulating film. On the other hand, many ions pass through the regions 110 and 113, and eventually, in this case, the ions are mainly injected into the regions 111 and 112 (FIGS. 1E and 1F).
[0024]
If the dose amount of low-speed ions is made larger than the dose amount of high-speed ions, the regions 110 and 113 become low resistance regions and the regions 111 and 112 become high resistance regions. The dose amount may be controlled by doping time or ion generation amount. In the above doping process, it is only necessary to change the acceleration voltage without changing the ion source of the impurity element. Also in this case, as in the above example, the low-speed ions may be used first and the high-speed ions may be used later, or vice versa.
[0025]
Furthermore, the acceleration voltage may be changed stepwise as shown in FIG. 4 (A), or may be changed continuously as shown in FIG. 4 (B). However, in any method, in the present invention, once the substrate is set in a doping apparatus, all doping processes are completed without taking them out to the outside, and a high resistance region is formed by one doping process. It is characterized by that.
[0026]
As described above, the present invention is characterized in that the width of the high resistance impurity region is controlled in a self-aligned manner by the thickness y of the anodic oxide 107. Further, the end portion 109 of the gate insulating film 104 ′ and the end portion 117 of the high resistance region (HRD) 112 can be substantially matched. In the conventional method shown in FIG. 3, it is extremely difficult to control the width of the side wall that plays such a role. In the present invention, the width of the anodic oxide 107 is determined by the anodic oxidation current (charge amount). Therefore, very delicate control is possible.
[0027]
Further, as is clear from the above steps, the low resistance region and the high resistance region can be formed even if the impurity doping step is substantially once, and the subsequent activation step is naturally 1. Only one process is required. Thus, in the present invention, mass productivity can be enhanced by reducing the steps of doping and activation. Conventionally, HRD has a large resistance, so that it is difficult to make ohmic contact with the electrode, and the drain voltage is lowered due to this resistance. However, on the other hand, the presence of the HRD has the advantage that generation of hot carriers can be suppressed and high reliability can be obtained. The present invention solves this contradictory problem all at once, and can obtain an ohmic contact with a 0.1 to 1 μm wide HRD formed in a self-aligned manner and the source / drain electrodes.
[0028]
Further, in the present invention, by appropriately utilizing the thickness of the anodic oxide 108 in FIG. 1, the positional relationship between the end portion of the gate electrode and the impurity region can be arbitrarily changed, and a so-called offset structure can be obtained.
In general, in the offset state, the reverse leakage current is reduced and the on / off ratio is improved. For example, a leakage current such as a TFT (pixel TFT) used for controlling a pixel of an active matrix liquid crystal display is used. Suitable for applications that require a small amount of However, it also has a disadvantage that the hot carriers generated at the end of the HRD are deteriorated by being trapped by the anodic oxide.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
FIG. 1 shows this embodiment. First, a silicon oxide film having a thickness of 1000 to 3000 mm was formed as a base oxide film 102 on a substrate (Corning 7059, 300 mm × 400 mm or 100 mm × 100 mm) 101. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further increase mass productivity, a film obtained by decomposing and depositing TEOS by plasma CVD may be used.
[0030]
Thereafter, an amorphous silicon film was deposited in an amount of 300 to 5000 Å, preferably 500 to 1000 に よ っ て by plasma CVD or LPCVD, and left to stand in a reducing atmosphere at 550 to 600 ° C. for 4 to 24 hours for crystallization. . This step may be performed by laser irradiation. Then, the island film 103 was formed by patterning the silicon film crystallized in this manner. Further, a silicon oxide film 104 having a thickness of 700 to 1500 mm was formed thereon by sputtering.
[0031]
Thereafter, an aluminum (including 1 wt% Si or 0.1 to 0.3 wt% Sc (scandium)) film having a thickness of 1000 to 3 μm was formed by electron beam evaporation or sputtering. A photoresist (for example, OFPR 800/30 cp, manufactured by Tokyo Ohka) was formed by spin coating. If an aluminum oxide film having a thickness of 100 to 1000 mm is formed on the surface by anodic oxidation before the formation of the photoresist, the adhesion with the photoresist is good and current leakage from the photoresist is suppressed. Thus, it was effective in forming the porous anodic oxide only on the side surface in the subsequent anodic oxidation step. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form the gate electrode 105 mask film 106 (FIG. 1A).
[0032]
Further, this was anodized through an electric current in an electrolytic solution to form anodic oxide 107 having a thickness of 3000 to 6000 mm, for example, 5000 mm. Anodization is performed using 3 to 20% of an acidic aqueous solution such as citric acid or succinic acid, phosphoric acid, chromic acid, sulfuric acid, etc., and a constant current of 5 to 30 V may be applied to the gate electrode. In this embodiment, the voltage was set to 8 V in an oxalic acid solution (30 ° C.), and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. The anodizing voltage was preferably lower than the anodizing voltage before resist application (FIG. 1B).
[0033]
Next, the mask was removed, and a current was applied to the gate electrode again in the electrolytic solution. This time, an ethylene glycol solution containing 3 to 10% tartaric acid solution, boric acid and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature of around 10 ° C. For this reason, the barrier type anodic oxide 108 was formed on the upper surface and the side surface of the gate electrode. The thickness of the anodic oxide 108 was proportional to the applied voltage, and 2000 anodic oxide was formed at an applied voltage of 150V. Although the thickness of the anodic oxide 108 was determined by the required offset width, a high voltage of 250 V or higher is necessary to obtain an anodic oxide having a thickness of 3000 mm or more, which adversely affects the TFT characteristics. The thickness is preferably 3000 mm or less. In this embodiment, the voltage is raised to 80 to 150 V, and the voltage is selected depending on the required thickness of the anodic oxide film 108 (FIG. 1C).
[0034]
Thereafter, the silicon oxide film 104 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selection ratio between silicon and silicon oxide. For example, CF as an etching gas_FourIs used, the anodic oxide is not etched and only the silicon oxide film 104 is etched. Further, the silicon oxide film 104 'under the porous anodic oxide 107 remained without being etched (FIG. 1D).
[0035]
Thereafter, the anodic oxide 107 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 107 was etched, and the etching rate was about 600 Å / min. The underlying gate insulating film 104 'remained as it was. Then, by ion doping, impurities are implanted into the active layer 103 of the TFT in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as a mask, and a low-resistance impurity region ( Source / drain regions) 110 and 113 and high resistance impurity regions 111 and 112 were formed. As a doping gas, phosphine (PH_Three), An N-type impurity region was formed. In order to form a P-type impurity region, diborane (B₂H₆) May be used as a doping gas. First, doping was performed at an acceleration energy of 1 to 30 keV, for example, 5 kV. Dose amount is 5 × 10¹⁴~ 5x10¹⁵cm^-2For example, 1 × 10¹⁵cm^-2It was. As a result, the regions 110 and 113 which are not covered with the gate insulating film 104 'are mainly doped with impurities to form a low resistance region (FIG. 1E).
[0036]
Thereafter, the acceleration energy was increased to 65 to 110 keV, for example, 90 kV while the substrate was set in the doping apparatus. Dose amount is 5 × 10¹²~ 5x10¹³cm^-2For example, 1 × 10¹³cm^-2It was. As a result, mainly, the regions 111 and 112 covered with the gate insulating film 104 ′ are doped with impurities to form a high resistance region (FIG. 1F).
Thereafter, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to activate impurity ions introduced into the active layer. In this way, the high resistance regions 111 and 112 were obtained.
[0037]
[Embodiment 2]
  FIG. 2 shows this embodiment. First, a base oxide film 202, an island are formed on a substrate having an insulating surface (for example, NA35 glass manufactured by NH Techno Glass Co., Ltd.) using the steps of FIGS.SilicaA gate electrode 205 of an elementary semiconductor region (for example, crystalline silicon semiconductor) 203, a silicon oxide film 204, an aluminum film (thickness: 200 nm to 1 μm), and a porous anodic oxide (thickness: 3000 μm to 1 μm, for example) 5000 cm) 206 was formed (FIG. 2A).
  Then, a barrier type anodic oxide 207 having a thickness of 1000 to 2500 mm was formed as in the first embodiment. Further, using the porous anodic oxide 206 as a mask, the silicon oxide film 204 was etched to form a gate insulating film 204 '(FIG. 2B).
[0038]
Thereafter, the porous anodic oxide film 206 was removed by etching using the barrier type anodic oxide film 207 as a mask. Thereafter, nitrogen ions were implanted by ion doping using the gate electrode portions (205, 207) and the gate insulating film 204 'as a mask. The doping gas is nitrogen gas (N₂) Was used. The dose is 1 × 10¹⁴~ 3x10¹⁶cm^-2For example, 2 × 10¹⁵cm^-2The acceleration voltage was 65 to 110 kV, for example, 80 kV. In this doping, since nitrogen ions are high-speed, ions pass through the regions 208 and 211 that are not covered with the gate insulating film 204 ′ and are hardly doped (SIMS (secondary ion mass spectrometry) method). According to 1 × 10¹⁹cm^-2It was the following. On the other hand, the regions 209 and 210 covered with the gate insulating film are 5 × 10 5¹⁹~ 2x10^{twenty one}cm^-3A concentration of nitrogen (depending on the depth) was introduced (FIG. 2C).
[0039]
  Next, the doping chamber atmosphere is changed to phosphine (PH ₃ ) And phosphorus ions were implanted. First, the acceleration energy was set to 65 to 110 keV, for example, 90 kV. Dose amount is 5 × 10¹²~ 5x10¹³cm^-2For example, 1 × 10¹³cm^-2It was. As a result, the region mainly covered with the gate insulating film 204 '209,210Impurities were doped to form a high resistance region (FIG. 2D).
  Thereafter, the acceleration energy was lowered to doping at 1 to 30 keV, for example, 5 kV while the substrate was set in the doping apparatus. Dose amount is 5 × 10¹⁴~ 5x10¹⁵cm^-2For example, 1 × 10¹⁵cm^-2It was. As a result, the regions 208 and 211 which are not covered with the gate insulating film 204 'are mainly doped with impurities to form a low resistance region (FIG. 2E).
[0040]
Thereafter, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to activate impurity ions introduced into the active layer. As the laser, a XeCl excimer laser (wavelength: 308 nm, pulse width: 50 nsec) may be used.
Needless to say, other lasers may be used in addition to the excimer laser. As for the pulse laser, an infrared laser such as an Nd: YAG laser (preferably Q-switched pulse oscillation) and a visible laser such as the second harmonic can be used. However, when laser irradiation is performed from the upper surface of a metal film. Therefore, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Moreover, you may irradiate a laser beam from the board | substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.
[0041]
Further, instead of the laser, lamp annealing by irradiation with visible light or near infrared light may be used. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several tens of seconds at 1000 ° C. so that the surface to be irradiated has a temperature of about 600 to 1000 ° C. Annealing with near-infrared rays (for example, 1.2 μm infrared rays) selectively absorbs near-infrared rays into the silicon semiconductor, does not heat the glass substrate so much, and shortens the irradiation time once, thereby heating the glass substrate. This is extremely useful.
[0042]
Finally, as shown in FIG. 2F, a silicon oxide film having a thickness of 2000 mm to 1 μm, for example, 3000 mm, is formed as an interlayer insulator 212 over the entire surface by CVD, and contact holes are formed in the source / drain of the TFT. The aluminum wiring / electrodes 213 and 214 were formed to a thickness of 2000 to 1 μm, for example, 5000 mm. If, for example, titanium nitride is formed as a barrier metal between the aluminum electrodes 213 and 214 and the low resistance regions 208 and 211, the reliability can be further improved.
[0043]
In the present embodiment, as a result, the high resistance regions 209 and 210 can be selectively doped with nitrogen. This may be oxygen, carbon, or a mixture thereof. By doing so, the leakage current of the TFT can be suppressed, and this is particularly suitable for the application in which the TFT of this embodiment requires high charge retention characteristics such as an active matrix.
The state of the doping process in this embodiment is shown in FIG. After nitrogen doping is first performed in this manner, nitrogen doping may be performed later as shown in FIG. In any case, the present embodiment is characterized in that both phosphorus doping and nitrogen doping can be performed continuously with the substrate set in a doping apparatus.
[0044]
【The invention's effect】
According to the present invention, a high resistance region (HRD) can be formed by an activation process such as one doping, one laser annealing, and RTA. In other words, it is no longer necessary to form the two types of the same conductivity type regions by an independent process as in the prior art. This shortening of the process increases mass productivity and is effective in reducing the amount of investment in the TFT production line. In the present invention, since the width of the HRD is formed with extremely high accuracy, a TFT having excellent yield and uniformity can be obtained.
[0045]
It goes without saying that the TFT of the present invention is similarly formed when a three-dimensional integrated circuit is formed on a substrate on which a semiconductor integrated circuit is formed, or when it is formed on glass or an organic resin. Is formed on an insulating surface in any case. In particular, the effect of the present invention is remarkable for an electro-optical device such as a monolithic active matrix circuit having peripheral circuits on the same substrate.
[Brief description of the drawings]
FIG. 1 shows a manufacturing method of a TFT according to Embodiment Mode 1;
FIG. 2 shows a manufacturing method of a TFT according to Embodiment Mode 2;
FIG. 3 shows a method for manufacturing a TFT by a conventional method.
FIG. 4 shows a state of a doping process in the present invention.
[Explanation of symbols]
101 Insulating substrate
102 Base oxide film (silicon oxide)
103 Active layer (crystalline silicon)
104 Insulating film (silicon oxide)
104 'gate insulation film
105 Gate electrode (aluminum)
106 Mask film (photoresist)
107 Anodic oxide (porous aluminum oxide)
108 Anodic oxide (barrier type aluminum oxide)
109 Edge of gate insulating film
110, 113 Low resistance impurity region
111, 112 High resistance impurity region (HRD)

Claims (6)

Amorphous silicon film is crystallized by laser irradiation to form a crystalline silicon film,
Forming a gate insulating film on the crystalline silicon film and a gate electrode on the gate insulating film;
An N-type or P-type first impurity is added to the crystalline silicon film at a first accelerating voltage and a first concentration using the gate insulating film and the gate electrode as a mask in a reaction vessel. Forming a low resistance region in a region of the conductive silicon film not covered with the gate insulating film,
After the addition of the first impurity, the crystalline silicon film is taken out of the reaction vessel and the same conductivity as the first impurity is applied to the crystalline silicon film using the gate electrode as a mask in the reaction vessel. By adding a second impurity of a type at a second acceleration voltage higher than the first acceleration voltage and a second concentration lower than the first concentration , the gate insulating film of the crystalline silicon film is added. A method for manufacturing a thin film transistor, wherein a high resistance region is formed in a region which is covered and does not overlap with the gate electrode. Amorphous silicon film is crystallized by laser irradiation to form a crystalline silicon film,
Forming a gate insulating film on the crystalline silicon film and a gate electrode on the gate insulating film;
By adding an N-type or P-type first impurity to the crystalline silicon film at a first acceleration voltage and a first concentration in the reaction vessel using the gate electrode as a mask, A high resistance region is formed in a region that is covered with the gate insulating film and does not overlap the gate electrode,
After the addition of the first impurity, the first crystalline silicon film is formed on the crystalline silicon film using the gate insulating film and the gate electrode as a mask in the reaction container without taking the crystalline silicon film out of the reaction container. And adding a second impurity having the same conductivity type as the first impurity at a second acceleration voltage lower than the first acceleration voltage and a second concentration higher than the first concentration. A method for manufacturing a thin film transistor, wherein a low resistance region is formed in a region not covered with the gate insulating film. In claim 1 or claim 2 ,
The method for manufacturing a thin film transistor, wherein said first impurity and said second impurity in the boron prime. In claim 1 or claim 2,
The method for manufacturing a thin film transistor, wherein the first impurity and the second impurity are phosphorus. In any one of Claims 1 thru | or 4 ,
The method for manufacturing a thin film transistor, wherein the first impurity and the second impurity are the same impurity. In any one of Claims 1 thru | or 5,
A method for manufacturing a thin film transistor, wherein nitrogen, oxygen, or carbon, or a mixture of nitrogen, oxygen, and carbon is added to the high resistance region.

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