JP3140304B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (T
FT). In particular, the present invention relates to a semiconductor device used for a switching transistor of an active matrix circuit.

[0002]

2. Description of the Related Art Conventionally, it has been widely known to form a thin film transistor (TFT) for driving an active matrix type liquid crystal display device, an image sensor and the like. Particularly, recently, crystalline silicon TFTs have been developed in place of amorphous silicon TFTs using amorphous silicon for the active layer due to the need for high-speed operation. However, as higher characteristics and higher durability are required, low-concentration drains (LDs) used in semiconductor integrated circuit technology are required.
D) It was required to have an area.

For example, a crystalline silicon TFT generally has a leak current when a reverse bias voltage (for example, a positive voltage in the case of a P-channel TFT) is applied to a gate electrode, as compared with an amorphous silicon TFT. (Called off current) is large,
In addition, a phenomenon that the reverse bias voltage increases as the absolute value of the reverse bias voltage increases has been observed. However, it is known that such an off-state current can be significantly reduced by providing an LDD region. For example, in an electro-optical device such as a liquid crystal display, when it is used as a switching transistor of an active matrix circuit, it is preferable that the off-state current be small for the purpose of retaining charge.

[0004] In addition, a deterioration phenomenon in which the on-current of the TFT is reduced by applying a voltage for a long time has been observed.
This is explained by taking an N-channel TFT as an example. Since a positive voltage is applied to the gate electrode, accelerated electrons are injected into the gate insulating film, and this becomes fixed charges, thereby forming a channel forming region thereunder. This is because a P-type region is generated although it is weak. This means that a PN junction is formed between the source and the drain, so that the current was blocked. However, by providing the LDD region, generation of a P-type region can be suppressed, and such a deterioration phenomenon can be reduced.

[0005] A conventional method for forming an LDD is performed as follows. First, low dose ion doping is performed on the entire surface using the gate electrode as a mask to form a low concentration impurity region. Then, a side wall is formed adjacent to the side surface of the gate electrode. As a method for forming the side wall, an anisotropic etching is performed after forming an insulating film on the entire surface. Next, high dose ion doping is performed on the entire surface using the previously formed side wall and the gate electrode as a mask to form a high concentration impurity region. By doing so, the region below the side wall formed on the side surface of the gate electrode, where the high dose ion doping has not been performed, becomes
A DD region was formed.

[0006]

However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular, the device is formed on an insulating surface, and reactive ion anisotropic etching cannot be performed sufficiently to form a fine pattern. Therefore, it is difficult to form a sidewall, and the yield due to over-etching is reduced. There is a problem that it is difficult to perform uniform processing. Further, in the conventional method, when the LDD region is formed, at least two ion doping steps are performed on the active layer, so that the number of steps is increased and the productivity is reduced. I was Further, the ion doping method has extremely poor controllability in a low dose region, for example, 5 × 10 ¹³ , as compared with the ion implantation method used in the semiconductor integrated circuit process (a method in which ions are mass-separated and implanted into a substrate). Control of the dose amount of atoms / cm ³ or less was practically impossible.

[0007]

SUMMARY OF THE INVENTION The present invention proposes a method for solving the above-mentioned problems in a TFT and obtaining a thin film transistor which can obtain substantially the same effect as an LDD. That is, the present invention has at least one set of N-type or P-type impurity regions provided in the active layer, and at least one gate electrode sandwiched between the impurity regions, and the gate electrode and at least one of the gate electrodes. An offset region is provided between the impurity regions, and a fixed charge is contained in a gate insulating film except for a portion below a gate electrode. Here, the fixed charge is N
Positive in channel type TFT, P channel type TFT
In, a negative one is used. The fixed charge is a charge that does not move due to an external electric field or the like, and ions having a large ionic radius, crystal defects, dangling bonds, and the like can be fixed charges.

FIG. 5 shows the structure of the present invention and the reason why the present invention can provide substantially the same effects as those of the LDD.
This will be described with reference to FIG. In the present invention, for example, in the case of a P-channel TFT, as shown in FIG. 5A, the P-type impurity region 502 is formed slightly away from the gate electrode portion. As a result, a substantially intrinsic region (offset region) 5 extends not only immediately below the gate electrode portion but also to a region in the vicinity thereof.
01 is formed. The offset region is a region between the gate electrode portion and the P-type region when the gate electrode portion and the P-type region are separated from each other as shown in FIG. It is. In the present invention, as shown in the figure, there may be a case where offset regions are provided on both sides of the gate electrode portion, or a case where only one of them is provided.

Next, as shown in FIG. 5B, thermal annealing in a chlorine atmosphere, plasma discharge in a chlorine atmosphere, ion doping, etc., are performed to introduce negative ions Cl ^- into the gate insulating film 503. I do. Cl ^- F instead of ^-
And the like may be used. The negative ions become fixed charges. In any of the thermal annealing, plasma discharge, and ion doping methods, Cl ⁻ hardly enters the portion where the gate electrode portion 504 was present. Thus, Cl ⁻ is introduced into the gate insulating film 503.

In the present invention, it is required to form the offset region stably. What is important in practicing the present invention is a process for manufacturing a gate electrode. An anodic oxidation method may be used to stably form the offset region. That is, after forming the gate electrode with an anodizable material, the gate electrode is energized in an electrolytic solution,
An anodic oxide is formed on at least the side surface of the gate electrode.
The anodic oxidation at this time may be selectively performed on the side surface of the gate electrode, or may be performed on the upper surface and the side surface of the gate electrode. As a material for the gate electrode, a metal mainly composed of anodizable aluminum, tantalum, titanium, and silicon, or an alloy thereof, or a multilayer film is preferable.

[0011] Aluminum as a gate electrode,
When a porous anodic oxide is used, 3
It may be carried out using an acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like of up to 20%. In this case, a relatively thick anodic oxide of 0.5 μm or more can be formed at a low voltage of about 5 to 50 V. The thickness of the porous anodic oxide depends on the energizing time, and a thicker anodic oxide can be obtained by prolonged energizing. The porous anodic oxide thus obtained is also easy to etch.

P-type impurities are doped using the anodic oxide and the gate electrode thus formed as a mask. Then, as shown in FIG. 1D, the P-type region (106) is separated from the gate electrode (105), and an offset region is obtained. Then, the anodic oxide formed in the previous step is removed. In the case of a porous anodic oxide using aluminum as a gate electrode, a phosphoric acid-based etchant may be used as the etchant. However, the phosphoric acid-based etchant also etches aluminum. To avoid this difficulty,
A nonporous anodic oxide coating may be provided between the porous anodic oxide and the gate electrode. Phosphoric acid etchant
Since the etching rate is extremely slow for nonporous anodic oxide, only porous anodic oxide can be selectively etched.

In order to form a nonporous anodic oxide between the porous anodic oxide and the gate electrode, tartaric acid, boric acid, nitric acid and the like are contained after forming the porous anodic oxide. The current may be applied in a neutral ethylene glycol solution. In this anodic oxidation step, the thickness of the resulting nonporous anodic oxide is determined by the maximum voltage applied between the gate electrode and the opposite electrode. In the present invention, the thickness of the nonporous anodic oxide formed for the above purpose (etching stopper) is 500 to 250.
0 ° is preferred.

After the anodic oxide is etched, negative ions are introduced into the gate insulating film by thermal annealing, plasma discharge, or ion doping in an atmosphere of a negative ion source (for example, an atmosphere of a chlorine-based gas). Among them, when plasma discharge is adopted, when ECR plasma discharge is used, plasma damage to the device is reduced by R
This is preferable because it is smaller than F discharge or the like. Further, it is preferable to activate the doped P-type impurity before introducing the negative ions. Furthermore, when introducing negative ions, hydrogen may be introduced at the same time to neutralize dangling bonds of silicon in the active layer.

The negative ions introduced into the gate insulating film by the above-described means are expected to be released due to a subsequent process (thermal annealing or the like) or a change in environment.
This can be dealt with by forming a coating (for example, silicon nitride) having a barrier action over the gate insulating film. Although the above example relates to a P-channel TFT, the same can be applied to an N-channel TFT. However, in the case of an N-channel TFT,
It is necessary to use a positive fixed charge instead of a negative ion.

[0016]

As described above, the offset region (5 in FIG. 5)
01) When negative ions, which are fixed charges, are introduced into the upper gate insulating film, holes are drawn to the surface layer of the underlying semiconductor layer by the negative ions. At this time, in the impurity region 502, there is almost no change because the impurity region is originally a P-type impurity region, and the effect is remarkably exhibited in the substantially intrinsic semiconductor region which was the offset region 501, and holes are drawn. Weak P-type region 50
5 are formed. Then, the weak P-type region 505 exhibits substantially the same effect as that of the LDD. Such a weak P-type region 505 means a drain induced by fixed charges, and is referred to as a charge-induced drain (Charge-Inducer).
ed-Drain, CID).

The above-described operation appears exactly the same when a positive fixed charge is introduced into an N-channel TFT. In that case, electrons are attracted to the offset region by the positive fixed charges, and a weak N-type CID is formed.
In the present invention, the gate electrode portion (504 in FIG. 5) does not need to be entirely made of a conductor.
An insulating coating may be provided on the surface of the conductor. This will be apparent from the reason that the gate electrode portion is mainly used in the present invention for selectively introducing positive or negative fixed charges.

The semiconductor device of the present invention has a special effect in that it contributes to a reduction in off current. Therefore,
When the present invention is applied to a switching transistor of an active matrix circuit, a great effect can be obtained.
In particular, as described in Japanese Patent Application Laid-Open No. 5-335572, the advantage of using a P-channel TFT as a switching transistor of an active matrix circuit is known. Is smaller than that of an N-channel TFT. When a P-channel TFT having such advantageous characteristics is used for an active matrix circuit and the present invention is applied thereto, the off-state current can be further reduced, and the characteristics of the active matrix circuit can be improved. Can be. Further, it is clear that the effect of the present invention is also effective in preventing deterioration such as reduction in on-state current, because the operation of the present invention is exactly the same as that of the conventional LDD structure.

[0019]

【Example】

Embodiment 1 FIG. 1 shows this embodiment. First, the substrate 101
(Corning 7059, 100 mm × 100 mm) as a base oxide film having a thickness of 1000 to 5000 °, for example,
A 3000 ° silicon oxide film 102 was formed by a sputtering method in an oxygen atmosphere. After that, plasma CV
The amorphous silicon film is formed in a thickness of 300 to 1 by the D method or the LPCVD method.
500 °, for example, 500 ° deposited, and
It was left in a reducing atmosphere at 600 ° C. for 8 to 24 hours to be crystallized. In that case, crystallization may be promoted by adding a trace amount of a catalyst element such as nickel which promotes crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was etched to form an island-shaped silicon film 103. This island-shaped silicon film 103 forms an active layer of the TFT later. further,
A gate insulating film 104 was formed thereon. Here, a silicon oxide film having a thickness of 700 to 1500 Å, for example, 1200 に よ っ て was formed by a plasma CVD method. (Figure 1
(A))

Thereafter, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) film having a thickness of 1000 to 3 μm, for example, 6000 ° is formed by a sputtering method. Then, a thin anodic oxide film having a thickness of 100 to 400 ° was formed on the surface of the aluminum film by an anodic oxidation method. For example, as an electrolytic solution at the time of anodic oxidation, a substrate is immersed in an ethylene glycol solution of 3% tartaric acid (neutral pH adjusted with ammonia), a current is passed through the aluminum film, and a constant current of 20 mV is applied. A voltage was applied, and the voltage was increased to 12 V to perform anodic oxidation. The resulting anodic oxide was nonporous and had a thickness of less than 200 °. This thin anodic oxide
It has the function of maintaining the adhesion to the photoresist in the next anodic oxidation step.

Thereafter, a photoresist having a thickness of about 1 μm was formed on the thus treated aluminum film by spin coating. Then, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form the gate electrode 105. Here, a photoresist mask 106 is formed on the gate electrode 105.
Exists. (FIG. 1 (B)) Next, the substrate was immersed in a 10% oxalic acid solution,
For example, at a constant voltage of 10 V for 10 to 500 minutes, for example, 80
The anode electrode 105 is anodized by applying a current to the gate electrode 105, and the porous anodic oxide 1
07 was formed on the side surface of the gate electrode 105. Since the photoresist mask 106 was present on the upper surface of the gate electrode 105, the anodic oxidation hardly proceeded.

Next, the mask material 106 is removed to expose the upper surface of the gate electrode, and the substrate is immersed in an ethylene glycol solution of 3% tartaric acid (neutral pH adjusted with ammonia). A voltage was applied at a constant current of 20 mV, and the voltage was increased to 100 V to perform anodization. In this case, not only the upper surface of the gate electrode,
The side surface of the gate electrode was also anodized to form a dense nonporous anodic oxide 108 having a thickness of 1400 °. (Figure 1
(C))

Thereafter, boron is implanted into the island-like silicon film 103 as an impurity in a self-aligned manner using the gate electrode portion (gate electrode and surrounding anodic oxide) as a mask, thereby forming the P-type impurity region 109. Formed.
Here, the dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm.
^{2. The} acceleration voltage is 40 to 80 kV, for example, the dose amount is 1
× 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 65 kV.
(Fig. 1 (D))

Then, the porous anodic oxide 107 was etched with a phosphoric acid-based etchant to expose the non-porous anodic oxide 108. Since the etching rate of the phosphoric acid-based etchant is extremely low with respect to the non-porous anodic oxide, only the porous anodic oxide can be selectively etched. Protected by etching process. At this time, an offset region was formed in the lower portion of the portion where the porous anodic oxide 107 was present, because boron was not doped.

Thereafter, a KrF excimer laser (wavelength 2
Irradiation of 48 nm and a pulse width of 20 nsec) was performed to activate the doped impurity region. The energy density of the laser was 200 to 400 mJ / cm ² , and preferably 250 to 300 mJ / cm ² . In this case, the laser is irradiated also on the boundary between the impurity region and the offset region, which is effective in preventing deterioration at the boundary.

Next, 300-45 in a chlorine atmosphere.
A chlorination treatment was performed by performing thermal annealing at 0 ° C.
By performing this chlorination treatment, Cl ^- was taken into the gate insulating film. At this time, in the offset region, which was substantially an intrinsic silicon film, holes were drawn near the surface by Cl ⁻ taken into the gate insulating film, and a weak P-type region 110 was formed. As a result, the weak P-type region 110 has the same effect as that of the low-concentration P-type impurity doping.
D region was formed. (FIG. 1 (E))

Next, a 5000-nm-thick silicon oxide film was formed as an interlayer insulating film 111 on the entire surface by a plasma CVD method. Then, the interlayer insulating film 111 and the gate insulating film 10
4 was etched to form contact holes in the source / drain regions. Thereafter, an aluminum film of 3000 to 2 μm, preferably 4000 to 8000 °, for example, 5000 ° was formed by a sputtering method.
Then, the aluminum film is etched and the source /
P-channel type TF having a weak P-type region for forming drain electrode 112 and obtaining substantially the same effect as LDD
T was obtained. (FIG. 1 (F)) As is clear from the drawing, the TFT of this embodiment has a very simple structure. However, it exhibited substantially the same characteristics as those of a TFT having an LDD.

Embodiment 2 FIG. 2 shows this embodiment. In the present embodiment, hydrogenation treatment of the active layer and chlorination treatment of the gate insulating film are simultaneously performed, and silicon nitride is used as an interlayer insulating film so that Cl ⁻ taken in the gate insulating film does not diffuse into the interlayer insulating film. It uses a membrane. First, the substrate 20
1 (Corning 7059), a 4000-nm-thick silicon oxide film was formed as a base oxide film 202 by a sputtering method in an oxygen atmosphere.

After that, an amorphous silicon film is deposited at a thickness of 800 ° by a plasma CVD method or an LPCVD method.
It was left in a reducing atmosphere at 0 to 600 ° C. for 8 to 24 hours to be crystallized. In this case, crystallization may be promoted by adding a trace amount of a catalyst element such as nickel which promotes crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was etched to form an island-like silicon film 203. further,
A gate insulating film 204 was formed thereon. Here, a silicon oxide film having a thickness of 1500 ° was formed by a plasma CVD method. (Fig. 2 (A))

Thereafter, an aluminum film having a thickness of 1000 to 3 μm, for example, 5000 ° was formed by a sputtering method. Then, a thin anodic oxide film having a thickness of 100 to 400 ° was formed on the surface of the aluminum film. Thereafter, a photoresist having a thickness of about 1 μm was formed on the thus treated aluminum film by spin coating. Then, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a gate electrode 205. Here, the gate electrode 205
Above there is a photoresist mask 206.
(FIG. 2 (B))

Next, the substrate is immersed in a 10% oxalic acid solution,
By performing anodization at a constant voltage of 10 V for 120 minutes, a porous anodic oxide 207 having a thickness of about 8000 mm is formed.
Was formed on the side surface of the gate electrode 205. Gate electrode 20
Since the photoresist mask 206 was present on the upper surface of No. 5, anodic oxidation hardly proceeded. next,
The mask material 206 is removed, the upper surface of the gate electrode 205 is exposed, and the substrate is immersed in an ethylene glycol solution of 3% tartaric acid (neutral pH adjusted with ammonia). Apply voltage in the state,
The voltage was increased to 100 V to perform anodic oxidation.
At this time, not only the top surface of the gate electrode but also the side surfaces of the gate electrode are anodized, so that a dense nonporous anodic oxide 208 is formed.
Was formed to a thickness of 1500 °. (Fig. 2 (C))

Thereafter, boron is implanted as an impurity into the island-shaped silicon film 203 in a self-aligned manner by using the gate electrode portion (gate electrode and surrounding anodic oxide) as a mask, thereby forming the P-type impurity region 209. Formed.
Here, the dose was 5 × 10 ¹⁵ atoms / cm ² and the acceleration voltage was 65 kV. (FIG. 2D) Then, the porous anodic oxide 207 was etched with a phosphoric acid-based etchant to expose the nonporous anodic oxide 208. At this time, since the lower portion of the portion where the porous anodic oxide 207 was present was not doped with boron, an offset region was formed.

Thereafter, a KrF excimer laser (wavelength 2
Irradiation of 48 nm and a pulse width of 20 nsec) was performed to activate the doped impurity region. The energy density of the laser was suitably from 250 to 300 mJ / cm ² . In this case, the laser is irradiated also on the boundary between the impurity region and the offset region, which is effective in preventing deterioration at the boundary.

Next, thermal annealing at 300 to 450 ° C. was performed in a mixed gas atmosphere of chlorine and hydrogen to simultaneously perform chlorination of the gate insulating film and hydrogenation of the active layer. By performing this chlorination treatment, Cl ⁻ was taken into the gate insulating film 204. In addition, the characteristics of the active layer were improved by the hydrogenation treatment. At this time, in the offset region which was substantially an intrinsic silicon film,
Due to Cl ⁻ taken into the gate insulating film 204,
Holes are drawn near the surface, and the weak P-type region 21 is formed.
0 was formed. As a result, in the weak P-type region 210, an effect similar to that obtained by doping a low-concentration P-type impurity was obtained, and a substantial LDD region was formed.
(FIG. 2 (E))

Next, a silicon nitride film 211 having a thickness of 300 to 1500.degree., For example, 500.degree. Further, a silicon oxide film having a thickness of 50
00 ° was formed. The silicon nitride film 211 is a gate insulating film 2
Cl was incorporated into 04 ^- is detached by the external environment such as heat and humidity, it was effective in preventing diffusion. Then, the silicon nitride film 211, the interlayer insulating film 212, and the gate insulating film 204 were etched to form contact holes in the source / drain regions. Thereafter, a 6000 ° aluminum film was formed by a sputtering method. Then, the aluminum film was etched to form the source / drain electrodes 213, and a P-channel TFT having a weak P-type region capable of substantially obtaining the same effect as the LDD was obtained. (FIG. 2 (F))

[Embodiment 3] FIG. 3 shows this embodiment. The present embodiment relates to a CMOS circuit constituted by a P-channel TFT having a substantial LDD and an N-channel TFT having no LDD according to the present invention. First, a 4000-nm-thick silicon oxide film was formed as a base oxide film 302 on a substrate 301 of Corning 7059 by a plasma CVD method.

Further, an amorphous silicon film was deposited at 500 ° by a plasma CVD method, and was left in a reducing atmosphere at 550 to 600 ° C. for 8 to 24 hours to be crystallized. In this case, crystallization may be promoted by adding a trace amount of a catalyst element such as nickel which promotes crystallization. After crystallization, the silicon film was irradiated with KrF excimer laser light to further improve the crystallinity. The substrate temperature during laser irradiation is 150-250 ° C, and the energy density is 150
３５０350 mJ / cm ² was a preferable condition. Then, the silicon film crystallized in this manner was etched to form island-like silicon films 303 and 304. Further, a gate insulating film 305 was formed thereon. Here, the plasma C
A silicon oxide film having a thickness of 1000 ° was formed by the VD method. (FIG. 3 (A))

Thereafter, an aluminum film having a thickness of 6000 ° was formed by a sputtering method. Then, anodic oxidation was performed by the same means as in Example 1. That is, first, only the gate electrode 307 of the P-channel TFT is anodized to form the porous anodic oxide 30.
8 (1.5 μm width). Next, the P-channel type T
The FT gate electrode 307 and the N-channel TFT gate electrode 306 were anodized to form dense, nonporous anodic oxides 309 and 310 to a thickness of 1000 °. (FIG. 3
(B))

Thereafter, impurities were implanted into the island-like silicon films 303 and 304 in a self-aligned manner by ion doping using the gate electrode portions (gate electrode and surrounding anodic oxide) as a mask. First, a region where a P-channel TFT was to be formed was covered with a photoresist mask 311 and phosphorus was implanted to form an N-type impurity region 312. Here, the dose was 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , the acceleration voltage was 60 to 90 kV, for example, the dose was 5 × 10 ¹⁴ atoms / cm ² and the acceleration voltage was 80 kV. (FIG. 3 (C))

Thereafter, the region for forming the N-channel TFT was covered with a photoresist mask 313, and boron was implanted into the region for forming the P-channel TFT to form a P-type impurity region 314. Here, the dose amount is 1 × 10
¹³ to 8 × 10 ¹⁵ atoms / cm ^2, the accelerating voltage is 40~80k
V, for example, the dose was 3 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 65 kV. (FIG. 3D) Then, the porous anodic oxide 308 was etched with a phosphoric acid-based etchant to expose the non-porous anodic oxide 310.

Thereafter, a KrF excimer laser (wavelength 2
Irradiation of 48 nm and a pulse width of 20 nsec) was performed to activate the doped impurity region. The energy density of the laser was suitably from 250 to 350 mJ / cm ² . Next, fluorine was implanted into the gate insulating film by an ion doping method. At this time, the dose amount is 1 ×
10 ¹² to 1 × 10 ¹⁵ atoms / cm ² , for example, 5 × 10 ¹³
Atoms / cm ² , and the acceleration voltage was 30 kV. As a result,
F ⁻ was introduced into the gate insulating film 305. At this time,
In the offset region, which was a substantially intrinsic silicon film, holes were drawn near the surface by F ⁻ taken into the gate insulating film 305, and a weak P-type region 315 was formed. As a result, this weak P-type region 31
In No. 5, the same effect as that obtained by doping with a low concentration of P-type impurity was obtained, and a substantial LDD region was formed. In this doping step, almost no fluorine was injected into the active layer, so that the crystallinity of the active layer hardly changed before and after doping. (FIG. 3
(E))

Next, a 5000-nm-thick silicon oxide film was formed on the entire surface as an interlayer insulating film 316 by a plasma CVD method. Then, the interlayer insulating film 316 and the gate insulating film 30
5 was etched to form contact holes in the source / drain regions. Thereafter, a 5000 ° aluminum film was formed by a sputtering method, and this was etched to form source / drain electrodes 317. Through the above steps, a CMOS-type circuit including a P-channel TFT having a weak P-type region and an N-channel TFT having no LDD and having substantially the same effect as the LDD was obtained. (FIG. 3 (F))

[Embodiment 4] FIG. 4 shows this embodiment. The present embodiment relates to a method of manufacturing an active matrix liquid crystal display, and more particularly to a monolithic active matrix circuit in which an active matrix circuit and a peripheral driving circuit for driving the same are formed on the same substrate.
P-channel TF with substantial LDD according to the present invention
T is used as a switching transistor of a pixel circuit (active matrix circuit), and N-channel and P-channel TFTs having no LDD are used as peripheral driving circuits.

First, a silicon oxide film having a thickness of 4000.degree.
0 ° amorphous silicon film is deposited, and
The mixture was left in a reducing atmosphere at 8 ° C. for 8 to 24 hours to be crystallized. Then, the silicon film crystallized in this manner was etched to form island-like silicon films 403, 404, and 405.
Further, a gate insulating film 406 of silicon oxide (thickness: 1200 °) was formed thereon. (FIG. 4 (A))

Thereafter, an aluminum film having a thickness of 6000 ° was formed by a sputtering method. Then, a thin anodic oxide film having a thickness of 100 to 400 ° was formed on the surface of the aluminum film. Thereafter, anodic oxidation was performed in the same manner as in Examples 1 and 3. That is, first, the gate electrode 409 of the TFT constituting the pixel circuit was anodized, and a porous anodic oxide 410 having a width of 1 μm was formed on the side surface of the gate electrode 409. Next, the gate electrode 409 of the TFT constituting the pixel circuit and the gate electrodes 407 and 408 of the TFT constituting the peripheral driving circuit are anodized to form a dense nonporous anodic oxide 411, 41 having a thickness of 1500 °.
2, 413 were formed. (FIG. 4 (B))

Thereafter, impurities were implanted into the island-like silicon films 403, 404, and 405 in a self-aligned manner by ion doping using the gate electrode portion (gate electrode and surrounding anodic oxide) as a mask. First, a region where a P-channel TFT was to be formed was covered with a photoresist mask 414, and phosphorus was implanted to form an N-type impurity region 415. Here, the dose amount is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / c.
m ² , the acceleration voltage was 60 to 90 kV, for example, the dose was 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage was 80 kV.
(FIG. 4 (C))

Thereafter, the region for forming the N-channel TFT was covered with a photoresist mask 416, and boron was implanted into the region for forming the P-channel TFT to form P-type impurity regions 417 and 418. Here, the dose is 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 40.
８０80 kV, for example, a dose of 1 × 10 ¹⁵ atoms / cm
^{2. The} acceleration voltage was set to 65 kV. (FIG. 4 (D))

Then, the porous anodic oxide 410 was etched with a phosphoric acid-based etchant to expose the non-porous anodic oxide 413. Thereafter, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was performed to activate the doped impurity region. Laser energy density is 250-350mJ /
cm ² was adequate. Next, plasma treatment of chlorine and hydrogen was performed to introduce chlorine and hydrogen into the gate insulating film 406. That is, the substrate was placed on one electrode of a parallel plate type device provided in a reduced-pressure atmosphere of chlorine and hydrogen to generate RF plasma (excitation frequency 13.56 MHz). During the plasma treatment, the substrate may be heated to 120 to 450 ° C. By performing this process,
Cl ⁻ was introduced into the gate insulating film 406.

The degree to which chlorine enters the silicon oxide film when the above-described plasma treatment is performed on the crystalline silicon film and the gate insulating film (silicon oxide) formed under the same conditions as in this embodiment. That secondary ion mass spectrometry (SI
MS). FIG. 6 shows the result. Here, plasma treatment was performed for one hour. The ratio of chlorine to hydrogen is 1: 1 and the total pressure is 4 Pa, 13.56 MHz
Of 150 W was supplied. As is clear from the obtained SIMS data, it can be seen that 1 × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ of chlorine was introduced into the film.

In an actual TFT, the same amount of chlorine was introduced into the gate insulating film 406 as chlorine ions (Cl ⁻ ).
Then, in the offset region which was a substantially intrinsic silicon film, Cl ⁻ taken into gate insulating film 406.
The hole is drawn near the surface by the weak P
A mold region 419 was formed. As a result, in this weak P-type region, the same effect as that obtained by doping a low-concentration P-type impurity was obtained, and a substantial LDD region was formed. At the same time, hydrogen was introduced, but the hydrogen ions
l ^- because ionic radius than small and penetrate the active layer. (FIG. 4E) Next, a first interlayer insulating film 42 is formed on the entire surface.
0, a 5000 nm thick silicon nitride film is formed by a plasma CVD method, and an interlayer insulating film 420 and a gate insulating film 4 are formed.
06 was etched to form contact holes in the source / drain regions.

Thereafter, a 5000 ° aluminum film was formed by sputtering, and the aluminum film was etched to form source / drain electrodes 421. Through the above steps, a peripheral drive circuit region was formed. (FIG. 4F) Further, plasma CVD is used as the second interlayer insulating film 422.
A silicon oxide film having a thickness of 3000 .ANG. Was formed by the method, and the interlayer insulating film 420 and the gate insulating film 406 were etched to form contact holes. Thereafter, a 500 ° ITO (indium tin oxide) film was formed by a sputtering method, and the ITO film was etched to form a pixel electrode 423. (Fig. 4 (G))

Through the above steps, a pixel circuit is formed using a P-channel type TFT having a weak P-type region which can provide substantially the same effect as the LDD, which is a pixel circuit, and a monolithic active matrix circuit is obtained. I was able to. FIG. 7 shows the drain current (I _D ), field-effect mobility (μ _FE ), and gate-source leakage current (I _G ) of the TFT (channel length: 10 μm, channel width 5 μm) manufactured by the above steps. Shows the gate voltage (V _G ) dependency. I _D, μ _FE, I _G is the drain voltage (V _D) -
The values at 1 V and -14 V are also shown. As is clear from FIG. 7, the off-state current was reduced. On the other hand, the mobility was 100 to 110 cm ² / Vs at the maximum, and a high level could be maintained.

[0053]

According to the present invention, the LDD has a very simple structure, and the LDD can be substantially eliminated by performing the P-type or N-type impurity doping step on the active layer substantially once.
Thus, a TFT having a weak positive or negative channel region capable of obtaining the same effect as described above could be formed. In the example,
The manufacturing process of the P-channel TFT has been described.
It will be apparent that the same can be applied to a channel type TFT. According to the present invention, a TFT having a substantial LDD can be easily formed, and the throughput has been improved. In the present invention, in addition to the reduction in the number of steps, the production yield has been improved because low concentration doping, which was conventionally required and extremely technically difficult, has become unnecessary. Thus, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 shows the steps of Example 1.

FIG. 2 shows the steps of Example 2.

FIG. 3 shows a process of Example 3.

FIG. 4 shows the steps of Example 4.

FIG. 5 shows the configuration and principle of the present invention.

FIG. 6 shows how chlorine is added to a gate insulating film in Example 4.

FIG. 7 shows characteristics of the TFT obtained in Example 4.

[Explanation of symbols]

 101, substrate 102, base oxide film 103, island-shaped silicon film 104, gate insulating film 105, gate electrode 106, photoresist mask 107, ··· Porous anodic oxide 108 ··· Non-porous anodic oxide 109 ··· P-type impurity region 110 ··· Weak P-type region 111 ··· Interlayer insulating film 112 ··· .Source / drain electrodes

Claims (10)

(57) [Claims] A channel forming region and a pair of P-type impurities
An active layer including a target region, a gate insulating film provided on the active layer, and a gate electrode provided on the gate insulating film, wherein the channel forming region and at least one of the impurity regions are provided.
Charge-induced drain region is provided between the band, negative in the gate insulating film except for the lower portion of the gate electrode
A semiconductor device comprising a fixed charge of ions . 2. The method according to claim 1, wherein the negative ion is Cl.
^- or F ^- and wherein a is. 3. A channel forming region and a pair of N-type impurities.
An active layer including a target region, a gate insulating film provided on the active layer, and a gate electrode provided on the gate insulating film, wherein the channel forming region and at least one of the impurity regions are provided.
A charge-induced drain region is provided between the regions , and a positive electrode is formed in the gate insulating film except for a portion below the gate electrode.
A semiconductor device comprising a fixed charge of ions . 4. The method according to claim 1, wherein:
Wherein the semiconductor device is used as a switching transistor of an active matrix circuit. 5. A method according to claim 1 , wherein a gate insulating film is provided on the semiconductor layer , a gate electrode is provided on the gate insulating film , an oxide is provided on a side surface of the gate electrode, and the oxide and the gate electrode are used as masks.
A method for manufacturing a semiconductor device , comprising: introducing a P-type impurity into a semiconductor layer in a self-aligning manner ; selectively removing the oxide; and introducing fixed negative ions into the gate insulating film . 6. The method according to claim 5, wherein said negative ion is Cl.
^- or F ^- The method for manufacturing a semiconductor device which is a. 7. A gate insulating film is provided on a semiconductor layer , a gate electrode is provided on the gate insulating film , an oxide is provided on a side surface of the gate electrode, and the oxide and the gate electrode are used as masks.
A method for manufacturing a semiconductor device , comprising: introducing an N-type impurity into a semiconductor layer in a self-aligned manner ; selectively removing the oxide; and introducing fixed charges of positive ions into the gate insulating film . 8. The method according to claim 5, wherein :
Te, wherein the said introduction into the gate insulating film fixed charge, a method for manufacturing a semiconductor device which is characterized in that the plasma discharge. 9. The method according to claim 5, wherein :
The method of manufacturing a semiconductor device , wherein the fixed charges are introduced into the gate insulating film by an ion implantation method. 10. The method according to claim 5, wherein :
The method for manufacturing a semiconductor device , wherein the fixed charges are introduced into the gate insulating film by performing heat treatment in a gas atmosphere in which fixed charges are generated.