JPH09237898A - Polycrystal semiconductor tft, manufacture thereof and tft substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase in the manufacturing cost by thinning the extended part of the value of the specific range of a gate insulating film pattern without masking with a gate electrode pattern, and thinning ion impurity. SOLUTION: The gate pattern 5 of Cr to become a gate electrode is formed by photolithography. After a gate insulating film is etched without releasing photoresist, a substrate is again dipped in etchant of Cr, and etching is proceeded from the side of the pattern 5. The end face of the pattern 5 is formed 0.1 to 2.0μm at the inside from the gate insulating film. After the photoresist on the Cr is removed, photoresist is deposited as the mask layer 6 covering the part to become n-channel TFT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline semiconductor TFT used for driving an image display device, a method for manufacturing the same, and a TFT substrate.

[0002]

2. Description of the Related Art In recent years, a thin film transistor (TFT) or the like has been used as a driving element for each pixel in a liquid crystal display element which provides a high quality image display. In particular, polycrystalline silicon thin film transistors have been actively developed.
Since the polycrystalline silicon TFT has a larger current supply capability than the amorphous silicon TFT, not only the driving of the liquid crystal of each pixel of the liquid crystal display element but also the driving circuit of the scanning line and the signal line can be formed on the same substrate. Have advantages. When a polycrystalline silicon TFT is used as a pixel driving element, it is necessary to suppress off-current, and a gate offset structure is often used.

A method of forming a gate electrode, a gate offset, and a source / drain region in a self-aligned manner in order to form a fine gate offset uniformly in a plane of a substrate with good reproducibility is disclosed in Japanese Patent Laid-Open No. 5-47791. Example 1). With reference to FIG. 3, a polycrystalline semiconductor TF formed by polycrystallizing an amorphous semiconductor by using laser light is formed.
T will be described below.

A passivation film 2 and an amorphous semiconductor layer are laminated on a substrate 1, polycrystallized by laser light irradiation, and a pattern of the polycrystalline semiconductor thin film 3 is formed by photolithography. A gate insulating film 4 and a gate electrode material are laminated thereon, and a gate electrode pattern 5 is formed again by photolithography. After that, the gate insulating film is etched without peeling off the photoresist, and the etching is further advanced from the side surface of the gate electrode.
The end face of the gate electrode is formed inside the gate insulating film of 0.1 to 2.0 μm.

Impurity ions are doped into the polycrystalline semiconductor layer using the gate electrode as a mask by the ion implantation method, and heat treatment for activating the impurity ions is performed to form the source / drain regions 7. Further, an interlayer insulating film is deposited, ITO of the pixel electrode is formed and patterned, contact holes are formed on the source / drain regions, and source / drain electrodes are formed thereon. Forming a protective film SiN _x ,
I opened the window.

Further, as a structure of a TFT, a structure in which a low impurity concentration region is formed between a channel region and a source / drain region is known. Technical report (TECHNICA)
LREPORT OF IEICE, EID94-14
2, ED94-170, SDM94-199 (1995
-02)) 43 to 48), there is a disclosure about the characteristics of a polycrystalline silicon semiconductor having an LDD structure formed by using an ion implantation method (Prior art example 2).

However, there is no particular description in the conventional example 2 that laser annealing is used to form a polycrystalline semiconductor, and TF is used.
There is no mention of controlling the thickness of the gate insulating film in the T offset structure.

[0008]

Since the gate offset structure of the TFT reduces the ON current, it is not suitable for the TFT for the peripheral drive circuit. Particularly in the case of a p-channel TFT having a low field effect mobility, the resistance of the offset portion is large and the on-current is significantly reduced.

In the above-mentioned prior art gate offset structure, the acceleration voltage at the time of ion implantation should be sufficiently high,
By thinning the gate insulating film, a small amount of impurity ions are also implanted through the gate insulating film into the semiconductor layer in the gate offset portion during ion implantation in the source / drain regions. Then, by forming a so-called LDD structure, it is possible to prevent a decrease in the on-current of the TFT.

However, if the acceleration voltage during ion implantation is increased, the temperature rise of the substrate during ion implantation will increase. Therefore, when a CMOS circuit is formed by TFTs, the mask (photoresist layer) at the time of ion implantation for forming the n-channel TFT and the p-channel TFT is altered by heat, and cracks are generated or peeling becomes difficult. I have a problem. Moreover, the ion implantation device for a TFT substrate with a high acceleration voltage becomes extremely large and expensive.
Increases the manufacturing cost of the substrate.

In the manufacturing method in which the ion implantation is performed through the thinned gate insulating film, there is a limit to the ion implantation at a high acceleration voltage. That is, even in the case of implanting boron ions having the smallest mass number among the substances generally used as impurity ions in the semiconductor manufacturing technology, the acceleration voltage must be suitable for the heat resistance of the photoresist. There is a limit in using a high accelerating voltage due to the manufacturing apparatus, material, manufacturing temperature, etc., and there is a problem in reducing the thickness of the gate insulating film in terms of the element structure.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a gate insulating film is formed by sequentially forming three material layers of a semiconductor layer, a gate insulating film and a gate electrode on a substrate. An end face of the gate electrode pattern is formed 0.1 to 2.0 μm inward of the pattern, and impurity ions are implanted into the semiconductor layer using the gate electrode pattern and the gate insulating film pattern as a mask to form a channel region and a source / source region of the semiconductor layer.
In a method of manufacturing a polycrystalline semiconductor TFT in which a low impurity concentration region is formed between a gate electrode pattern and a gate insulating film pattern,
Provided is a method for manufacturing a polycrystalline semiconductor TFT, characterized in that a protruding portion of 2.0 μm is thinned and impurity ions are injected into a semiconductor layer through a thinned gate insulating film pattern.

Further, the thickness of the material layer of the gate insulating film is 12
Provided is a method for manufacturing the above-mentioned polycrystalline semiconductor TFT in which the thickness of the thinned portion of the gate insulating film pattern is 0 to 150 nm, the thickness of the gate insulating film pattern is 80 to 100 nm, and impurity ions containing boron atoms are implanted at an acceleration voltage of 15 to 25 kV. .

Also provided is a method for manufacturing a polycrystalline semiconductor TFT as described above, wherein both a polycrystalline semiconductor TFT having a low impurity concentration region and a polycrystalline semiconductor TFT having no low impurity concentration region are formed on a substrate.

Further, there is provided a method for manufacturing the above-mentioned polycrystalline semiconductor TFT, in which the gate insulating film pattern is thinned by using the photoresist pattern as a mask.

Further, in a polycrystalline semiconductor TFT having a polycrystalline semiconductor layer, a gate insulating film and a gate electrode on a substrate and having a low impurity concentration region between a channel region and a source / drain region of the polycrystalline semiconductor layer, Provided is a polycrystalline semiconductor TFT, wherein a thickness of a gate insulating film in an offset portion not covered with a gate electrode is 20 to 70 nm thinner than that in a non-offset portion of a channel.

The polycrystalline semiconductor T described above has a gate insulating film having a thickness of 80 to 100 nm in the offset portion and a gate insulating film having a thickness of 120 to 150 nm in the channel portion.
Provide FT.

Also provided is the above-mentioned polycrystalline semiconductor TFT having a channel length of 3 to 10 μm.

Also provided is the above-mentioned polycrystalline semiconductor TFT in which a polycrystalline semiconductor is formed by laser annealing.

A polycrystalline semiconductor TFT having no low impurity concentration region between the semiconductor layer and the source / drain regions
And a polycrystalline semiconductor TFT described above are provided.

[0021]

Even in the conventional TFT offset structure, a small amount of impurity ions are implanted into the semiconductor layer in the gate offset portion through the gate insulating film by increasing the acceleration voltage during ion implantation, LD of TFT
A D structure was obtained. With this configuration, it is possible to prevent the on-current of the TFT from decreasing.

For example, when boron ions are implanted to form a p-channel TFT, the gate insulating film SiO
_With the accelerating voltage of about 30 kV with respect to 120 nm of the _two films, it is possible to dope the source / drain and simultaneously implant a necessary and sufficient amount of boron ions into the semiconductor layer in the offset portion.

However, if an attempt is made to form a TFT CMOS circuit under these manufacturing conditions, as described above, the n-channel TF is used.
The photoresist masking T is deteriorated by heat,
Problems such as cracking and difficulty in peeling occur. As described above, it has been experimentally found that the acceleration voltage that the photoresist can withstand is up to about 25 kV.

On the contrary, in order to implant a necessary and sufficient amount of boron ions into the semiconductor layer in the offset portion at the same time as doping the source / drain at an acceleration voltage of 20 kV, the thickness of the gate insulating film in the offset portion is set to 100 nm or less. .
When the gate insulating film is thin, the breakdown voltage becomes low, and it becomes difficult to control the formation of the low impurity region during ion implantation. Therefore, the thickness is preferably 80 to 90 nm.

Regarding the size of the TFT, the shorter the channel length, for example, 20 μm or less, the larger the effect is.
The range of 10 μm is preferable. With respect to the offset length, it is preferable that the ON current is substantially constant in the range of 0.2 to 1.0 μm and the manufacturing process margin is wide.

In the case of the LDD structure, the correlation with the offset length is slightly lowered to about 15V. The variation can be suppressed within a certain range. TN liquid crystal and liquid crystal /
It is possible to drive a polymer composite type element. Also, LDD
In the structure, when the metal light-shielding film is provided in the lower layer of the TFT, there is an advantage that the off breakdown voltage is less likely to decrease due to the influence of the light-shielding film potential.

The etching for thinning the gate insulating film in the offset portion may be performed after the gate electrode and the gate offset structure are formed and before the ion implantation, but the film thickness of other films can be reduced by minimizing the etching amount. It is necessary to suppress the decrease and the formation of overhangs under the gate electrode.

The lower the accelerating voltage for ion implantation, the lower the manufacturing cost and the less damage to the photoresist or the like used for the mask. However, as described above, there is a limit to the thinning of the gate insulating film in the offset portion, so it is 15 to 25 k.
About V is necessary.

The etching for thinning the gate insulating film at the offset portion may be performed on the entire surface of the substrate, or may be performed only on the p-channel TFT using a photoresist masking the n-channel TFT. If necessary, a TFT having an offset structure may be formed separately on the same substrate surface by using a dedicated mask.

The case of forming a p-channel TFT and a CMOS circuit using boron ion implantation has been described above. However, the present invention can be applied to other implanted ion species and other film configurations, and source / drain. The conditions for simultaneous implantation of the region and the offset portion can be optimized. Since the low-concentration implantation into the offset portion uses the region in which the impurity concentration in the depth direction changes exponentially, even a slight reduction in the thickness of the gate insulating film is effective. Next, an embodiment of the present invention will be described with reference to FIG.

[0031]

【Example】

(Example 1) forming the base film 2 of SiO ₂ in 200nm thickness by the plasma CVD method on a glass substrate 1, 100n
An m-thick a-Si layer 3 was formed at a substrate temperature of 300 ° C., and then a 50 nm thick SiN _x antireflection film was formed at 350 ° C. 8 W of argon ion laser light was condensed to a diameter of about 100 μm, and scanning irradiation was performed at a linear velocity of 13 m / s to polycrystallize the a-Si layer 3. The polycrystallization process was completed in about 2 minutes.

After removing the antireflection film by etching, the polycrystalline Si is patterned into an island shape by photolithography, and SiO ₂ of 120 is formed thereon by plasma CVD.
A gate insulating film 4 having a thickness of 150 nm was deposited at 350 ° C., and Cr 150 nm was formed as a gate electrode material at 300 ° C. by a sputtering method.

A Cr gate pattern 5 serving as a gate electrode was formed by photolithography. After etching the gate insulating film without peeling off the photoresist,
The substrate was again immersed in a Cr etching solution, and etching was advanced from the side surface of the gate pattern 5 to form the end surface of the gate pattern 5 by 0.7 ± 0.1 μm inside the gate insulating film.

After removing the photoresist on Cr, n
Photoresist was deposited as a mask layer 6 covering the part of the channel to be the TFT. As the photoresist, OFPR-800 manufactured by Tokyo Ohka was used. Here, the substrate was immersed in a 0.5% hydrofluoric acid aqueous solution for 2 minutes, and the gate insulating film protruding by about 0.7 μm from the end face of the gate pattern 5 was thinned by etching to a thickness of about 90 nm.

Next, the Cr of the gate pattern 5 is formed by the ion shower method (ion implantation method of irradiating the substrate with a large-area surface beam without mass separation from the ion source) using 10% B ₂ H ₆ gas diluted with hydrogen as a source gas. With the mask as a mask, H _x , BH _x ,
B ₂ H _x ions are accelerated at a voltage of 20 kV and a dose of 1 × 10
Doping was performed under the condition of ¹⁶ / cm ² .

Although the gate pattern 5 is used as a mask,
Since the gate insulating film protruding from the end face of the gate pattern 5 is thinned, a small amount of B atoms is also doped into the polycrystalline semiconductor layer 8 below this, and the electrical resistance is lowered to form the LDD structure. A TFT could be formed.

After removing the mask layer 6, hydrogen diluted with 5% P
Doping was performed by an ion shower method using H ₃ gas as a source gas under the conditions of an acceleration voltage of 5 kV and a dose amount of 1 × 10 ¹⁵ pieces / cm ² , and heat treatment for activating impurity ions was performed. Further, SiN _x was deposited as an interlayer insulating film, ITO of the pixel electrode was formed and patterned, contact holes were formed on the source / drain regions, and source / drain were formed thereon. A protective film SiN _x was formed, a window was opened, and then heat treatment was performed to measure TFT characteristics.

FIG. 2 is a graph showing the dependence of the field effect mobility of the p-channel polycrystalline Si TFT formed by the manufacturing method of the present invention and the conventional manufacturing method on the channel length L. In the conventional TFT having the offset structure (reference numeral 10), since the resistance of the offset portion is large, when L is small, the resistance of the offset portion becomes dominant and the effective mobility is significantly reduced.

On the other hand, the TFT (reference numeral 20) formed according to the present invention has a small dependence on the channel length L, and thus TF
A large mobility was obtained as T. It was found that the resistance at the offset portion of the TFT was sufficiently reduced.

According to the present invention, it is possible to obtain a T having extremely high characteristics by adding an etching step once from the conventional manufacturing method.
The FT could be uniformly and stably formed within the same TFT substrate.

(Example 2) In the same manner as in Example 1, a TFT substrate in which row driving circuits were integrated on the same substrate surface was formed. The diagonal length is 9.1 cm, the number of pixels is 384 × 288, and the row drive circuit includes a static register with a redundant circuit and a current amplification unit, and the row direction is 55 mm × the column direction is 3.5 mm.
It was possible to fit within the area. The prior art required a width of 6 mm in the column direction. This row drive circuit has a diagonal length of 31 cm (the number of pixels of an engineering workstation for displaying high density information, for example, 1024 × 128).
It was confirmed by experiments that drive circuits in display devices up to 0) can be formed. The field effect mobility of the formed TFT is n channel 15 cm ² / V · S, p channel T
The FT was 20 cm ² / V · S.

A color liquid crystal display device was formed using this TFT substrate. A drive circuit which was conventionally attached externally can be formed on the same substrate, and a high-performance compact color liquid crystal display device has been obtained with high productivity and efficiency. We were able to display full-color, high-density, high-speed video movies.

Further, in the case of forming the CMOS circuit of the TFT according to the present invention, even if the masking of the n-channel TFT is carried out by the photoresist and the doping of boron of the p-channel TFT is carried out at a low acceleration voltage, the p-channel T of the LDD structure is formed.
An FT can be formed and a CMOS circuit-embedded TFT substrate can be realized by a low-cost process.

That is, according to the present invention, an n-channel TFT having an offset structure and an LDD type p-type on the same substrate.
A high-performance CMOS circuit could be formed by forming both channel TFTs. As the TFT in the pixel region, either a p-channel TFT or an n-channel TFT could be used. In this case, either one can be selected according to the specifications, but for the purpose of high-speed display, the p-channel which exhibits high mobility is advantageous.

[0045]

According to the present invention, a high-performance polycrystalline semiconductor TFT can be obtained without complicating the manufacturing process. It is possible to appropriately build a circuit according to the specification requirements of each circuit within the substrate surface of the TFT, and an extremely high-performance display device as a whole can be obtained.

In particular, a p-channel TFT, which has not been able to obtain a high mobility conventionally, has a stable mobility of 20 cm.
High-temperature polycrystal TF because it can obtain elements of ² / V · S or higher.
An element design equal to or higher than that of T can be made, and a polycrystalline semiconductor TFT can be manufactured stably at low cost. In addition, a polycrystalline semiconductor TFT that operates stably in a wide temperature range (-10 to 80 ° C) can be obtained as a use environment condition.

By making it possible to form a p-channel TFT having a mobility higher than that of an n-channel TFT, especially in the case of forming a CMOS circuit, the overall operation characteristics thereof can be freely adjusted and a well-balanced circuit can be obtained. Configuration can be adopted.

Moreover, the degree of freedom in design is improved, and desired performance of the TFT liquid crystal panel can be obtained. The present invention can be applied to other devices as long as the effect is not impaired.

[Brief description of drawings]

FIG. 1 is a schematic view showing one step of a method for manufacturing a polycrystalline semiconductor TFT of the present invention.

FIG. 2 is a p-channel polycrystalline Si TFT of the present invention and a conventional example.
FIG. 6 is a characteristic diagram showing the dependence of the field-effect mobility on the channel length L.

FIG. 3 is a cross-sectional view of a conventional polycrystalline semiconductor TFT.

[Explanation of symbols]

1: Substrate 2: SiO ₂ film 3: Semiconductor layer 4: Gate insulating film 5: Gate electrode pattern

Claims (9)

[Claims] 1. A semiconductor layer, a gate insulating film, and three material layers of a gate electrode are sequentially formed on a substrate, and an end face of the gate electrode pattern is formed 0.1 to 2.0 μm inside the gate insulating film pattern. A polycrystalline semiconductor TFT in which impurity ions are implanted into a semiconductor layer by using a gate electrode pattern and a gate insulating film pattern as a mask to form a low impurity concentration region between a channel region and a source / drain region of the semiconductor layer.
In the method for manufacturing the same, the 0.1 to 2.0 μm protruding portion of the gate insulating film pattern not masked by the gate electrode pattern is thinned, and impurity ions are injected into the semiconductor layer through the thinned gate insulating film pattern. A method for manufacturing a characteristic polycrystalline semiconductor TFT. 2. The thickness of the material layer of the gate insulating film is 120 to 1
The method for producing a polycrystalline semiconductor TFT according to claim 1, wherein the thickness of the thinned portion of the gate insulating film pattern is 50 nm, the thickness is 80 to 100 nm, and the impurity ions containing boron atoms are implanted at an acceleration voltage of 15 to 25 kV. 3. The method for producing a polycrystalline semiconductor TFT according to claim 1, wherein both a polycrystalline semiconductor TFT having a low impurity concentration region and a polycrystalline semiconductor TFT not having a low impurity concentration region are formed on a substrate. . 4. The method for producing a polycrystalline semiconductor TFT according to claim 1, 2 or 3, wherein the gate insulating film pattern is thinned using the photoresist pattern as a mask. 5. A polycrystalline semiconductor layer, a gate insulating film, and
In a polycrystalline semiconductor TFT having a gate electrode and a low impurity concentration region between a channel region and a source / drain region of the polycrystalline semiconductor layer, the thickness of the gate insulating film at the offset portion not covered by the gate electrode is 20 to 7 more than the non-offset part of
A polycrystalline semiconductor TFT characterized by being provided with a thickness of 0 nm. 6. The thickness of the gate insulating film at the offset portion is 8
The polycrystalline semiconductor TF according to claim 5, wherein the gate insulating film in the channel portion has a thickness of 0 to 100 nm and a thickness of 120 to 150 nm.
T. 7. The channel length is 3 to 10 μm.
Or a polycrystalline semiconductor TFT of 6. 8. The polycrystalline semiconductor TF according to claim 5, 6 or 7, wherein the polycrystalline semiconductor is formed by laser annealing.
T. 9. A polycrystalline semiconductor TFT having no low impurity concentration region between the semiconductor layer and the source / drain regions, and the polycrystalline semiconductor TFT according to claim 5, 6, 7 or 8. TFT substrate characterized by.