JPH07142739A - Manufacture of polycrystal line silicon thin-film transistor - Google Patents

Abstract

PURPOSE:To make thin only a channel portion and its vicinities and also to provide an LDD structure by forming a gate electrode on a polycrystalline silicon layer having a thicker layer at a source-drain portion than a channel portion and its vicinities on a substrate and by filling the polycrystalline silicon layer with the impurities at an accelerated voltage. CONSTITUTION:An island of a polycrystalline silicon film 2 and a gate oxide film 3 as a gate insulation layer are formed in such a manner that the layer thickness of a source portion 9 and a drain portion 10 becomes larger than that of a channel portion 11 and its vicinities on a quartz substrate 1. After performing the doping of phosphorus of a high concentration, a gate electrode 4 is formed. Next, by using an ion implantation apparatus with the gate electrode 4 as a mask, arsenic of a low concentration is first injected at a predetermined accelerated voltage and in succession arsenic of a high concentration is fully injected at a accelerated voltage higher than that of the preceding process. As a result, the arsenic has a low concentration at the portion 12 between the channel portion and the source portion and at the portion 13 between the channel portion and drain portion, thereby providing an LDD region 8 having a gentle concentration gradient.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and more particularly to a method for manufacturing a polycrystalline silicon thin film transistor suitable for a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been widely used as display devices for OA equipment such as Japanese word processors and personal computers because they have the great advantages of thinness, light weight and low power consumption. In particular, a polycrystalline silicon thin film transistor using polycrystalline silicon for the active layer (hereinafter,
An active matrix type liquid crystal display device using poly-Si TFTs) has been drawing attention because it is easy to obtain a large screen and conventional semiconductor manufacturing technology can be applied to manufacturing. Here, the Poly-Si TFT is applied to a switching element for applying a voltage to liquid crystal in a pixel of a display pixel section of a liquid crystal display device and a drive circuit section for driving the switching element. At the same time, it is desired to improve the characteristics of Poly-Si TFTs and improve the manufacturing process. Above all, the Poly-Si TFT used as a switching element is required to reduce the drain leak current. This is because the drain leak current occurs on the OFF side of the transistor operation, so
This is because the ON / OFF switching function is not sufficiently fulfilled, and when it is used in a liquid crystal display device, electric signals of pixels cannot be held, so that the contrast is deteriorated and the image quality of the liquid crystal display device is particularly affected.

However, originally the Poly-Si TFT is
There is a problem that the leakage current is large for two reasons. One reason is due to the structure of the polycrystalline silicon film, and the other reason is due to the light leakage current caused by the light entering the transistor.

The leak current due to the structure of the polycrystalline silicon film is generated for the following reasons. In general, the source and drain parts of a thin film transistor are formed in a self-aligned manner by implanting necessary ions into a junction layer with an ion implanter using a gate electrode as a mask. Therefore, the charge distribution sharply rises from the end of the gate electrode. Since the electric field distribution is proportional to the charge distribution, the electric field rises rapidly near the drain. Due to this electric field, a tunnel current flows at the junction between the channel and the drain, which is observed as an abnormal leak current.

As a method for preventing the generation of abnormal leakage current, LDD (Lightly Doped Drain) is used.
n) A technique known as a structure is known. This technique is a technique for forming a drain junction by gradually changing the charge distribution near the drain portion. Since the charge distribution changes gradually,
The junction electric field at the junction gradually changes, and abnormal leakage current stops flowing.

A conventional LDD structure manufacturing method will now be described with reference to the transistor manufacturing process as shown in FIG.
It will be described with reference to FIGS. (A) First, a polycrystalline silicon film is formed on the quartz substrate 1,
The islands of the polycrystalline silicon film are formed by CDE etching. Then, surface oxidation is performed to form the first polycrystalline silicon film 2 and the gate oxide film 3.

(B) A second polycrystalline silicon film is formed on the film of (a), heavily doped with phosphorus, activated at a high temperature, and the gate electrode 4 is formed by CDE etching.

(C) Using the ion implanter, arsenic is implanted over the entire surface using the gate electrode 4 as a mask to form the gate electrode 4
The low-concentration region 5 is formed except for the lower part of.

(D) Next, both sides of the gate electrode are covered with a resist 6 by a PEP process, and arsenic is implanted at a high concentration from above with an ion implanter to form a high concentration region 7.

(E) When the resist 6 is removed, the lower side of the portion covered with the resist becomes the LDD region 8 (region having a low impurity concentration), and the outside thereof is the source portion 9 and the drain portion 10 (both impurities). It becomes a high concentration area). The lower side of the gate electrode becomes the channel portion 11. As described above, the LDD structure is a method in which a low-concentration region is provided in the vicinity of the source / drain portions to relax the electric field and reduce leakage current.

On the other hand, as an effective measure for reducing the light leak current caused by the light entering the transistor, there is a method of reducing the thickness of the channel portion and the vicinity of the channel of the polycrystalline silicon film. It is also known that this reduces the light leak current and at the same time improves the TFT characteristics such as the decrease of the threshold voltage and the off leak current.

[0012]

However, the above-mentioned method for reducing the leakage current has the following problems. In the case of the LDD structure, the implantation on the low-concentration side is usually performed with a gate mask, but on the high-concentration side it is necessary to shift it from directly under the gate, so some mask is always required. Usually, this mask uses a resist, an oxide film, or the like, but it is unavoidable that the manufacturing process becomes complicated, and therefore there is a problem that the manufacturing yield is reduced.

When the islands of the polycrystalline silicon film are made thin, the thickness must be thinned from the initial film formation, so that the crystallinity is lowered. At the same time, since the source / drain portions are also thinned, there is a problem that the TFT characteristics are deteriorated due to poor contact with the wiring.

The present invention has been made in order to solve such a problem, and thins only the channel portion and its periphery without thinning the source / drain portion, and the LD
The purpose is to manufacture a Poly-Si TFT having a D structure without increasing the number of PEP steps.

[0015]

Poly-SiTF of the present invention
The manufacturing method of T includes a substrate, a step of forming a polycrystalline silicon layer in which the source / drain portions are thicker on the substrate than on the channel portion and in the vicinity of the channel, and insulating on the polycrystalline silicon layer. The method is characterized by including a step of forming a gate electrode through the layer and a step of implanting impurities into the polycrystalline silicon layer with at least two kinds of accelerating voltages using the gate electrode as a mask.

The polycrystalline silicon layer according to the present invention can be formed on the substrate by a known method. For example, first, low pressure CVD on a substrate such as alkali-free glass or quartz,
A polycrystalline silicon layer can be formed by depositing an amorphous silicon layer using a plasma CVD apparatus or the like and then performing heat treatment.

As a method for forming the source / drain portions so that the source / drain portions are thicker than the channel portion and the portion in the vicinity of the channel, a polycrystalline silicon layer is uniformly formed and then the layer thickness is adjusted by etching, or dummy oxidation is performed. Methods and the like can be used. In the dummy oxidation method, after forming an oxide film on the surface of a uniformly formed polycrystalline silicon layer, the oxide film is peeled off leaving the source / drain portions, and then the part where the oxide film is peeled is further oxidized. The method is to peel off the entire oxide film. The channel vicinity part means an intermediate region between the source / drain part and the channel part. The thickness of the portion near the channel is formed thinner than that of the source / drain portion. Preferably, it is formed with the same layer thickness as the channel portion.

As a method for forming an insulating layer on the polycrystalline silicon layer formed as described above, a known method such as a thermal oxidation method can be used. The layer thickness of this insulating layer can be determined in relation to the magnitude of at least two kinds of accelerating voltages used when implanting impurities. For example, low-concentration (10 ¹² particles / cm ² ) impurity injection is performed at a low acceleration voltage (150 keV), and high-concentration (10 ¹⁵ particles / cm ² ) is injected at a high acceleration voltage (200-220 keV). In the case of 2), the LDD region having a favorable impurity concentration gradient can be obtained by making the layer thickness of the insulating layer uniform between the source / drain portion and the channel vicinity portion. On the other hand, when the low-concentration impurity implantation is performed at a high acceleration voltage and the high-concentration impurity implantation is performed at a low acceleration voltage, the thickness of the insulating layer is improved by increasing the thickness in the vicinity of the channel rather than in the source / drain portion. L
The DD area is obtained.

The following methods can be used to increase the thickness of the insulating layer above the channel portion and near the channel portion rather than the source / drain portion. First, after forming an oxide film on the surface of a uniformly formed polycrystalline silicon layer, a nitride film is selectively formed only on the source / drain portions. After that, an oxide film is formed over the surface of the polycrystalline silicon layer, and then the nitride film is peeled off. In this way, the layer thickness of the insulating layer above the channel portion and near the channel portion can be made larger than that of the source / drain portion.

The method of forming the gate electrode on the above-mentioned insulating layer is performed by forming a second polycrystalline silicon film on the oxide film, performing high concentration phosphorus doping, activating at a high temperature, and performing CDE etching. A known method such as that according to the above can be used.

By implanting impurities into the polycrystalline silicon layer with at least two kinds of accelerating voltages depending on the thickness of the insulating layer, a good LDD structure can be obtained. The two types of accelerating voltage depend on the thickness of the insulating layer above the source / drain part and the part near the channel, the type of impurities, and the implantation amount, but low accelerating voltage is 150 to 170 keV and high accelerating voltage is 310 to 400 keV
It is preferably in the keV range. Further, the application order of the low acceleration voltage and the high acceleration voltage may be first.

[0022]

The operation will be described below with reference to FIG. 2, which schematically shows the relationship between the thickness of the insulating layer above the source / drain portion and the portion near the channel, the acceleration voltage, and the impurity implantation dose distribution. Figure 2
FIG. 2A shows the case where the insulating layer thickness is equal in the source / drain portion and the upper portion near the channel, and FIG. 2B shows the case where the insulating layer thickness in the upper portion near the channel is thicker than that in the source / drain portion. 2 (a) and 2 (b), the distribution curve (a) shows a low acceleration voltage, and the distribution curve (b) shows an impurity implantation concentration distribution at a high acceleration voltage.
However, the impurity implantation concentration is the same.

In FIG. 2A, for example, when impurities are implanted at a low acceleration voltage, the concentration of the impurities is distributed in the distribution curve (a).
Since the insulating layer is constant, the entire polycrystalline silicon layer is doped with impurities in the vicinity of the channel where the active layer is thin, but the source / drain parts where the active layer is thick are mainly formed on the insulating layer. To be doped. On the other hand, the concentration at high accelerating voltage is shown by the distribution curve (b), and the vicinity of the channel where the active layer is thin penetrates through the polycrystalline silicon layer and is mainly doped with impurities that do not contribute to activation. The thick source / drain portions are doped in the entire polycrystalline silicon layer. Therefore, in this case, the LD with a gentle concentration gradient can be obtained by lowering the impurity implantation concentration at a low acceleration voltage and increasing the impurity implantation concentration at a high acceleration voltage.
The D region can be formed. Note that the impurity implantation method using the low acceleration voltage / low impurity implantation concentration and the high acceleration voltage / high impurity implantation concentration can be applied even when the insulating layer thickness of the source / drain portion is thicker than that in the vicinity of the channel.

Next, referring to FIG. 2B, for example,
When impurities are implanted with a low acceleration voltage, the concentration is shown by the distribution curve (a). Since the insulating layer is thick near the channel where the active layer is thin, it stays in the insulating layer that is not involved in activation and is hardly doped into the polycrystalline silicon layer. Doped throughout the layer. On the other hand, the concentration in the case of a high accelerating voltage is shown by the distribution curve (b), and the source / drain portions are doped under the polycrystalline silicon layer while the channel vicinity portion is entirely doped with the polycrystalline silicon layer. Therefore, in this case, the LDD region having a gentle concentration gradient can be formed by increasing the impurity implantation concentration at a low acceleration voltage and decreasing the impurity implantation concentration at a high acceleration voltage.

In the above description, two types of acceleration voltage, one having a high magnitude and one having a low magnitude, have been described. However, a plurality of acceleration voltages can be used, and the vicinity of the channel and the source.
By combining with the layer thickness of the drain portion and the impurity implantation concentration, it is possible to form an LDD region having a more gradual concentration gradient.

As described above, for Poly-Si TFTs having different layer thicknesses in the vicinity of the channel and the source / drain portions, a low concentration of impurities is provided between the channel portion and the source portion and between the channel portion and the drain portion. Regions can be formed, and source / drain portions can be formed in thick portions. As a result, it is possible to manufacture a transistor having a countermeasure against leakage current while maintaining good contact with the wiring without increasing the number of PEP steps.

[0027]

Embodiments of the present invention will be described in detail with reference to the drawings. Example 1 FIGS. 3A to 3E are views showing a method for manufacturing a Poly-Si TFT when the insulating layer thickness is constant. On the quartz substrate 1, the thickness of the channel and its vicinity is 85.
An island of a polycrystalline silicon film is formed by a dummy oxidation method so that the film thickness of the source portion 9 and the drain portion 10 is 1350 angstroms. Then, surface oxidation is performed in an oxidation furnace to form a film with the first polycrystalline silicon film 2.
A gate oxide film 3 which is a gate insulating layer of 700 angstrom is formed (FIG. 3A).

A second polycrystalline silicon film is formed on the gate oxide film 3, is doped with high concentration phosphorus, is activated at a high temperature, and is formed by CDE etching to form a gate electrode 4 (FIG. 3B. )).

Using the gate electrode 4 as a mask, a low concentration (about 10 ¹² pieces / cm ² ) of arsenic is implanted into the entire surface by using an ion implanter. At this time, the acceleration voltage of the ion implanter is 150k
When set to eV, the low concentration region 5 is formed under the gate oxide film of the source part 9 and the drain part 10. On the other hand, the low-concentration region 5 is simultaneously formed in the region 12 between the channel part 11 and the source part 9 and in the region 13 between the channel part 11 and the drain part 10. The entire polycrystalline silicon film 2 of No. 1 is doped with arsenic (FIG. 3).
(C)).

Subsequently, a high concentration (about 10 ¹⁵ atoms / cm ² ) of arsenic is implanted again using the gate electrode 4 as a mask at an acceleration voltage of 315 keV higher than that in the previous step. At this time, the arsenic implanted into the source portion 9 and the drain portion 10 is distributed in the first polycrystalline silicon film 2, but the gap 12 between the channel portion 11 and the source portion 9 and the channel portion 11 and the drain portion 10 are distributed. The arsenic implanted in the space 13 and the space 13 penetrates the first polycrystalline silicon film 2 and reaches the quartz substrate 1 because of its thin film thickness. Since the arsenic 14 reaching the quartz substrate 1 does not participate in activation, the region 12 between the channel portion and the source portion and the region 13 between the channel portion and the drain portion become a low concentration region (FIG. 3 (d)). .

Through the above steps, a Poly-Si TFT having an LDD region 8 with a more gradual concentration gradient can be formed (FIG. 3 (e)).

The obtained Poly-Si TFT showed good characteristics that the drain current was almost the same as the value of the gate voltage of 0 V even if the gate voltage was changed.

Example 2 FIGS. 4 (a) to 4 (e) are views showing a method of manufacturing a Poly-Si TFT when the insulating layer thickness in the channel portion and in the vicinity of the channel portion is thicker than that in the source / drain portion. .
On the quartz substrate 1, the thickness of the channel portion and the portion near the channel is 850 Å, and the source portion 9 and the drain portion 1 are formed.
An island of a polycrystalline silicon film is formed by the dummy oxidation method so that the film thickness of 0 becomes 1350 angstrom. Then, surface oxidation is performed in an oxidation furnace to form a gate oxide film having a film thickness of 700 Å on the polycrystalline silicon film. After that, a nitride film is selectively formed on the source / drain area only by 100
After forming 0 angstrom, an oxide film of 300 angstrom is formed again on the surface of the polycrystalline silicon layer, and then the nitride film is peeled off. As a result, the source / drain area is 700
Angstrom, channel and near channel
A gate oxide film 3 which is a gate insulating layer of 1000 angstrom is formed (FIG. 4A).

A second polycrystalline silicon film is formed on the gate oxide film 3, is doped with high concentration phosphorus, is activated at a high temperature, and is formed by CDE etching to form a gate electrode 4 (FIG. 4 (b). )).

Using the gate electrode 4 as a mask, a low concentration (about 10 ¹² pieces / cm ² ) of arsenic is implanted into the entire surface by using an ion implanter. At this time, the acceleration voltage of the ion implanter is 400k
If set to eV, the distance between the channel section 11 and the source section 9 is 1
A low-concentration region 5 is formed between the channel portion 11, the channel portion 11, and the drain portion 10. On the other hand, arsenic is also implanted into the source part 9 and the drain part 10. However, since the gate oxide film is thin in this region, arsenic is doped deep in the first polycrystalline silicon film 2 (see FIG. 4 (c)).

Subsequently, a high concentration (about 10 ¹⁵ atoms / cm ² ) of arsenic is implanted again using the gate electrode 4 as a mask at an acceleration voltage of 150 keV, which is lower than in the previous step. At this time, the arsenic implanted in the source portion 9 and the drain portion 10 is distributed in the first polycrystalline silicon film 2 because the gate oxide film 3 is thin.
However, the arsenic implanted between the channel portion 12 and the source portion 12 and between the channel portion and the drain portion 13 remains in the gate oxide film 3 because the thickness of the gate oxide film 3 is large. Since the arsenic 15 in the gate oxide film 3 does not participate in activation, the space 12 between the channel portion and the source portion and the space 13 between the channel portion and the drain portion are low concentration regions (FIG. 4).
(D)).

Through the above steps, a Poly-Si TFT having an LDD region 8 with a more gradual concentration gradient can be formed (FIG. 4 (e)).

The obtained Poly-Si TFT showed good characteristics that the drain current was almost the same as the value of the gate voltage 0 V even if the gate voltage was changed.

[0039]

According to the method of manufacturing a Poly-Si TFT of the present invention, a step of forming a polycrystalline silicon layer in which the source / drain portions are thicker on the substrate than on the channel portion, and on the polycrystalline silicon layer Since it has a step of forming a gate electrode via an insulating layer and a step of implanting impurities into the polycrystalline silicon layer with at least two kinds of accelerating voltages using the gate electrode as a mask, good contact with the wiring can be achieved. It is possible to easily fabricate a thin film transistor having an LDD structure while taking measures against light leakage while maintaining the above temperature, and without increasing the PEP process.

[Brief description of drawings]

FIG. 1 is a diagram showing a method for manufacturing a conventional LDD structure.

FIG. 2 is a diagram schematically showing a relationship of impurity implantation amount distribution.

FIG. 3 Poly-Si TFT when the insulating layer thickness is constant
It is a figure which shows the manufacturing method of.

[Fig. 4] Po when the insulating layer thickness in the upper part near the channel is thick
It is a figure which shows the manufacturing method of ly-SiTFT.

[Explanation of symbols]

1 ... Quartz substrate, 2 ... First polycrystalline silicon film,
3 ... Gate oxide film, 4 ... Gate electrode, 5 ...
Low-concentration area, 6 ......... resist, 7 ......... high-concentration area,
8 ... LDD region, 9 ... Source part, 10 ... Drain part, 11 ... Channel part, 12 ... Between channel part and source part, 13 ... Channel part and drain part Between 14 ......... Arsenic reaching the quartz substrate, 15
……… Arsenic in the gate oxide film.

Claims (1)

[Claims] 1. A substrate, a step of forming a polycrystalline silicon layer in which a source / drain portion is thicker than a channel portion and a portion in the vicinity of the channel on the substrate, and insulation on the polycrystalline silicon layer. Of a polycrystalline silicon thin film transistor characterized by including a step of forming a gate electrode through a layer and a step of implanting impurities into the polycrystalline silicon layer with at least two kinds of accelerating voltages using the gate electrode as a mask. Production method.