JPH09139504A - Coplanar type thin film transistor, its manufacture, and liquid crystal display using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT(thin film transistor) wherein electron mobility is increased, channel length is reduced, and self-alignment is perfect, and shorten the manufacturing process without using silicide. SOLUTION: A light shielding film 2 of Ta is formed on a glass substrate 1, and an SiO2 insulating film 3 covering the film 2 is formed, on which a film of I-type microcrystal silicon 4 is formed as a semiconductor layer and patterned in an island type. After a gate insulating film 5 is formed on the semiconductor layer, Al-Si alloy is sputtered on the film 5, and patterned in a gate electrode 6. The semiconductor layer is subjected to ion doping by using the gate electrode as a mask, and source.drain regions 7, 8 are formed. An interlayer insulating film 9 of Si3 N4 is formed. A contact hole penetrating the gate insulating film 5 and the interlayer insulating film 9 is formed by a patterning process and an etching process. A source.drain electrodes 11, 12 are formed by patterning the Al-Si alloy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coplanar thin film transistor (Thin F Thin Film Transistor) mainly used for liquid crystal displays.
The present invention relates to an ilm transistor (TFT), a manufacturing method thereof, and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a structure of a thin film transistor 61 which is mainly used in a liquid crystal display and manufactured by a conventional technique. First, the manufacturing process of the thin film transistor 61 will be described with reference to FIG.

The thin film transistor 61 is made of a transparent or electrically insulating substrate 62 such as resin or glass.
A band-shaped gate electrode 63 made of a metal film such as chromium
A gate insulating film 64 of silicon nitride (SiN _x ) formed so as to cover the gate electrode 63, a semiconductor layer 65 made of amorphous silicon, and a channel protection film 6.
6, ohmic contact layers 67 and 68 doped with impurities such as phosphorus, a source electrode 69 and a drain electrode 70 made of metal such as chromium, and a protective layer 71 are laminated in this order.

As described above, the thin film transistor 61 having a structure in which the gate electrode 63 is first formed on the substrate 62 is called an inverted stagger type. On the other hand, although not shown, a thin film transistor having a structure in which a source electrode and a drain electrode are first formed on a substrate is called a forward stagger type as opposed to the above-mentioned inverted stagger type.

In the inverted staggered thin film transistor 61, ohmic contact layers 67 and 6 are formed on the semiconductor layer 65.
8 is formed, ohmic contact layers 67 and 6 are formed corresponding to the source electrode 69 and the drain electrode 70.
In order to prevent the semiconductor layer 65 from being etched at the time of etching the channel 72 portion for separating the channel 8, the channel protective film 6 is usually formed on the semiconductor layer 65.
6 is formed.

In this case, the obtained thin film transistor 61
However, since the channel protective film 66 is formed, complete self-alignment is not possible, and it is difficult to shorten the channel length to less than the usual 10 μm.

On the other hand, there is also a method of completing the thin film transistor 61 without using the channel protective film 66 in order to shorten the channel length. However, according to this method, when the channel 72 is etched, the semiconductor layer 65
Therefore, the semiconductor layer 65 needs to be thick. As a result, backside exposure cannot be performed using the gate electrode as a mask, which causes a problem that self-alignment cannot be performed.

In view of this, an inverted staggered thin film transistor, which uses a channel protective film to achieve complete self-alignment and shortens the channel length, is disclosed in Japanese Patent Application Laid-Open No. 63-168052. FIG. 6 is a cross-sectional view showing the manufacturing process of the thin film transistor described in the above publication.
The manufacturing process of the thin film transistor will be described based on FIG.

First, as shown in FIG. 6A, a gate electrode 82 is formed by sputtering a metal such as chromium as a gate metal on an insulating substrate 81 such as glass and patterning it.
Mold into Next, a silicon nitride (SiN _x ) gate insulating film 83, an amorphous silicon film 84, and a silicon oxide (S
A channel protection film 85 of iO _x ) is laminated in this order by a plasma CVD method, and further the amorphous silicon film 8 is formed.
4 and the channel protection film 85 are patterned in an island shape. After that, the photoresist 86 is coated on the surface, and the back surface is exposed from the gate side using the gate as a mask.

After patterning the photoresist 86, the photoresist 86 is used as a mask as shown in FIG.
As shown in (b), the channel protection film 85 is patterned. Next, with the channel protective film 85 as a mask, phosphorus as impurity atoms is ion-implanted into the amorphous silicon film 84 to form source / drain regions 87. Subsequently, as shown in FIG. 6C, a metal such as chromium is sputtered as the source / drain electrode metal 88. At this time, the silicide layer 8 is formed between the source / drain electrode metal 88 and the source / drain region 87.
9 (see FIG. 6D) is formed. After that, FIG.
As shown in (d), metal 88 for source / drain electrodes
Is etched to pattern the source / drain electrodes 90 to complete the thin film transistor 91.

[0011]

However, in the above publication, the silicide layer 89 is formed between the source / drain electrode metal 88 and the source / drain region 87 in order to reduce the resistance. In order to form the silicide layer 89, it is necessary to perform annealing at 150 ° C. for 20 minutes, and to devise not to etch the silicide layer 89 when the source / drain electrode metal 88 is etched and patterned. Therefore, there is a problem that the number of manufacturing processes is increased. Furthermore, the silicide layer 89 may be formed on the upper surface or the side surface of the channel protective film 85, and at that time, a leak occurs and the off current increases. Therefore, when the silicide layer 89 formed on the channel protective film 85 or the like is removed by etching in order to reduce the off current, the channel protective film 85 needs to be large so that it can be etched. As a result, the channel length becomes longer, and the number of manufacturing steps increases due to the etching of the silicide layer 89.

When the semiconductor layer is an amorphous semiconductor film, the conductivity in the source / drain regions is as low as 1.0 × 10 ⁻⁴ / Ωcm even if ion doping is performed. As a result, there is a problem that the on-current decreases due to the voltage drop in the source / drain regions.

Further, in general, in the manufacturing process of the inverted staggered thin film transistor, the formation of the gate electrode and the source / drain electrodes is performed in the first process due to its structure regardless of the presence or absence of the channel protective film. Therefore, a low resistance metal such as aluminum (Al) is likely to cause hillocks due to heat in the subsequent process, and a low resistance metal such as aluminum is used as an electrode metal material in order to drive a large-sized or high-definition panel. There is also the problem that it is difficult.

The present invention has been made to solve the above problems, and its purpose is to use a low resistance metal for an electrode and to have a short channel length, a high electron mobility, and a complete self-alignment. It is to provide a coplanar thin film transistor and a manufacturing method thereof.

[0015]

In order to solve the above-mentioned problems, a coplanar thin film transistor according to the invention of claim 1 has a semiconductor layer formed on an insulating substrate and a gate electrode formed on the semiconductor layer. A coplanar thin film transistor comprising at least a gate insulating film formed under the gate electrode, a source / drain region, and a source / drain electrode electrically connected to the source / drain region. Is characterized in that at least a part in the film thickness direction is a microcrystalline semiconductor, and source / drain regions containing impurities are formed in at least the microcrystalline semiconductor portion of the semiconductor layer except directly under the gate electrode.

With the above structure, the semiconductor layer is formed on the insulating substrate. At least part of this semiconductor layer in the film thickness direction is made of a microcrystalline semiconductor and has source / drain regions. A gate electrode is formed on the semiconductor layer, and a gate insulating film is formed at least under the gate electrode. The source / drain electrodes are formed so as to be electrically connected to the source / drain regions.

The source / drain regions correspond to the regions except directly under the gate electrode, and impurities are implanted in the source / drain regions. As a result, the source / drain regions are obtained by self-alignment with the gate electrode.

As described above, when at least a part of the semiconductor layer in the film thickness direction is made of a microcrystalline semiconductor, the conductivity of the source / drain regions after the impurity implantation is higher than that of the conventional case made of an amorphous semiconductor. Become. As a result, the electron mobility is increased, so that the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

In order to solve the above-mentioned problems, a coplanar thin film transistor according to a second aspect of the present invention has the structure according to the first aspect, wherein at least a part of the semiconductor layer in the film thickness direction is made of silicon germanium SiGe _x (0 ≦ x ≦). 1), silicon carbon SiC _x (0 ≦ x ≦ 1), silicon nitride Si ₃ N _x (0 ≦ x ≦ 4), silicon oxide SiO _x (0
It is characterized in that it is made of a microcrystalline semiconductor of ≦ x ≦ 2).

With the above structure, in addition to the function of the first aspect, the microcrystalline semiconductor of silicon carbon SiC _x , silicon nitride Si ₃ N _x , and silicon oxide SiO _x is a conventional non-crystalline semiconductor having a semiconductor layer. Since the band gap is larger than that of a crystalline semiconductor, even if light is irradiated to this thin film transistor, electrons are not excited from the valence band to the conduction band, and thus the off current is less likely to increase. Therefore, if the thin film transistor is manufactured by forming the microcrystalline semiconductor on at least a part of the semiconductor layer in the film thickness direction, the thin film transistor can be suitably used for a projection type liquid crystal panel using light of high intensity. In addition, since the band gap of the silicon germanium SiGe _x microcrystalline semiconductor can be controlled to be narrow, _if the microcrystalline semiconductor is formed on at least a part of the semiconductor layer in the film thickness direction to manufacture a thin film transistor, the above-mentioned thin film transistor can be manufactured. Can be driven at a low voltage.

In order to solve the above-mentioned problems, a coplanar thin film transistor according to a third aspect of the present invention is characterized in that, in the structure of the first aspect, the semiconductor layer is formed by laminating an amorphous semiconductor and a microcrystalline semiconductor. There is.

With the above structure, in addition to the effect of the structure of claim 1, the on-current of the coplanar thin film transistor can be significantly increased as compared with the case where the microcrystalline semiconductor is not laminated with the amorphous semiconductor. .

Moreover, since the amorphous semiconductor is formed at a faster speed than the microcrystalline semiconductor, the amorphous semiconductor and the microcrystalline semiconductor are stacked as described above, so that the microcrystalline semiconductor can be used alone. The time required for the film formation as a whole can be significantly shortened as compared with the case where the film is formed, and the throughput can be improved.

Further, for example, when the microcrystalline semiconductor layer is formed after the amorphous semiconductor layer is formed, the lower layer can be prevented from being reduced by hydrogen plasma at the time of film formation of the microcrystalline semiconductor, and at the same time, the semiconductor can be prevented. In the layer, an amorphous semiconductor having a poor film quality at the beginning of film formation can be removed and a good amorphous semiconductor can be introduced into a portion where a channel is formed.

In order to solve the above-mentioned problems, a method of manufacturing a coplanar thin film transistor according to a fourth aspect of the present invention,
A step of forming a semiconductor layer including a microcrystalline semiconductor at least partly in the film thickness direction on an insulating substrate, a step of forming an insulating film so as to cover the semiconductor layer, and a gate electrode by forming and patterning a metal film And a step of injecting impurities into at least the microcrystalline semiconductor portion of the semiconductor layer using the gate electrode or the gate electrode and the resist thereon as a mask, and forming the metal film and patterning the impurities. And forming a source / drain electrode electrically connected to the implanted semiconductor region.

With the above structure, the semiconductor layer is formed on the insulating substrate. At least a part of this semiconductor layer in the film thickness direction is made of a microcrystalline semiconductor. An insulating film is formed so as to cover the semiconductor layer. A metal film is formed on this insulating film and patterned to form a gate electrode. Then, impurities are implanted into at least the microcrystalline semiconductor portion of the semiconductor layer using the gate electrode or the resist formed thereon as a mask. As a result, the impurity-implanted semiconductor region is obtained by self-alignment with the gate electrode.

After that, a metal film is formed and patterned to form source / drain electrodes. The source / drain electrodes are electrically connected to the semiconductor region in which the impurities are implanted.

As described above, since the impurity is injected into at least the microcrystalline semiconductor portion of the semiconductor layer at least a part of which in the film thickness direction is made of the microcrystalline semiconductor, the conductivity of the semiconductor region after the impurity implantation is: It is larger than the conventional case made of an amorphous semiconductor. As a result, the electron mobility is increased, so that the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

A liquid crystal display device according to a fifth aspect of the invention is characterized by using the coplanar thin film transistor according to the first aspect in order to solve the above problems.

With the above structure, the coplanar type thin film transistor according to the first aspect can improve the on-current by about 1.5 times as compared with the conventional thin film transistor in which the amorphous semiconductor is formed. . Therefore, when the above coplanar thin film transistor is adopted in a liquid crystal display, a 10.4 inch VGA (Video Graphics)
The aperture ratio of the array can be improved from 60% to 65%, and the liquid crystal display can be brightened. Further, due to the increase in on-current, it is possible to manufacture a liquid crystal display for an engineering workstation having 17-inch 1280 × 3 × 1024 picture elements, which was difficult in the past.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a cross-sectional view showing a manufacturing process of a coplanar thin film transistor, which is one embodiment of the present invention. The manufacturing process will be described in detail below with reference to FIG.

First, as shown in FIG. 1A, tantalum (T) is deposited on a transparent glass substrate 1 which is an electrically insulating substrate.
a) is formed into a film having a thickness of 150 nm by sputtering,
It is patterned into an island shape to form the light shielding film 2. Next, silicon oxide (Si
O ₂ ) is sputtered to form a SiO ₂ insulating film 3 having a thickness of 200 nm. Then, on the insulating film 3, under the conditions of a substrate temperature of 350 ° C., a pressure of 110 Pa, and an RF power of 400 W, a hydrogen dilution ratio (H ₂ / SiH ₄ ) of about 130 times silane (SiH ₄ ) 15 sccm, hydrogen (H ₂ ) 2000s
Using ccm, i-type microcrystalline silicon 4 is deposited to 70 nm as a semiconductor layer by a plasma CVD method. afterwards,
CF ₄ 280sccm, O ₂ 120sccm, RF
The i-type microcrystalline silicon 4 is dry-etched into an island shape under the condition of a power of 500 W.

Next, the substrate temperature is 300 ° C. and the pressure is 110P.
a, silane (Si
H ₄ ) 150 sccm, ammonia (NH ₃ ) 200 s
Nitrogen as an insulating film is formed by plasma CVD using ccm and 2000 sccm of nitrogen (N ₂ ) so as to cover the i-type microcrystalline silicon 4 formed in an island shape as shown in FIG. 1B. A gate insulating film 5 of silicon (Si ₃ N ₄ ) is formed to a thickness of about 200 nm. Then, silicon (S
i-containing 2 at% aluminum-silicon (Al-S
i) The alloy is sputtered to form a film having a thickness of 350 nm, and patterned to form the gate electrode 6. Then, in order to suppress the hillock phenomenon, the gate electrode 6 is set to 100 n.
m Anodize.

Next, using the gate electrode 6 as a mask, the i-type microcrystalline silicon 4 is removed from above the gate insulating film 5 by an ion doping apparatus except the region directly below the gate electrode 6.
Ion-doping with H ₃ . The doping conditions at this time are an ion energy of 100 keV and a dose amount of 1.0 × 10 ¹⁶ ions / cm ² . As a result, as shown in FIG. 1C, the semiconductor region has a conductivity of 5.0.
Source / drain regions 7 and 8 made of n + type microcrystalline silicon having a low resistance of × 10 ^-1 / Ωcm are formed. At this time, the source / drain regions 7 and 8 are obtained by self-alignment with the gate electrode 6.

Subsequently, the substrate temperature is 270 ° C. and the pressure is 110P.
a, silane (Si
H ₄ ) 150 sccm, ammonia (NH ₃ ) 200 s
As shown in FIG. 1D, a silicon nitride (Si ₃ N ₄ ) interlayer insulating film 9 is formed to a thickness of about 250 nm by plasma CVD using ccm and 2000 sccm of nitrogen (N ₂ ). Then, indium oxide (ITO) containing 5 at% of tin (Sn) is sputtered and etched to form the pixel electrode 10. After that, a contact hole penetrating the interlayer insulating film 9 is formed by patterning and etching. Then, although not shown, titanium (Ti) having a thickness of 15 nm is first formed in the contact hole as a barrier layer, and subsequently, an aluminum-silicon (Al-Si) alloy containing 2 at% of silicon (Si) is sputtered to form a film. A thickness of 350 nm is formed and patterning is performed. As a result, the source / drain electrode 1 electrically connected to the source / drain regions 7 and 8
1, 12 will be formed.

Finally, in order to improve reliability and yield rate,
As shown in FIG. 1 (e), silicon nitride (Si ₃
A protective film 13 of N ₄ ) is formed to obtain a coplanar thin film transistor 14.

The thin film transistor 14 has a channel width of 15 μm, which is the same as the conventional one, but the channel length is 5 μm.
And is shorter than the conventional inverted stagger type 11 μm. Further, in terms of electrical characteristics, the gate voltage is 10
The on-current generated when V and a voltage between the source and the drain of 10 V are applied is 2.5 × 10 ⁻⁶ A or more. On the other hand, the off-current generated when a gate voltage of −15 V and a source-drain voltage of 10 V is applied is 1.0 × 10 ⁻¹² A or less. Furthermore, the electron mobility is about 1.1 cm ² / V
・ Sec, which is about 1.5 times the conventional value.

In the present embodiment, ion doping is performed using only the gate electrode 6 as a mask, but a resist (not shown) formed on the gate electrode 6 when patterning the gate electrode 6 is used. Alternatively, ion doping may be performed using the gate electrode 6 and the resist as a mask. Since mass separation is not performed at the time of ion doping, hydrogen ions are also injected. Therefore, it is more preferable to perform ion doping with the resist left behind because hydrogen ions are more likely to be blocked.

With the above structure, when at least a part of the semiconductor layer in the film thickness direction is made of a microcrystalline semiconductor, the conductivity of the source / drain regions 7 and 8 after the impurity implantation is the same as that of the conventional semiconductor made of an amorphous semiconductor. Will be larger than. As a result, the electron mobility is increased, so that the channel length can be reliably and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

Unlike the inverted staggered thin film transistor, the gate electrode 6 and the source / drain electrodes 11 and 12 are formed in the last step of the manufacturing process, so that the gate electrode 6 and the source / drain electrodes 11 and 12 are formed. Drain electrode 11,
A low resistance metal such as aluminum can be used for 12.

[Second Embodiment] In the first embodiment, the i-type microcrystalline silicon 4 is ion-doped with the gate electrode 6 as a mask while the gate insulating film 5 is left. The gate insulating film 5 excluding the region directly below may be removed by etching, and the i-type microcrystalline silicon 4 may be directly ion-doped. The manufacturing process of the thin film transistor obtained by such a method is shown in FIG.
The manufacturing process will be described in detail below with reference to FIG.

First, the gate insulating film 25 shown in FIG.
Up to the formation of the above, it is the same as in the first embodiment described above.

Next, an aluminum-silicon (Al-Si) alloy containing 2 at% of silicon (Si) is formed by sputtering, and patterning is performed to form the gate electrode 26 (FIG. 2).
(See (b)). After that, the gate electrode 26 is anodized by 100 nm to suppress hillocks.

Then, using the gate electrode 26 as a mask,
CF ₄ 280sccm, O ₂ 120sccm, RF
Si ₃ N ₄ gate insulating film 2 under the condition of power 500W
5 is dry-etched (patterned). As a result, as shown in FIG. 2B, the gate insulating film 25 remains only under the gate electrode 26. afterwards,
Using the gate electrode 26 and the gate insulating film 25 directly below the remaining gate electrode 26 as a mask, the i-type microcrystalline silicon 24 except under the gate insulating film 25 is ion-doped with PH ₃ by an ion doping apparatus. Here, as described above, since the gate insulating film 25 other than directly under the gate electrode 26 is first etched and removed, the acceleration voltage of ions is lowered in order to reduce the damage to the i-type microcrystalline silicon 24. Ion energy is 30 keV
As a result, PH ₃ is ion-doped. The dose amount is 1.0 × 10 ¹⁶ ions / cm 3, which is the same as in the first embodiment.
² As a result, as shown in FIG. 2C, the source / drain regions 27 and 2 made of n + type microcrystalline silicon.
8 is formed. At this time, the source / drain regions 27 and 28 are obtained by self-alignment with the gate electrode 26.

After that, similarly to the first embodiment,
Substrate temperature 270 ° C., pressure 110 Pa, RF power 100
At 0 W, silane (SiH ₄ ) 150 sccm, ammonia (NH ₃ ) 200 sccm, nitrogen (N ₂ ) 20
FIG. 2 shows a plasma CVD method using 00 sccm.
As shown in (d), an interlayer insulating film 29 of silicon nitride (Si ₃ N ₄ ) is formed to a thickness of about 250 nm. After that, tin (S
n) Indium oxide (ITO) containing 5 at% is sputtered and etched to form the pixel electrode 30. After that, a contact hole penetrating the interlayer insulating film 29 is formed by patterning and etching.
Although not shown, titanium (Ti) is first formed in the contact hole to a thickness of 15 nm as a barrier layer, and subsequently, aluminum containing 2 at% of silicon (Si) is formed.
Silicon (Al-Si) alloy is sputtered to a film thickness of 350
nm and patterning is performed. As a result, the source / drain electrodes 31 and 32 electrically connected to the source / drain regions 27 and 28 are formed.

Finally, in order to improve reliability and yield rate,
As shown in FIG. 2 (e), silicon nitride (Si ₃
A protective film 33 of N ₄ ) is formed to obtain a coplanar thin film transistor 34.

In this case, regarding the electric characteristics of the thin film transistor 34, the on-current generated when a gate voltage of 10 V and a source-drain voltage of 10 V are applied is 2.
It is 9 × 10 ⁻⁶ A or more. On the other hand, gate voltage -15V,
The off-current generated when a source-drain voltage of 10 V is applied is 1.0 × 10 ⁻¹² A or less. That is, the characteristics are almost the same as the characteristics obtained in the first embodiment described above.

With the above structure, after the gate insulating film 25 is patterned, the source / drain regions 27 and 28 are subjected to ion doping with respect to the above semiconductor layer at least a part of which in the film thickness direction is made of a microcrystalline semiconductor. Done. At this time, since ion doping is performed through the portion of the gate insulating film 25 that is removed by patterning, the ion acceleration voltage can be reduced and damage to the semiconductor layer due to ion doping can be reduced. it can.

After that, ion doping is performed on the semiconductor layer except for the region directly below the gate insulating film 25. The conductivity of the source / drain regions 27 and 28 after the ion doping is higher than that in the conventional case where the semiconductor layer is made of an amorphous semiconductor. For this reason, the electron mobility is increased, so that the channel length can be surely and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance. Further, since the gate electrode 26 and the source / drain electrodes 31, 32 are formed in the last step of the manufacturing process, a low resistance metal such as aluminum is used for the gate electrode 26 and the source / drain electrodes 31, 32. Can be used.

[Embodiment 3] FIG. 3 shows the relationship between the film thickness and the electrical conductivity when forming the microcrystalline silicon of the semiconductor layer. The film formation conditions of the microcrystalline silicon at this time are as follows: substrate temperature 300 ° C., pressure 110 Pa, RF power 350 W.
Silane (SiH ₄ ) 15 sccm and hydrogen (H
₂ ) 3000 sccm is used. Even if microcrystalline silicon is formed under the above film forming conditions, the conductivity is as low as 5.0 × 10 ⁻¹² / Ωcm or less at a film thickness of 200 Å or less. This is because the conductivity of amorphous silicon is about 0.3.
Considering that the film thickness is up to 5.0 × 10 ^-11 / Ωcm, it is presumed that the film having a film thickness of 200 Å at the initial stage of film formation is amorphous silicon. However, since the above film forming conditions are not suitable for forming amorphous silicon, the film quality of amorphous silicon at this time is poor. After that, in FIG. 3 again, since the electric conductivity also greatly increases as the film thickness increases, it is conceivable that microcrystalline silicon has grown on the amorphous silicon at the initial stage of film formation.

The film forming rate of microcrystalline silicon is about 0.
The film forming rate is 3 Å / sec, which is slower than the film forming rate of amorphous silicon of about 1.0 Å / sec.

Furthermore, under the film formation conditions for microcrystalline silicon by the plasma CVD method, hydrogen (H ₂ ) is large with respect to silane (SiH ₄ ), and the hydrogen dilution ratio is high. Therefore, the lower insulating film is subjected to hydrogen plasma treatment, and there is a problem that the lower layer is reduced.

Therefore, in the third embodiment, in order to improve the above problems, a method of manufacturing a thin film transistor in which two layers of microcrystalline silicon and amorphous silicon are formed as semiconductor layers will be described with reference to FIG. The details will be described below.

FIG. 4 is a sectional view showing a manufacturing process of a coplanar type thin film transistor which is still another embodiment of the present invention.

First, as shown in FIG. 4A, a tantalum (Ta) film having a thickness of 150 nm is formed on a glass substrate 41, which is an electrically insulating substrate, by sputtering, and is patterned into an island shape to shield light. The film 42 is formed. next,
Silicon oxide (Si
O ₂ ) is sputtered to form an insulating film 43 having a film thickness of 200 nm. Then, the substrate temperature 35 is formed on the insulating film 43.
Silane (SiH ₄ ) 200 sccm, hydrogen (H ₂ ) 200 under conditions of 0 ° C., pressure 80 Pa, and RF power 150 W.
First, i-type amorphous silicon 44 is deposited to a thickness of 50 nm as a semiconductor layer by a plasma CVD method using 0 sccm. After that, the substrate temperature is 350 ° C., the pressure is 110 Pa,
Under the condition of RF power 400W, hydrogen dilution ratio (H ₂ / Si
H ₄ ) About 130 times more silane (SiH ₄ ) 15 sccm,
Plasma (CV) using 2000 sccm of hydrogen (H ₂ )
A 30 nm thick i-type microcrystalline silicon 45 is formed on the i-type amorphous silicon 44 by the D method. After that, CF ₄ is 280 sccm, O ₂ is 120 sccm,
The i-type amorphous silicon 44 and the i-type microcrystalline silicon 45 are dry-etched into an island shape under the condition of RF power of 500 W.

Next, the substrate temperature is 300 ° C. and the pressure is 110 P.
a, silane (Si
H ₄ ) 150 sccm, ammonia (NH ₃ ) 200 s
ccm and 2000 sccm of nitrogen (N ₂ ) by a plasma CVD method, as shown in FIG.
-Type amorphous silicon 44 and i-type microcrystalline silicon 4
5 to cover the silicon nitride film (Si ₃ (Si ₃
A gate insulating film 46 of N ₄ ) is formed to a thickness of about 200 nm. Then, aluminum containing 2 at% of silicon (Si)
Silicon (Al-Si) alloy is sputtered to a film thickness of 350
Then, the gate electrode 47 is formed by patterning. Then, in order to suppress hillocks, the gate electrode 4 is formed.
7 is anodized to 100 nm.

Next, using the gate electrode 47 as a mask, the i-type amorphous silicon 44 and the i-type microcrystalline silicon 45 except under the gate electrode 47 are ion-doped with PH ₃ from above the gate insulating film 46 by an ion doping apparatus. To do. The doping conditions at this time are as follows: ion energy is 100 keV and dose is 1.0 × 10.
¹⁶ ions / cm ² . As a result, as shown in FIG. 4C, source / drain regions 48 and 49 made of n + type amorphous silicon and n + type microcrystalline silicon are formed. At this time, the source / drain regions 48 and 49 are obtained by self-alignment with the gate electrode 47.

Subsequently, the substrate temperature is 270 ° C. and the pressure is 110P.
a, silane (Si
H ₄ ) 150 sccm, ammonia (NH ₃ ) 200 s
As shown in FIG. 4D, a silicon nitride (Si ₃ N ₄ ) interlayer insulating film 50 of about 250 nm is formed by plasma CVD using ccm and 2000 sccm of nitrogen (N ₂ ).
Form. Then, indium oxide (ITO) containing 5 at% of tin (Sn) is sputtered and etched to form a pixel electrode 51. After that, the interlayer insulating film 50
A contact hole penetrating through is formed by patterning and etching. Then, titanium (Ti) having a thickness of 15 nm is first formed as a barrier layer in the contact hole, and subsequently, an aluminum-silicon (Al-Si) alloy containing 2 at% of silicon (Si) is sputtered to form a film having a thickness of 350 nm and patterned. I do. As a result, source / drain electrodes 52, 53 electrically connected to the source / drain regions 48, 49 are formed.

Finally, in order to improve reliability and yield rate,
As shown in FIG. 4 (e), silicon nitride (Si ₃
A thin film transistor 55 is obtained by forming a protective film 54 of N ₄ ).

In this case, regarding the electric characteristics of the thin film transistor 55, the on-current generated when a gate voltage of 10 V and a source-drain voltage of 10 V are applied is 3.
It is 1 × 10 ⁻⁶ A or more. On the other hand, gate voltage -15V,
The off-current generated when a source-drain voltage of 10 V is applied is 1.0 × 10 ⁻¹² A or less. That is, the characteristics are almost the same as the characteristics obtained in the first and second embodiments described above.

With the above structure, when the semiconductor layer is formed, the i-type amorphous silicon 44 is formed and then the i-type amorphous silicon 44 is formed.
The i-type microcrystalline silicon 45 is stacked on the type amorphous silicon 44. The i-type amorphous silicon 44 is
Since the film is formed at a faster speed than the i-type microcrystalline silicon 45, the i-type microcrystalline silicon 45 is independently formed by stacking the i-type amorphous silicon 44 and the i-type microcrystalline silicon 45 as described above. The time required for film formation as a whole can be greatly shortened as compared with the case.

Further, in the above structure, since the i-type microcrystalline silicon 45 is formed after the i-type amorphous silicon 44 is formed, the amorphous semiconductor at the initial stage of film formation having a poor film quality is removed from the portion where the channel is formed. An amorphous semiconductor having a good film quality can be introduced.

In addition, i except under the gate electrode 47 is removed.
Since the source / drain regions 48 and 49 are formed by implanting impurities into the region of the type microcrystalline silicon 45,
The conductivity of the source / drain regions 48 and 49 after the impurity implantation is higher than that in the conventional case where the semiconductor layer is made of an amorphous semiconductor. Therefore, since the electron mobility increases,
The channel length can be reliably and significantly shortened without forming a silicide, which was conventionally required to reduce the resistance. Further, since the gate electrode 47 and the source / drain electrodes 52 and 53 are formed in the last step of the manufacturing process, the gate electrode 47 and the source / drain electrode 5
A low resistance metal such as aluminum can be used for 2, 53.

In the third embodiment, it was confirmed from the distribution of phosphorus concentration in the thickness direction of the source / drain regions 48 and 49 by simulation that both amorphous silicon and microcrystalline silicon were n-type. However, the effect of the present invention can be obtained if at least the microcrystalline silicon is of n-type.

Further, in the third embodiment, the i-type microcrystalline silicon 45 is formed on the i-type amorphous silicon 44 and ion doping is performed, but an amorphous semiconductor and a microcrystalline semiconductor are laminated as a semiconductor layer. However, the effect of the present invention can be obtained by adding an impurity to at least the microcrystalline semiconductor portion to form an n + type microcrystalline semiconductor.

In the first to third embodiments described above,
I-type microcrystalline silicon is used for a part of the semiconductor layer in the film thickness direction or one or more laminated microcrystalline semiconductors.
It is not necessarily limited to this. As the above microcrystalline semiconductor, for example, silicon germanium SiGe _x (0 ≦
x ≦ 1), silicon carbon SiC _x (0 ≦ x ≦ 1),
The effect of the present invention can also be obtained by using a microcrystalline semiconductor of silicon nitride Si ₃ N _x (0 ≦ x ≦ 4) or silicon oxide SiO _x (0 ≦ x ≦ 2).

Conventionally, the band gap is about 1.7 eV.
Since amorphous silicon is used for the semiconductor layer, the off current increases because electrons are excited from the valence band to the conduction band when light is irradiated. In order to suppress the off current, the conductivity of the semiconductor layer is about 1.0 × 10 ⁻⁶ / Ω.
It has been empirically obtained that a lower value of about cm or less is better.

Therefore, silicon carbon SiC _x and silicon nitride Si as described above, in which another element is added to silicon, are used.
_{With 3} N _x and silicon oxide SiO _x , the band gap can be controlled from about 1.7 eV to 2.1 eV. If the band gap is large, even if the thin film transistor is irradiated with light, electrons are not excited from the valence band to the conduction band, and the off current hardly increases. Therefore, if the pixel is small like a projection liquid crystal module that uses strong light and you want to suppress the off-current even if the on-current decreases a little, implant an appropriate amount of impurities in silicon and Alloy (conductivity about 1.0 × 10 ^-6 /
Ωcm or less) is more suitable.

In the case of silicon germanium SiGe _x , the band gap is about 1.7 eV to 1.4 eV.
Can be controlled up to. When the band gap is narrowed in this way, it is weak against light, but there is an advantage that the thin film transistor can be driven at a low voltage.

Therefore, as described above, by using a microcrystalline semiconductor obtained by adding another element to silicon and controlling the band gap, a thin film transistor suitable for the application of the liquid crystal module can be manufactured.

Further, in the first to third embodiments,
Since at least one microcrystalline semiconductor layer is formed on the semiconductor layer, compared with the conventional method in which an amorphous semiconductor is formed,
The on-current can be improved about 1.5 times.
Therefore, when the coplanar thin film transistor of the present invention is adopted in a liquid crystal display, it is 10.4 inches VG.
The aperture ratio of A (Video Graphics Array) can be improved from the conventional 60% to 65%, and the liquid crystal display can be brightened. Also, due to the increase in on-current, the 17-inch 1280 × 3, which was difficult in the past,
It is possible to manufacture a liquid crystal display for engineering workstations having × 1024 picture elements.

The specific resistances of α-Ta, β-Ta, and Al are 25 μΩcm, 180 μΩcm, and 5 μΩcm, respectively, and Al is a low-resistance α-Ta of Ta.
It has a low resistance of 1/5. When this Al is used for the gate electrode in the lower layer of the inverted staggered thin film transistor, there is a problem that hillocks are generated due to heat in a later process.

On the other hand, in the coplanar type thin film transistor, the gate electrode is formed after the semiconductor layer and the gate insulating film are formed. Therefore, even if a hillock or the like occurs,
There is little influence on the characteristics of the thin film transistor.

Further, when the picture element is charged by the electric signal, the product of the wiring resistance and the wiring capacitance becomes the time constant. Therefore, when the high resistance wiring is used, only a small panel having a small wiring capacitance or a panel having a poor definition can be driven. On the other hand, when a low resistance wiring such as Al is used, it is possible to drive a large panel or a high definition panel.

[0075]

As described above, in the coplanar thin film transistor according to the invention of claim 1, at least a part of the semiconductor layer in the film thickness direction is a microcrystalline semiconductor, and at least the semiconductor layer except directly under the gate electrode is formed. In this structure, source / drain regions containing impurities are formed in the microcrystalline semiconductor portion.

Therefore, since at least a part of the semiconductor layer in the film thickness direction is made of the microcrystalline semiconductor, the conductivity of the source / drain regions after the impurity implantation is higher than that of the conventional case made of the amorphous semiconductor. Become. That is, since the electron mobility is increased, there is an effect that the channel length can be surely and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

As described above, the coplanar type thin film transistor according to the invention of claim 2 has the following structure:
At least a part of the semiconductor layer in the film thickness direction is silicon germanium SiGe _x (0 ≦ x ≦ 1), silicon carbon SiC _x (0 ≦ x ≦ 1), silicon nitride Si ₃ N _x (0
≦ x ≦ 4) and a silicon oxide SiO _x (0 ≦ x ≦ 2) microcrystalline semiconductor.

Therefore, in addition to the effect of the structure of claim 1, silicon carbon SiC _x , silicon nitride Si ₃
If a thin film transistor is manufactured by forming a microcrystalline semiconductor of N _x and silicon oxide SiO _{x on} at least a part of the semiconductor layer in the film thickness direction, it can be suitably used for a projection type liquid crystal panel using strong light. .
In addition, since the band gap of the microcrystalline semiconductor of silicon germanium SiGe _x can be controlled to be narrow,
If this microcrystalline semiconductor is formed on at least a part of the semiconductor layer in the film thickness direction to manufacture a thin film transistor, the thin film transistor can be driven at a low voltage.

As described above, the coplanar type thin film transistor according to the invention of claim 3 has the following structure.
The semiconductor layer has a structure in which an amorphous semiconductor and a microcrystalline semiconductor are stacked.

Therefore, in addition to the effect of the first aspect, the on-current of the coplanar thin film transistor can be significantly increased as compared with the case where the microcrystalline semiconductor is not laminated with the amorphous semiconductor.

Moreover, since the amorphous semiconductor is formed at a higher speed than the microcrystalline semiconductor, the amorphous semiconductor and the microcrystalline semiconductor are stacked as described above, so that the microcrystalline semiconductor is used alone. The time required for film formation as a whole can be significantly shortened as compared with the case where it is formed.

Further, for example, when the microcrystalline semiconductor is formed after the amorphous semiconductor is formed, it is possible to prevent the lower layer from being reduced by hydrogen plasma at the time of forming the microcrystalline semiconductor, and at the same time, to form the semiconductor layer. In addition, the effect of being able to remove an amorphous semiconductor having a poor film quality at the initial stage of film formation and introducing an amorphous semiconductor having a good film quality is also obtained.

As described above, the method of manufacturing a coplanar type thin film transistor according to the fourth aspect of the present invention includes the step of forming a semiconductor layer at least a part of which in the film thickness direction includes a microcrystalline semiconductor on the insulating substrate, and the semiconductor layer. A step of forming an insulating film so as to cover the semiconductor layer, a step of forming a metal film and patterning to form a gate electrode, and a step of forming at least the gate electrode or the gate electrode and the resist on the mask as a mask. The structure includes a step of implanting an impurity into the microcrystalline semiconductor portion and a step of forming a source / drain electrode electrically connected to the semiconductor region into which the impurity is implanted by forming and patterning a metal film.

Therefore, since the impurity is injected into at least the microcrystalline semiconductor portion of the semiconductor layer at least a part of which in the film thickness direction is made of the microcrystalline semiconductor, the conductivity of the semiconductor region after the impurity implantation is amorphous. It is larger than the conventional case made of high quality semiconductor. As a result, the electron mobility is increased, so that the channel length can be surely and significantly shortened without forming a silicide, which is conventionally required to reduce the resistance.

A liquid crystal display device according to a fifth aspect of the present invention is configured to use the coplanar thin film transistor according to the first aspect as described above.

Therefore, the coplanar thin film transistor according to the first aspect can improve the on-current by about 1.5 times as compared with the conventional thin film transistor in which the amorphous semiconductor is formed. When the above coplanar thin film transistor is adopted in a liquid crystal display,
The aperture ratio of a 0.4-inch VGA (Video Graphics Array) can be improved from 60% in the past to 65%, and the liquid crystal display can be brightened. In addition, the increase in on-current also brings about an effect that it is possible to manufacture a liquid crystal display for an engineering workstation having 17-inch 1280 × 3 × 1024 picture elements, which has been difficult in the past.

[Brief description of the drawings]

1A to 1E are cross-sectional views showing a manufacturing process of a coplanar thin film transistor according to an embodiment of the present invention.

FIGS. 2A to 2E are cross-sectional views showing a manufacturing process of a coplanar thin film transistor according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between a film thickness of microcrystalline silicon and conductivity.

4A to 4E are cross-sectional views showing a manufacturing process of a coplanar thin film transistor according to still another embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the structure of a conventional inverted staggered thin film transistor.

6A to 6D are cross-sectional views showing a manufacturing process of a conventional inverted staggered thin film transistor.

[Explanation of symbols]

1 glass substrate (insulating substrate) 3 SiO ₂ insulating film (insulating film) 4 i-type microcrystalline silicon (microcrystalline semiconductor) 5 silicon nitride (Si ₃ N ₄ ) gate insulating film 6 gate electrode 7 source region 8 drain region 11 Source electrode 12 Drain electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toyohide Ayukawa 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka

Claims (5)

[Claims] 1. A semiconductor layer formed on an insulating substrate, a gate electrode formed on the semiconductor layer, a gate insulating film formed at least under the gate electrode, a source / drain region, and the source / drain region. In a coplanar thin film transistor including a drain region and a source / drain electrode electrically connected, at least a part of the semiconductor layer in the film thickness direction is a microcrystalline semiconductor, and the semiconductor layer except under the gate electrode A coplanar thin film transistor in which a source / drain region containing an impurity is formed in at least the microcrystalline semiconductor portion of the. 2. At least a part of the semiconductor layer in the film thickness direction is made of silicon germanium SiGe _x (0 ≦ x ≦).
1), silicon carbon SiC _x (0 ≦ x ≦ 1), silicon nitride Si ₃ N _x (0 ≦ x ≦ 4), silicon oxide Si
The coplanar type thin film transistor according to claim 1, which is made of a microcrystalline semiconductor of O _x (0 ≦ x ≦ 2). 3. The coplanar thin film transistor according to claim 1, wherein the semiconductor layer is formed by laminating an amorphous semiconductor and a microcrystalline semiconductor. 4. A step of forming a semiconductor layer at least a part of which in the film thickness direction includes a microcrystalline semiconductor on an insulating substrate, a step of forming an insulating film so as to cover the semiconductor layer, and forming and patterning a metal film. Thereby forming a gate electrode, a step of implanting impurities into at least the microcrystalline semiconductor portion of the semiconductor layer using the gate electrode or the gate electrode and the resist thereon as a mask, and forming and patterning a metal film. And a step of forming source / drain electrodes electrically connected to the semiconductor region into which the impurities are implanted. 5. A liquid crystal display device using the coplanar type thin film transistor according to claim 1.