KR100491820B1 - array substrate for a low temperature poly silicon liquid crystal display and fabrication method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device including a polycrystalline silicon thin film transistor and a manufacturing method thereof.

The present invention is a manufacturing method of simultaneously performing line forming and protective film etching using a diffraction exposure method when forming a top busline during the fabrication process of an array substrate fabricated with a top busline structure, and manufactured according to the manufacturing method of the present invention. An array substrate is proposed.

Since the manufacturing method according to the present invention as described above can save time and money, it is possible to enhance the price competitiveness of the product.

Description

Array substrate for a low temperature poly silicon liquid crystal display and fabrication method of the same}

The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a top bus line structure including a low temperature polysilicon thin film transistor and a method of manufacturing the same.

Low-temperature polysilicon is generally crystallized by irradiating a laser to amorphous silicon, which has several hundred times higher electric field mobility than amorphous silicon, and has a merit that it is possible to reduce the production cost and reduce the light and weight by mounting a driving circuit on a glass substrate. have.

The thin film transistor using the low temperature polysilicon as an active layer uses a coplanar structure in which a gate electrode is positioned on the active layer and is positioned in a plane centered on the source electrode, the drain electrode, and the active layer.

As described above, an array substrate for a liquid crystal display device including a thin film transistor having a coplanar structure and an active layer of polysilicon and a pixel electrode can be generally manufactured by a six mask process. The configuration of an array substrate for a liquid crystal display device having a line structure will be described schematically.

FIG. 1 is an enlarged plan view of an enlarged pixel of a liquid crystal display array substrate having a general top bus line structure.

First, the thin film transistor is positioned at the intersection of the data line 16 and the gate line 17. The thin film transistor includes the active layer 12, the source electrode 15a, the drain electrode 15b, and the gate line 17. It is made up of a gate electrode 18 connected from.

As shown in the drawing, a gate line extending in one direction and a data line defining a pixel area crossing vertically with the gate line are formed.

Thin film transistors formed of an active layer 12, a source electrode 15a, a drain electrode 15b, and a gate electrode 18 are formed at the intersections of the two wires. In this case, the data line 16 is connected to the source electrode 15a, and the gate line 17 is connected to the gate electrode 18. The gate electrode 18 is formed on the active layer. This is called the top bus line structure.

A method of manufacturing an array substrate for a liquid crystal display device configured as described above will now be described with reference to FIGS. 2A to 2F.

FIG. 2A illustrates a first mask process for forming an active layer, in which amorphous silicon is deposited on the substrate on which the buffer layer 10 is formed and then crystallized by a predetermined method.

The active layer 12 crystallized from the polysilicon is patterned by a first mask process to form an island-shaped active layer 12.

FIG. 2B illustrates a result of the second mask process of forming the gate electrode 18 on the active layer 12. The gate insulating film, which is a second insulating film, is formed on the entire surface of the substrate on which the active layer 12 is formed. After the deposition of the metal layer 14 and the metal layer, the gate electrode 18 is formed on the gate insulating layer 14 on the active layer 12 by patterning the second mask process. The material used for the metal layer is aluminum or aluminum alloy, and the gate insulating film uses a silicon nitride film or a silicon oxide film.

Subsequently, an ohmic contact region 13 is formed by implanting n + or p + ions into both sides of the active layer 12 where the gate electrode 18 is not located.

FIG. 2C is a view showing a result of a third mask process for forming a contact hole. An interlayer insulating film 22, which is a third insulating film, is formed on the entire surface of the substrate on which the gate electrode 18 is formed. The interlayer insulating layer 22 and the gate insulating layer 18 under the etching are etched to form a contact hole 19 exposing a part of the ohmic contact region 13.

FIG. 2D shows a fourth mask process for forming the data wiring (16 in FIG. 1) and the source and drain electrodes (15a and 15b in FIG. 1), wherein the interlayer insulating film 22 is formed. A metal layer is deposited on the entire surface, and is patterned by a fourth mask process to contact the exposed ohmic contact region 13 with the source electrode 15a and the drain electrode 15b, and the data wiring electrically connected to the source electrode 15a (Fig. 1 of 16).

FIG. 2E illustrates a result of a fifth mask process in which a contact hole (19 of FIG. 2C) is formed to expose a drain electrode, and is formed on the entire surface of the substrate 5 on which the source and drain electrodes 15a and 15b are formed. A protective film 26, which is a fourth insulating film, is formed and patterned in a fifth mask process so as to expose a portion of the drain electrode 15b.

FIG. 2F illustrates a result of a sixth mask process of forming the pixel electrode 28 in contact with the drain electrode 15b, and includes indium tin oxide and indium zinc oxide on the passivation layer 26. A transparent conductive metal is deposited and patterned by a sixth mask process to form a transparent pixel electrode 28 positioned in the pixel region while contacting the exposed drain electrode 15b.

However, since the conventional process as described above uses six masks, the process is complicated and it is difficult to be competitive in terms of time and cost.

The present invention is a conventional low-temperature polysilicon as described above In order to solve the problems appearing in the manufacturing process of the array substrate, an object of the present invention is to manufacture a liquid crystal display device having improved yield and price competitiveness by simplifying the process and saving time and cost.

In order to achieve the above object, a liquid crystal display using low temperature polysilicon according to the present invention includes a substrate; A buffer layer which is a first insulating film formed on the entire surface of the substrate; An island-shaped active layer formed on the buffer layer; A second insulating film stacked over the active layer; A gate electrode on the second insulating layer; Third and fourth insulating layers sequentially stacked on the gate electrode; Source and drain electrodes in contact with the active layers on both sides of the gate electrode; A pixel electrode is formed between the third and fourth insulating layers in contact with the drain electrode and not facing the active layer, and the active layer is crystallized through a laser annealing method.

In addition, an active region of the portion contacting the source and drain electrodes is an ohmic contact region, and the ohmic contact region is doped with n + or p + ions.

The ohmic contact region and the source and drain electrodes are contacted through a hole formed by patterning the second, third and fourth insulating layers stacked on the ohmic contact region, and the first, second, third and fourth insulating layers Silicon nitride film or silicon oxide film is a material.

The pixel electrode is made of indium tin oxide or indium zinc oxide.

Next, forming polysilicon on the substrate and forming an active layer using a first mask; Forming a source and a drain region in the active layer; Forming a gate electrode on the active layer using a second mask; Forming an interlayer insulating film on the gate electrode; Forming a pixel electrode on the interlayer insulating film by using a third mask; Forming an insulating layer on the pixel electrode; Forming first and second contact holes in the interlayer insulating layer and the insulating layer using a fourth mask to expose the source and drain regions of the active layer and the pixel electrode, respectively; After the formation of the first and second contact holes, continuously depositing a metal and a photoresist on the insulating layer; Using a fifth mask, partially patterning a boundary portion of the metal in contact with the source and drain regions through diffraction or partial exposure and performing a full exposure of the pixel region; Removing a metal part of the partially patterned region to form a source electrode and a drain electrode, wherein the partially exposed region of the fifth mask is a slit or monosilicide Alternatively, a silicon nitride film is laminated on the monosilicide.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

In accordance with another aspect of the present invention, a mask process is performed by applying a diffraction exposure method during fabrication of an array substrate to simplify the process.

3A to 3G, a method and a configuration of a liquid crystal display array substrate according to the present invention will be described.

 3A to 3G are cross-sectional views taken along the line AA ′ of FIG. 1 according to the process sequence of the present invention. (The planar configuration of the array substrate is similar to that of FIG. 1 and will be described with reference to this.)

First, FIG. 3A relates to a first mask process for forming an active layer. The amorphous silicon is deposited on the array substrate 105 on which the buffer layer 110 is deposited, and then crystallized by a predetermined method. Annealing methods are widely used.

Next, the crystallized active layer 112 is patterned in an island form using a first mask.

3B illustrates a gate mask 118 and a metal layer deposited on the substrate 105 on which the active layer 112 is formed, as shown in the second mask process, and the gate electrode 118 is formed using the second mask. do. Thereafter, an ohmic contact region 113 is formed through ion implantation.

A material used for the gate insulating film 114 is a silicon nitride film or a silicon oxide film, and the gate electrode 118 is made of aluminum or an aluminum alloy.

The ions implanted to form the ohmic contact region 113 are n-channel thin film transistors when n + ions are implanted into n + ions and p + ions, and p-channel thin film transistors when p + ions are implanted.

3C, an interlayer insulating film 122, which is a third insulating film, is formed on the entire surface of the substrate 105 on which the gate electrode 118 is formed, as shown in the third mask process.

Subsequently, a process of activating the ohmic contact region 113 into which ions are implanted is performed.

Next, a transparent conductive metal is deposited on the interlayer insulating layer 122 and the transparent conductive metal is patterned by using a third mask. As shown in the drawing, the pixel is removed by leaving a surface that does not correspond to the active layer 112. Electrode 128 is formed.

In this case, the material used as the pixel electrode is a transparent and conductive material as indium tin oxide or indium zinc oxide. In addition, the material used as the interlayer insulating film is deposited one selected from the group of inorganic insulating materials including silicon nitride film and silicon oxide film, or in some cases selected from the group of organic insulating materials including benzocyclobutene (BCB) and acrylic resin. Apply and form.

Next, FIG. 3D illustrates a fourth mask process, in which a fourth insulating layer 130 is deposited on the array substrate 105, and ohmic contact regions formed on both sides of the gate electrode using the fourth mask, respectively. The first contact hole 132a and the second contact hole 132b are formed to expose the third contact hole 133 which exposes a part of the pixel electrode 128 positioned adjacent to the active layer 112. Form.

Next, FIG. 3E illustrates a process of stacking a metal layer on the fourth insulating layer 130 and the first, second, and third contact holes 132a, 132b, and 133. The metal layer contacts the ohmic contact layer 113 and the pixel electrode 128 through the first, second, and third contact holes 132a, 132b, and 133. The ohmic contact layer 113 is implanted with n + or p + ions through ion doping or ion implantation.

FIG. 3F illustrates a fifth mask process in which a photoresist 138 is stacked on the metal layer 136, a fifth mask 139 is positioned on the top, and then light 137 is irradiated onto the mask 139. To expose the lower photoresist 138.

In this case, the fifth mask 139 to be used is composed of a blocking part 139a, a transmitting part 139c, and a transflective part 139b, and the transflective part 139b may form a slit, and is opaque such as mono silicide. It can be formed by depositing a material.

The transflective portion 139b of the mask is positioned to correspond to the region A which is a part of the region where the source electrode and the drain electrode are formed, and the transmissive portion 139c is positioned to correspond to the pixel region B. The blocking unit 139a is positioned corresponding to a region where a source electrode, a drain electrode, and a data line are formed later.

Subsequently, in FIG. 3G, the cross section which developed the photoresist exposed through the 5th mask was shown.

The area A corresponding to the transflective portion 139b of the above-described mask (139 in FIG. 3F) is partially exposed and partially removed the photoresist (PR) 138 as shown in the cross section. However, the area B corresponding to the transmission portion 139c is completely exposed so that the metal layer 136 is exposed.

 As shown in FIG. 3H, the exposed metal layer 136 and the fourth insulating layer 130 are sequentially removed.

The partially left pattern in the region A is formed through partial exposure, and when the metal layer 136 and the insulating layer 130 of the pixel region P are sequentially etched, the metal layer 136 and the insulating layer 130 of the region A are formed. Do not etch like this.

Next, as shown in FIG. 3I, when the photoresist 138 layer is ashed, the lower metal layer 136 is exposed by completely removing the photoresist 138 corresponding to the A region.

Next, as shown in FIG. 3J, when the exposed metal layer 136 is etched, the source electrode 134a and the drain electrode 134b that are spaced apart are formed. As a result, the array substrate including the thin film transistor and the pixel electrode of the liquid crystal display device using the top bus line structure is completed.

FIG. 4 is a cross-sectional view of a liquid crystal display device including an array substrate having a top bus line structure manufactured through the above process.

A liquid crystal display device in which a lower substrate 105 having a top bus line structure and an upper substrate 150 having a common electrode 142 are formed to face each other and are spaced apart from each other is illustrated. A thin film transistor including a gate electrode 118, a source electrode 134a, a drain electrode 134b, and an active layer 112 is positioned on the lower substrate 105.

The pixel electrode 128 is not opposed to the thin film transistor and is connected to the drain electrode 134b and is disposed under the metal layer 136 used as the source electrode 134a and the drain electrode 134b. The metal layer 136 and the pixel electrode 128 are divided around the fourth insulating layer.

Next, the upper substrate 150 has a black matrix 148, a color filter 146, and a planarization layer 144 disposed on the lower substrate, and the liquid crystal layer 140 has the lower substrate 105 and the upper substrate 150. ) Is formed in the middle of the gap.

As described above, using the thin film transistor array substrate having a top bus line structure can simplify the process and can be applied in various ways without departing from the spirit of the present invention.

As described above, the present invention is a manufacturing process of an array substrate for a liquid crystal display device using five masks by modifying a structure used in forming an array substrate using six existing masks, thereby reducing the process time by reducing the number of masks. And can reduce the process cost.

As a result, price competitiveness, which has been the biggest challenge in forming the lower substrate of the low temperature polysilicon liquid crystal display, can be improved.

1 is a plan view of a thin film transistor array substrate.

2A to 2F illustrate a process of forming a thin film transistor array substrate using six masks.

3A to 3J illustrate a process of forming a thin film transistor array substrate having a top bus line structure using five masks formed through the present invention.

4 is a cross-sectional view of an LCD including an array substrate having a top bus line structure using five masks formed by the present invention.

<Brief description of symbols for the main parts of the drawings>

105: lower substrate 112: active layer

118: gate electrode 134a: source electrode

134b: drain electrode 114: second insulating film

122: third insulating film 128: pixel electrode

130: fourth insulating film 136: metal layer

Claims (14)

A substrate; A buffer layer which is a first insulating film formed on the entire surface of the substrate; An island-like active layer formed on the buffer layer; A second insulating film stacked over the active layer; A gate electrode formed in the center of the active layer above the second insulating film; A third insulating film formed on the entire upper surface of the gate electrode; A pixel electrode formed on the third insulating film; A fourth insulating film formed on one side of the pixel electrode and on the third insulating film; A source electrode formed on the fourth insulating layer in contact with a lower active layer; A drain electrode spaced apart from the source electrode on the fourth insulating layer, in contact with the active layer, and at the same time in contact with the pixel electrode Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the active layer is crystallized through a laser annealing method. The method of claim 1, And an active region in contact with the source and drain electrodes is an ohmic contact region. The method of claim 3, wherein And the ohmic contact region is a region doped with n + or p + ions. The method of claim 4, wherein And the ohmic contact region and the source and drain electrodes are in contact with each other through holes formed by patterning the second, third and fourth insulating layers stacked on the ohmic contact region. The method of claim 1, And the first, second, third and fourth insulating films are silicon nitride films or silicon oxide films. The method of claim 1, The pixel electrode is an indium tin oxide or indium zinc oxide array substrate for a liquid crystal display device. Forming an active layer on the substrate using a first mask; Forming a source and a drain region in the active layer; Forming a first insulating film over the active layer on which the source and drain regions are formed; Forming a gate electrode on the first insulating layer by using a second mask corresponding to an active layer region excluding the source and drain regions; Forming a second insulating film on the gate electrode; Forming a pixel electrode on the second insulating layer using a third mask; Forming a third insulating film over the top of the pixel electrode and over the exposed second insulating film; Forming first to third contact holes in the second and third insulating layers using a fourth mask to expose the source and drain regions of the active layer and the pixel electrode, respectively; A source electrode continuously deposited on the third insulating layer including the first to third contact holes and spaced apart from each other by diffraction exposure using a fifth mask and contacting the active layer of the source region; Forming a drain electrode in contact with the active layer of the drain region and the pixel electrode at the same time Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 8, The partial exposure region of the fifth mask is a slit. The method of claim 8, The partial exposure region of the fifth mask is monosilicide Or a silicon nitride film laminated on top of monosilicide. The diffraction exposure using the fifth mask Continuously depositing a metal and a photoresist over the third insulating film; Using a fifth mask, partially patterning a boundary portion of the portion in contact with the source and drain regions of the metal through partial exposure and completely exposing the pixel region; Exposing the pixel electrode by removing the photoresist of the fully exposed pixel region and the metal underneath; Removing the photoresist of the partially exposed region to expose the metal portion; Removing the exposed metal parts to form source and drain electrodes spaced apart from each other; Method of manufacturing an array substrate for a liquid crystal display device comprising a. And forming a buffer layer between the substrate and the polysilicon layer. And the polysilicon layer is formed by laser annealing. Forming source and drain regions in the active layer Method of manufacturing an array substrate for a liquid crystal display device comprising the step of implanting n + or p + ions.