JPH10173197A - Thin film transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor which can be manufactured at a high throughput, by reducing the frequency to use the exposure masks. SOLUTION: After a source electrode 33A and a drain electrode 33B are formed on a transparent substrate 31, a semiconductor layer 35 is deposited on the substrate 31 and ions are implanted into the semiconductor layer 35 by using a first photoresist 34 which can be self-aligned with the electrodes 33A and 33B and is patterned on the semiconductor layer 35 as a mask. Since no exposure mask is required in the process for forming the ion implanting mask for the semiconductor layer 35, the throughput of a TFT can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter, referred to as TFT) and a method of manufacturing the same, and more particularly, to a TFT capable of forming a high-concentration impurity region in a self-aligned manner.

[0002]

2. Description of the Related Art Conventionally, a planar type TFT formed through steps shown in FIGS. 4 to 7 has been known. The TFT shown here is an example in which the TFT is connected to a pixel electrode formed in a display region of a liquid crystal display device.
In order to clarify the configuration and characteristics of this TFT, the description will be made in the order of the manufacturing process shown in the figure. First,
As shown in FIG. 4A, a base insulating film 2 and an intrinsic semiconductor layer 3 are sequentially deposited on a transparent substrate 1 made of, for example, glass. Then, the first photoresist 4 is patterned on the semiconductor layer 3 by photolithography as shown in FIG. 2A, and the semiconductor layer 3 and the base insulating film 2 are patterned using the first photoresist 4 as a mask. Is anisotropically etched to form an alignment mark A.

Next, after the first photoresist 4 is peeled off, as shown in FIG. 4B, a second photoresist 5 is newly applied and the second photoresist 5 is applied by photolithography.
After patterning the photoresist 5, using the second photoresist 5 as a mask, for example, boron (B) is ion-implanted under low-concentration conditions into the semiconductor layer 3 to be a source / drain region of the TFT to form a low-concentration impurity region. Form 3A.

After the second photoresist 5 is stripped off, FIG.
As shown in (c), a third photoresist 6 is newly applied, patterning is performed using photolithography technology, and ion implantation is performed under a high concentration condition to form a high concentration impurity region 3B. At this time, the high concentration impurity region 3B
, The above-described low-concentration impurity region 3A remains and L
It has a DD structure.

Thereafter, a new photolithography step is performed to pattern the fourth photoresist 7 as shown in FIG. Then, using the fourth photoresist 7 as a mask, the semiconductor layer 3 is anisotropically etched to process the island-shaped semiconductor layer 3.

Next, as shown in FIG. 5B, after depositing a gate insulating film 8 on the entire surface, a gate metal film 9 is deposited on the gate insulating film 8. After that, the fifth photoresist 10 is patterned by using the photolithography technique, and the gate metal film 9 is etched using the fifth photoresist 10 as a mask to form the gate electrode 9A and the auxiliary electrode 9B.

Further, as shown in FIG. 5 (c), after depositing an ITO (indium tin oxide) film 11 on the entire surface, a photolithography step is performed to perform the sixth photoresist 1
2 is patterned, and the pixel electrode 11A is processed based on the sixth photoresist 12.

Subsequently, as shown in FIG. 6A, after an interlayer insulating film 13 is deposited on the entire surface, a seventh photoresist 1 is formed.
4 is patterned using the seventh photoresist 14 as a mask to perform etching to reach the high-concentration impurity region 3B and the auxiliary electrode 9B.
6 is opened.

Next, as shown in FIG. 6B, after the seventh photoresist 14 is peeled off, a metal film 17 is deposited on the entire surface, and an eighth photoresist 18 is patterned thereon, thereby forming an eighth photoresist. The source electrode 17A and the drain electrode 17B are formed by performing anisotropic etching using the mask 18 as a mask.

Then, as shown in FIG. 7, after removing the eighth photoresist 18, a protective film 19 is deposited on the entire surface. Thereafter, a ninth photoresist 20 is patterned thereon, and the protection film 19 and the interlayer insulating film 13 are etched using the ninth photoresist 20 as a mask. Thus, the manufacture of the TFT 21 is substantially completed. As shown in FIG. 7, the TFT has a planar structure.

[0011]

However, in the above-described TFT 21, nine photolithography steps are required until the manufacture of the TFT 21 including the step of forming the alignment mark A is completed. 9
Use twice. As described above, since an exposure mask is required in each step, the manufacturing process is lengthened and the throughput is not good.

The problem to be solved by the present invention is that the number of times of use of the exposure mask is small and the T
What measures should be taken to obtain FT?

[0013]

According to the first aspect of the present invention,
A source electrode and a drain electrode made of a metal film are formed on a transparent substrate, and a semiconductor layer is formed over the source electrode and the drain electrode so as to cover a substrate between these electrodes and the two electrodes; An impurity region is formed in a portion of the layer above the source electrode and the drain electrode in a self-aligned manner, and a gate electrode is formed on the semiconductor layer via a gate insulating film. According to the first aspect of the present invention, a resist pattern self-aligned with the source electrode and the drain electrode is formed on the semiconductor layer by performing backside exposure using the source electrode and the drain electrode formed on the transparent substrate as a mask. be able to. By performing ion implantation using this resist, a semiconductor layer bonded to the source electrode and the drain electrode can be used as an impurity implantation region. With such a configuration, an exposure mask in a photolithography process can be eliminated. For this reason,
The TFT can be easily manufactured, and the throughput can be improved.

The invention according to claim 2 is characterized in that a wiring is connected to the source electrode or the drain electrode via a contact hole formed in the gate insulating film.

The invention according to claim 3 is characterized in that a pixel electrode is connected to one of the source electrode and the drain electrode.

According to a fourth aspect of the present invention, a low-concentration low-concentration impurity region is formed adjacent to the impurity region on the channel forming region side. The invention according to claim 5, wherein a source layer and a drain electrode patterned on a substrate and a semiconductor layer and a negative photoresist layer are sequentially deposited on the substrate, and the source electrode and the negative electrode are exposed from the lower side of the substrate. An impurity region is formed in the semiconductor layer using a resist layer provided on a portion other than the drain electrode as a mask. By applying such a manufacturing method, a semiconductor layer having a channel region between a source electrode and a drain electrode and an impurity region on the source electrode and the drain electrode is formed in a self-aligned manner without using a resist exposure mask. be able to.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, details of a TFT according to the present invention will be described based on an embodiment shown in the drawings. FIG.
FIGS. 3A to 3B are process cross-sectional views showing a process for manufacturing a TFT according to the present invention. In this embodiment, the present invention is applied to a TFT connected to a pixel electrode of a liquid crystal display device.

First, as shown in FIG. 1A, a base insulating film 32 made of SiO2 and a metal film 33 made of aluminum (Al-1% Si) are sequentially deposited on a transparent substrate 31 made of glass. Let it. After that, as shown in FIG.
4 is patterned. In this step, as the first photoresist 34, either a positive resist or a negative resist may be used. Using the first photoresist 34 as a mask, the metal film 33 is processed by performing anisotropic etching (for example, reactive ion etching) of the metal film 33, and the source electrode 33A and the drain electrode 33 are formed.
B, an alignment mark 33C, and the like are formed.
Note that the alignment mark 33C is formed in a region apart from the pixel region. After that, the first photoresist 34 is stripped.

Next, as shown in FIG. 1B, a semiconductor layer 35 made of intrinsic polysilicon is deposited on the entire surface. Subsequently, a negative-type second photoresist 36 is applied on the semiconductor layer 35, and a back surface exposure, development, and the like are performed by irradiating light from the back side of the transparent substrate 31, as shown in FIG. Self-aligned patterning is performed on the source electrode 33A and the drain electrode 33B. In this photolithography step, there is no need to prepare an exposure mask, and complicated steps such as mask alignment can be omitted. Then, using the second photoresist 36 as a mask, for example, arsenic (As) or phosphorus (P), which is an n-type impurity, is ion-implanted into the semiconductor layer 35 under a high-concentration condition, thereby forming an n-type high-concentration impurity region. Form 35A.

After the second photoresist 36 is peeled off, a third photoresist 37 is newly applied,
By performing development, a pattern of the third photoresist 37 as shown in FIG. 1C is formed. That is, the portion of the semiconductor layer 3 between the source electrode 33A and the drain electrode 33B
Patterning is performed such that a third photoresist 37 having a width smaller than the distance between the two electrodes is left in an intermediate portion on the upper surface of the fifth photoresist 5. And
Using this third photoresist 37 as a mask, n
For example, phosphorus (P), which is an n-type impurity, is ion-implanted into the semiconductor layer 35 under a low-concentration condition, so that
Form 5C. Thereby, the high concentration impurity region 35
The low-concentration impurity region 35C can be formed so as to be joined to A, whereby an LDD structure can be formed later. The region sandwiched between the low-concentration impurity regions 35C between the source electrode 33A and the drain electrode 33B remains an intrinsic semiconductor, and the channel formation region 35B
Becomes The high-concentration impurity region 35A is subjected to ion implantation under a low-concentration condition, but the sum of the dose amounts of the two ion implantations may be set in advance.

Next, after the third photoresist 37 is peeled off, the fourth photoresist 38 is patterned as shown in FIG. Fourth photoresist 38
Is formed so as to cover the inner half of the two high-concentration impurity regions 35A, the low-concentration impurity regions 35C, and the channel formation region 35B, as shown in FIG. And
The semiconductor layer 3 is formed by using the fourth photoresist 38 as a mask.
5 is performed to leave the island-shaped semiconductor layer 35. At this time, the outer halves of the source electrode 33A and the drain electrode 33B are exposed without being covered by the semiconductor layer 35.

Thereafter, the fourth photoresist 35 described above is used.
Then, an ITO film 39 is deposited on the entire surface. Further, a fifth photoresist 40 is applied on the ITO film 39 and is patterned to form a pattern as shown in FIG. Then, the fifth photoresist 40
Is used as a mask to etch the ITO film 39 to form the pixel electrode 39A. By this step, a structure in which the source electrode 33A and the pixel electrode 39A are connected is obtained.

Next, after the fifth photoresist 40 is peeled off, a gate insulating film 41 made of, for example, SiNx is deposited on the entire surface. Then, a sixth photoresist 42 is applied on the gate insulating film 41 and patterned by photolithography to form a resist pattern for forming a contact hole as shown in FIG. 2C. Thereafter, anisotropic etching is performed using the sixth photoresist 42 as a mask to form a contact hole 41A exposing the source electrode 33A in the gate insulating film 41.

Next, after the sixth photoresist 42 is stripped, a gate metal film 43 is deposited on the entire surface.
Thereafter, as shown in FIG. 3A, the seventh photoresist 44 is patterned, and the seventh photoresist 44 is patterned.
Is used as a mask to perform anisotropic etching to form a gate electrode 43A and a drain electrode wiring 43B.

After stripping the seventh photoresist 44, a protective film 45 made of, for example, SiNx is deposited on the entire surface. Thereafter, as shown in FIG. 3B, an eighth photoresist 46 is patterned on the protective film 45 by using a photolithography technique.
Is used as a mask, the protective film 45 and the gate insulating film 41 existing on the pixel electrode 39A are etched. Then, the eighth photoresist 46 is peeled off, and the manufacture of the TFT 47 of the present embodiment is completed.

The TFT of this embodiment performs the photolithography process eight times as described above. However, when exposing the second photoresist 36 for ion implantation of the high concentration impurity region 35A, the source electrode 33A is exposed. And the back surface is exposed using the drain electrode 33B as a mask,
The use of an exposure mask was reduced to seven times without the need for a separate exposure mask. Therefore, according to the present embodiment, the process can be simplified and the time can be reduced. Further, since the junction area between the source electrode 33A and the drain electrode 33B and the high-concentration impurity region 35A can be increased in the structure of the TFT, there is an advantage that the contact resistance can be reduced. In the TFT of the present embodiment, a source electrode 33A and a drain electrode 33B are patterned on the base insulating film 32, and a semiconductor layer 35 is formed on both the electrodes 33A and 33B. A high-concentration impurity region 35A is formed reflecting the patterns of both electrodes 33A and 33B. Therefore, the pixel electrode 39A
And the source electrode 33A to connect the
Even if the outer portion of the high-concentration impurity region 35A on A is removed, the contact resistance is greatly increased as compared with a conventional configuration in which a source electrode (or a drain electrode) is connected to a pixel electrode via a contact hole. Can be reduced. Similarly, in the drain electrode 33B, even if the outer portion of the high-concentration impurity region 35A is removed to connect the drain electrode wiring 43A, the semiconductor layer 35
And the contact area between the drain electrode 33B and the high-concentration impurity region 35A, the contact resistance can be sufficiently reduced.

As described above, in the present embodiment, it is possible to reduce the number of exposure masks used in the manufacturing process as compared with the conventional TFT, and to perform self-aligned patterning with high dimensional accuracy. it can. Therefore, according to the present embodiment, it is possible to realize a TFT having a good throughput and a high yield. Further, in the present embodiment, a photolithography process only for forming the alignment mark is not required, so that the number of processes can be further reduced.

When a TFT is formed as a switching element of a liquid crystal display device as in this embodiment,
There is an advantage that the connection with the pixel electrode can be facilitated and a structure in which a step on the TFT substrate side is suppressed can be achieved.

Although the embodiment has been described above, the present invention is not limited to this, and various modifications accompanying the gist of the configuration are possible. For example, in the above-described embodiment, the TFT is an n-channel transistor.
Of course, it is also possible to use a channel transistor.
In the above embodiment, polysilicon is used as the semiconductor layer, but amorphous silicon can be used. Further, in the step of performing the back surface exposure, a negative type photoresist is used, but in the other steps, either a positive type or a negative type may be used.

As is clear from the above description, according to the present invention, there is an effect that the number of times of use of the exposure mask is small and a TFT with good throughput is realized.

[Brief description of the drawings]

FIGS. 1A to 1C are process cross-sectional views showing an embodiment of a TFT according to the present invention.

FIGS. 2A to 2C are process cross-sectional views showing an embodiment of a TFT according to the present invention.

FIGS. 3A and 3B are process cross-sectional views showing an embodiment of a TFT according to the present invention.

FIGS. 4A to 4C are process cross-sectional views showing a conventional TFT manufacturing process.

FIGS. 5A to 5C are process cross-sectional views illustrating a conventional TFT manufacturing process.

FIGS. 6A and 6B are process cross-sectional views showing a manufacturing process of a conventional TFT.

FIG. 7 is a process sectional view showing a manufacturing process of a conventional TFT.

[Explanation of symbols]

 31 Transparent substrate 33 Metal film 33A Source electrode 33B Drain electrode 34 First photoresist 35 Semiconductor layer 35A High concentration impurity region 35B Channel formation region 35C Low concentration impurity region 36 Second photoresist 37 Third photoresist 38 Fourth photoresist 39A Pixel electrode 40 Fifth photoresist 41 Gate insulating film 42 Sixth photoresist 43A Gate electrode 43B Drain electrode wiring 44 Seventh photoresist 45 Protective film 46 Eighth photoresist

Claims (5)

[Claims] A source electrode and a drain electrode formed of a metal film are formed on a transparent substrate, and a semiconductor layer is formed over the source electrode and the drain electrode so as to cover these electrodes and a substrate between both electrodes. And an impurity region is formed in a portion of the semiconductor layer above the source electrode and the drain electrode in a self-aligned manner, and a gate electrode is formed on the semiconductor layer via a gate insulating film. Thin film transistor. 2. A wiring is connected to the source electrode or the drain electrode via a contact hole formed in the gate insulating film.
The thin film transistor as described in the above. 3. The thin film transistor according to claim 1, wherein a pixel electrode is connected to one of said source electrode and said drain electrode. 4. The thin film transistor according to claim 1, wherein a low-concentration low-concentration impurity region is formed adjacent to the impurity region on the channel forming region side. 5. A source electrode and a drain electrode patterned on a substrate, a semiconductor layer and a negative photoresist layer are sequentially deposited on the substrate, and the source electrode and the drain electrode are exposed from the lower side of the substrate. A method for manufacturing a thin film transistor, comprising forming an impurity region in the semiconductor layer using a resist layer provided other than above as a mask.