JP4535921B2 - Thin film transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a thin film transistor in which low impurity concentration regions are provided on both sides of a channel region and a method for manufacturing the same.

  In recent years, a liquid crystal display in which this type of thin film transistor (TFT) is provided as a drive circuit in the periphery of an image display area and an organic EL (ElectroLuminescence) display have a high density of pixels provided in a matrix in the image display area. As the number of thin film transistors increases and the functions of peripheral circuits provided in the periphery of the image display area increase, the number of thin film transistors increases. Further, as the number of thin film transistors increases, the width of the frame that is the peripheral portion of the image display area increases. In order to prevent the increase in the frame width, it is necessary to reduce the pattern of the image display area.

  And as a liquid crystal display provided with this kind of thin film transistor, an undercoat layer is laminated on an insulating substrate, and a semiconductor layer is laminated on this undercoat layer. On both sides of the channel region of this semiconductor layer, LDD (Lightly Doped Drain) regions doped with impurities implanted at a low concentration are provided. Further, a source region and a drain region into which impurities are implanted at a high concentration are provided on both sides of these LDD regions. Further, a gate insulating film is stacked on the undercoat layer including the semiconductor layer, and a gate electrode is provided on the gate insulating film facing the channel region of the semiconductor layer.

An interlayer insulating film is stacked on the gate insulating film including these gate electrodes. In the interlayer insulating film and the gate insulating film, contact holes penetrating the source region and the drain region of the semiconductor layer are formed. A drain electrode is provided on the interlayer insulating film including the contact hole communicating with the source region of the semiconductor layer, and the source electrode is provided on the interlayer insulating film including the contact hole penetrating the drain region of the semiconductor layer. There is known a configuration in which a thin film transistor is provided by stacking layers (see, for example, Patent Document 1).
JP-A-11-274502

  However, also in the above-described liquid crystal display, it is necessary to reduce the width of the semiconductor layer of the thin film transistor in order to reduce the outer size. In order to reduce the width of the semiconductor layer, the contact hole interval must be reduced. However, when the distance between the contact holes is reduced, the variation in the current value of the thin film transistor increases rapidly.

That is, when the distance between the contact holes of these thin film transistors is reduced, the distance between the LDD region and the contact hole of each of these thin film transistors is reduced. In a thin film transistor in which the distance between the LDD region and the contact hole is narrowed, when a mask misalignment occurs when forming the contact hole, the sheet resistance of the LDD region is generated in the source region and the drain region. Compared to several tens Ω / cm ² to several hundreds Ω / cm ² , the extraction resistance varies greatly due to variations in the length of these LDD regions, so the variation in the current value of the thin film transistor is very large. turn into.

  Therefore, in order to prevent variations in the current value of the thin film transistor, the LDD region is formed large by the maximum width of the misalignment of the contact hole forming mask between the end of the LDD region and the contact hole. In addition, even if misalignment occurs during the formation of these contact holes, it may be possible to reduce the change in the drawing resistance. However, in this case as well, the outer size of the semiconductor layer of the thin film transistor cannot be reduced. Has the problem that it is not easy.

  The present invention has been made in view of these points, and an object of the present invention is to provide a thin film transistor in which a change in resistance is small and a semiconductor layer can be made small, and a manufacturing method thereof.

The present invention includes a channel region, a low impurity concentration region provided on both sides of the channel region, and a high impurity concentration region provided on both sides of the low impurity concentration region and having a higher impurity concentration than the low impurity concentration region. a semiconductor layer, a semiconductor layer provided in the insulating layer, a gate electrode provided apart opposed via the insulating layer on the channel region of the semiconductor layer, the semiconductor layer high in the insulating layer At least a part of each of the low impurity concentration region and the high impurity concentration region is opened in a state where a part smaller than the interval between the impurity concentration regions is provided and the part is located in the low impurity concentration region of the semiconductor layer. a pair of openings, the semiconductor disposed on said insulating layer containing said apertures through each other a small distance than the spacing between the high impurity concentration region of said semiconductor layer Some in the low impurity concentration regions of those provided with the source electrode and the drain electrode electrically connected to each of these low impurity concentration region and the high impurity concentration region in a state where the position.

Then, a pair of openings for opening at least a part of each of the low impurity concentration region and the high impurity concentration region in a state where a part is located in the low impurity concentration region of the semiconductor layer in the insulating layer provided on the semiconductor layer Are provided with an interval smaller than the interval between the high impurity concentration regions of the semiconductor layer , and on the insulating layer including the pair of openings, with an interval smaller than the interval between the high impurity concentration regions of the semiconductor layer. A source electrode and a drain electrode were provided, and the source electrode and the drain electrode were conducted to the low impurity concentration region and the high impurity concentration region, respectively. As a result, even if there is a shift in providing the source electrode and the drain electrode, the extraction resistance of the source electrode and the drain electrode becomes the resistance value of the low impurity concentration region. Therefore, changes in the drawing resistance of each of the source electrode and the drain electrode are reduced. In addition, by providing a source electrode and a drain electrode with a distance smaller than the distance between the high impurity concentration regions of the semiconductor layer being partially located in the low impurity concentration region of the semiconductor layer, the source electrodes Since the space between the drain electrode and the drain electrode becomes small, the semiconductor layer becomes small.

  According to the present invention, even if the source electrode and the drain electrode are displaced, the extraction resistance of the source electrode and the drain electrode is the resistance value of the low impurity concentration region. Since the change can be reduced and the space between the source electrode and the drain electrode can be reduced, the semiconductor layer can be reduced.

  Hereinafter, the configuration of the liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS.

In FIG. 1, reference numeral 1 denotes a liquid crystal display 1 as a liquid crystal display. The liquid crystal display 1 is a flat display device and includes a top gate type array substrate 2 which is a substantially rectangular flat plate active matrix type as a circuit substrate. I have. The array substrate 2 has a glass substrate 3 which is a light-transmitting substrate as a substantially transparent rectangular flat plate-like insulating substrate. An undercoat layer (not shown) composed of a silicon nitride film (SiN _x ), a silicon oxide film (SiO _x ) or the like is laminated on the surface which is one main surface of the glass substrate 3. . This undercoat layer prevents diffusion of impurities into each element formed on the glass substrate 3.

  On the undercoat layer, a plurality of n-type thin film transistors (TFTs) 4 that are switching elements for pixel circuits are formed in a matrix. Each of these thin film transistors 4 includes an active layer 5 as a semiconductor layer formed on the undercoat layer. The active layer 5 is composed of a polysilicon layer having a thickness of 50 nm as a polycrystalline semiconductor. This polysilicon layer is subjected to laser annealing by irradiating an amorphous silicon layer having a film thickness of 50 nm as an amorphous semiconductor which is a non-single crystal semiconductor with an excimer laser beam by a plasma CVD (Chemical Vapor Deposition) method. It is formed by melt recrystallization.

The active layer 5 has a channel region 11 which is a p ⁻ region provided in the central portion of the active layer 5. On both sides of the channel region 11, a source region 12 and a drain region 13 as high impurity concentration regions as electrode portions which are n ⁺ regions are provided to face each other. These source region 12 and drain region 13 are contact regions as lead portions, and are formed as phosphorus (P) as impurities at a high concentration at a predetermined low acceleration voltage on both sides of a portion that becomes the channel region 11 of the active layer 5. It is formed by doping with implanted.

Further, LDD regions 14 and 15 as LDD (Lightly Doped Drain) portions which are n ⁻ regions as low impurity concentration regions are formed between the channel region 11 of the thin film transistor 4 and the source region 12 and the drain region 13. ing. The LDD regions 14 and 15 are configured by doping and doping phosphorus (P) as an impurity at a low concentration from the source region 12 and the drain region 13. Therefore, these LDD regions have a higher sheet resistance than the source region 12 and the drain region 13. Specifically, these LDD regions have a sheet resistance of about several tens Ω / cm ² to several hundreds Ω / cm ² . The LDD regions 14 and 15 are formed by implanting impurities at a low concentration at a predetermined high acceleration voltage into the active layer 5 located inside the source region 12 and the drain region 13 and outside the channel region 11. Formed by doping.

  That is, these LDD regions 14 and 15 are continuously provided on both sides of the channel region 11 of each thin film transistor 4. A source region 12 and a drain region 13 are continuously provided on both sides of the LDD regions 14 and 15. Here, each of the source region 12 and the drain region 13 is configured such that the impurity concentration is higher than that of the LDD regions 14 and 15 and the impurity concentration is higher.

Further, on the undercoat layer including each of the channel region 11, the source region 12, the drain region 13, and the LDD regions 14 and 15, a gate insulating film 16 made of an insulating silicon oxide film is laminated. The film is formed. The gate insulating film 16 is a gate insulating layer as a first insulating film, and is formed by stacking about 100 nm of silicon oxide (SiO ₂ ) by plasma CVD.

  Further, the gate electrode 20 is laminated and formed on the gate insulating film 16 facing each channel region 11. The gate electrode 20 is provided so as to be opposed to the channel region 11 and is provided inside the LDD regions 14 and 15. The gate electrode 20 is formed by laminating molybdenum (Mo), tungsten (W), aluminum (Al), or an alloy thereof such as molybdenum-tungsten alloy (MoW alloy) to a thickness of about 300 nm. The gate electrode 20 is opposed to the channel region 11 of each thin film transistor 4 through the gate insulating film 16, and has a gate length that is approximately equal to the width of the channel region 11.

Further, on the gate insulating film 16 including the gate electrode 20 of each thin film transistor 4, an interlayer insulating film 21 as an interlayer insulating layer made of an insulating silicon oxide film is laminated and formed. . The interlayer insulating film 21 is a second insulating film as a second insulating layer, and is formed by stacking a silicon oxide (SiO ₂ ) film with a thickness of 600 nm by a plasma CVD method.

  The interlayer insulating film 21 and the gate insulating film 16 are provided with a plurality of contact holes 22 and 23 that are openings as conductive parts penetrating through the interlayer insulating film 21 and the gate insulating film 16, respectively. It has been. These contact holes 22 and 23 are contact portions formed in a circular cross section as shown in FIG. Here, each of these contact holes 22 and 23 is on both sides of the gate electrode 20 of each thin film transistor 4, and is a lead portion between each LDD region 14, 15 of this thin film transistor 4 and the source region 12 and drain region 13. It is provided on certain boundaries 17,18.

  Specifically, the contact hole 22 is electrically connected to each of the LDD region 14 and the source region 12 and opens a part of each of the LDD region 14 and the source region 12 in the vicinity of the boundary portion 17. Similarly, the contact hole 23 is electrically connected to each of the LDD region 15 and the drain region 13 and opens a part of each of the LDD region 15 and the drain region 13 in the vicinity of the boundary portion 18. Further, these contact holes 22 and 23 are provided for extracting the source electrode 24 and the drain electrode 25 from the source region 12 and the drain region 13, respectively.

  The contact hole 22 is provided at a constant interval so that the boundary 17 between the source region 12 and the LDD region 14 is located in the middle of the contact hole 22. The contact hole 23 is provided so that the boundary 18 between the drain region 13 and the LDD region 15 is located in the middle of the contact hole 23. Specifically, the contact holes 22 and 23 are shifted from the inner side of the source region 12 or the drain region 13 toward the outer side of the LDD regions 14 and 15 by about ¼ of the diameter of the contact holes 22 and 23. In the position.

  The contact holes 22 and 23 are provided on the boundary portions 17 and 18 straddling the source region 12 or the drain region 13 and the LDD regions 14 and 15. That is, these contact holes 22 and 23 straddle the boundary portions 17 and 18 between the LDD regions 14 and 15 and the source region 12 or the drain region 13, and a part of the contact holes 22 and 23 is formed in the LDD region. It is provided so that it may be located on 14,15.

  Here, the contact holes 22 and 23 are arranged such that the distance A between the inner edges of the contact holes 22 and 23 is only an amount of misalignment from the end of the gate electrode 20. In other words, the LDD regions 14 and 15 are configured such that the drawing resistance from the source electrode 24 and the drain electrode 25 does not change even when the contact holes 22 and 23 are misaligned. That is, the LDD regions 14 and 15 have a total LDD length, which is a width dimension of the left and right LDD regions 14 and 15 located on both sides of the channel region 11, from the distance between the contact holes 22 and 23. It is installed in the length dimension minus 20 gate lengths.

  Further, as shown in FIG. 2, the distance A between the inner edges of the contact holes 22 and 23 is between the outer edges of the LDD regions 14 and 15 and the inner edges of the source region 12 and the drain region 13. It is comprised smaller than the space | interval B which is between. Further, the distance A between the contact holes 22 and 23 is larger than the distance C which is between the inner edges of the LDD regions 14 and 15 and is the gate length of the gate electrode 20. The distance D between the centers of the contact holes 22 and 23 is larger than the distance A and smaller than the distance E between the outer edges of the source region 12 and the drain region 13. Further, the distance F between the outer edges of the contact holes 22 and 23 is also larger than the distance A and smaller than the distance E. The radius R of these contact holes 22 and 23 is about two thirds of the width dimension W of the active layer 5.

  Further, a source electrode 24 that is a signal line is provided in a contact hole 22 that communicates with a boundary portion 17 between the source region 12 of each thin film transistor 4 and the LDD region 14 located inside the source region 12. It has been. These source electrodes 24 are electrically connected and conducted to the source region 12 and the LDD region 14 of the thin film transistor 4 through the contact holes 22, respectively.

  Further, as shown in FIG. 1, a drain electrode as a signal line is formed in a contact hole 23 communicating with a boundary portion 18 between the drain region 13 of each thin film transistor 4 and the LDD region 15 located inside the drain region 13. 25 are provided in a stacked manner. These drain electrodes 25 are electrically connected to and electrically connected to the drain region 13 and the LDD region 15 of the thin film transistor 4 through the contact holes 23, respectively.

  Then, on the interlayer insulating film 21 including each of the source electrode 24 and the drain electrode 25 of each thin film transistor 4, a passivation film 26 as a protective film made of a silicon nitride (SiN) film so as to cover these thin film transistors 4. Are stacked to form a film. The passivation film 26 is provided with a contact hole 27 as a conductive portion that penetrates the passivation film 26 and opens at least a part of the source electrode 24. The contact hole 27 communicates with the source electrode 24 of the thin film transistor 4.

  Further, a pixel electrode 28 controlled by the thin film transistor 4 is laminated and formed on the passivation film 26 including the contact hole 27. The pixel electrode 28 is electrically connected to the drain electrode 25 of the thin film transistor 4 through the contact hole 27 to be conductive. Further, an alignment film 29 is laminated and formed on the passivation film 26 including the pixel electrode 28.

  On the other hand, a rectangular flat plate-like counter substrate 31 as a common substrate is disposed facing the array substrate 2. The counter substrate 31 includes a glass substrate 32 which is a substantially transparent rectangular flat plate-like insulating substrate. On one main surface of the glass substrate 32 facing the array substrate 2, a counter electrode 33 as a common electrode is laminated and formed. An alignment film 34 is laminated on the counter electrode 33. A liquid crystal layer 36 is formed as a light modulation layer between the alignment film 34 of the counter substrate 31 and the alignment film 29 of the array substrate 2.

  Further, on the opposite side of the array substrate 2 from the side on which the counter substrate 31 is disposed facing, a backlight (not shown) as a back light source is disposed facing the array substrate 2. The backlight makes planar light incident on the array substrate 2, and the image displayed on the array substrate 2 is made visible by controlling the pixel electrodes 28 by the thin film transistors 4 on the array substrate 2.

  Next, a method for manufacturing the liquid crystal display according to the first embodiment will be described.

  First, after forming an undercoat layer on the glass substrate 3, an amorphous silicon film (not shown) having a thickness of 50 nm, which is an amorphous semiconductor layer, is deposited on the undercoat layer by plasma CVD.

  Thereafter, the amorphous silicon film is irradiated with excimer laser light and laser annealed to melt and recrystallize the amorphous silicon film to form polysilicon having a thickness of 50 nm, and then dry etching as shown in FIG. To form an island-shaped active layer 5.

Next, after forming a resist layer (not shown) on the active layer 5, the resist layer is subjected to dry etching with tetrafluoromethane (CF ₄ ) gas and patterned to form a channel which is a central portion of the active layer 5. A resist mask 42 for etching is formed on the regions 11 and LDD regions 14 and 15.

In this state, using this resist mask 42 as a mask, as shown in FIG. 4, for example, an impurity which is a dopant such as phosphorus (P) is used to form the source region 12 and the drain region 13 of the active layer 5 by ion doping. The source region 12 and the drain region 13 of the thin film transistor 4 are formed by ion doping to form an n ⁺ region.

  Thereafter, the resist mask 42 on each active layer 5 is removed by etching.

  Next, a gate insulating film 16 having a thickness of 100 nm is formed on one surface on the undercoat layer including each active layer 5 by plasma CVD or the like.

  Thereafter, for example, a molybdenum-tungsten (MoW) alloy is formed on one surface of the gate insulating film 16 by sputtering and then patterned by dry etching. As shown in FIG. A gate electrode 20 having a film thickness of 300 nm is formed on the region 11.

  At this time, the gate electrode 20 is patterned so as to be smaller than the region where impurities are implanted at a high concentration, and is formed to have a gate length smaller than the width dimension of the resist mask 42.

In this state, as shown in FIG. 6, by the self-alignment method using the gate electrode 20, the portions that become the LDD regions 14, 15 of the active layer 5, the source region 12 and the drain region using the gate electrode 20 as a mask. Impurities that are dopants such as phosphorus (P) are ion-doped by ion doping to each of 13 to form n ⁻ regions, and the LDD regions 14 and 15 of the thin film transistor 4 are formed.

  At this time, the active layer 5 located between the LDD regions 14 and 15 becomes the channel region 11.

  Next, the respective impurities in the source region 12, the drain region 13, and the LDD regions 14 and 15 are activated by thermal annealing at a temperature of 500 ° C. for 1 hour.

  Thereafter, an interlayer insulating film 21 having a thickness of 600 nm is formed on one surface of the gate insulating film 16 including the gate electrode 20 by plasma CVD, and then the interlayer insulating film 21 and the gate insulating film are insulated as shown in FIG. Contact holes 22 and 23 are formed in the film 16 using a photomask (not shown) through the space A, and the boundary 17 between the source region 12 and the LDD region 14 and the boundary 18 between the drain region 13 and the LDD region 15 are formed. Expose each one.

  In this state, after a metal film having a thickness of 500 nm is formed on one surface of the interlayer insulating film 21 including the contact holes 22 and 23, the metal film is patterned to form the source electrode 24 as shown in FIG. Then, the drain electrode 25 and the drain electrode 25 are formed to complete the thin film transistor 4 of the liquid crystal display 1.

  Further, as shown in FIG. 1, after forming a passivation film 26 on the interlayer insulating film 21 including each of the source electrode 24 and the drain electrode 25, a contact hole 27 is formed in the passivation film 26, and the thin film transistor 4 is formed. The drain electrode 25 is exposed.

  In this state, after the pixel electrode 28 is formed on the passivation film 26 including the contact hole 27, the alignment film 29 is formed on the passivation film 26 including the pixel electrode 28, thereby completing the array substrate 2.

  Further, after attaching the alignment film 34 side of the counter substrate 31 to the alignment film 29 side of the array substrate 2, a liquid crystal is interposed between the alignment film 29 of the array substrate 2 and the alignment film 34 of the counter substrate 31. The liquid crystal display 1 formed by interposing the layer 36 is completed.

  Thereafter, the backlight is attached to the back side of the array substrate 2 of the liquid crystal display 1 so as to face the back surface.

  As described above, according to the first embodiment, the contact holes 22 and 23 are arranged via the distance A smaller than the distance B between the source region 12 and the drain region 13 in which the impurity of each thin film transistor 4 is heavily doped. And the boundary portions 17 and 18 which are the boundaries between the LDD regions 14 and 15 doped with the impurities of each thin film transistor 4 and the source region 12 and the drain region 13 are exposed at the contact holes 22 and 23, respectively. Let Then, the source electrode 24 and the drain electrode 25 laminated on the interlayer insulating film 21 including the contact holes 22 and 23 are respectively connected to the boundary portions 17 and 15 between the source region 12 or the drain region 13 and the LDD regions 14 and 15. 18 was laminated.

  As a result, the sum (A−C) of the LDD lengths of the LDD regions 14 and 15 is the gate length of the gate electrode 20 from the distance A between the contact holes 22 and 23 of the photomask when the contact holes 22 and 23 are formed. It is determined by a value obtained by subtracting a certain interval C. For this reason, even if this photomask is displaced and contact holes 22 and 23 are formed, that is, when misalignment occurs when forming these contact holes 22 and 23, The lead-out resistance of the source electrode 24 and the drain electrode 25 formed in the above becomes the resistance value of the LDD regions 14 and 15. Therefore, changes in the drawing resistances of the source electrode 24 and the drain electrode 25 can be reduced, and fluctuations in the current value of the thin film transistor 4 due to misalignment when the contact holes 22 and 23 are formed can be reduced.

  Further, contact holes 22 and 23 are provided on the boundary portions 17 and 18 between the LDD regions 14 and 15 and the source region 12 and the drain region 13, and the source electrode is formed on the interlayer insulating film 21 including the contact holes 22 and 23. By laminating 24 and the drain electrode 25, the distance A between the contact holes 22 and 23 is greatly shortened to be smaller than the distance B which is the LDD width between the LDD regions 14 and 15. Therefore, since the outer size of the active layer 5 including the LDD regions 14 and 15 can be reduced, the outer size of the thin film transistor 4 including the active layer 5 can be reduced.

  In the first embodiment, the contact holes 22 and 23 of each thin film transistor 4 are formed in a circular cross section. However, as in the second embodiment shown in FIGS. 9 and 10, these contact holes 22 are formed. , 23 can also be formed. As shown in FIG. 9, the contact holes 22 and 23 are formed so that the length L of one side is about two thirds of the width dimension W of the active layer 5.

  Further, these contact holes 22 and 23 are provided by using a photomask 51 shown in FIG. 10 when a resist pattern of these contact holes 22 and 23 is formed. The photomask 51 is formed with a pair of openings 52 and 53 which are equal in size to the contact holes 22 and 23 and are spaced apart from each other by an interval equal to the interval A between the contact holes 22 and 23. These openings 52 and 53 are formed in a square shape equal to the cross-sectional shape of each contact hole 22 and 23.

  As a result, by making the contact holes 22 and 23 have a square cross section, the same operational effects as in the first embodiment can be obtained. Furthermore, the change in the extraction resistance between the source electrode 24 and the drain electrode 25 through these contact holes 22 and 23 can be made smaller, and the variation in the current value of the thin film transistor 4 due to the misalignment at the time of forming these contact holes 22 and 23 is also greater. Less.

  In each of the above embodiments, the same effect as in each of the above embodiments can be obtained by using, for example, boron (B) as an impurity to be implanted into the source region 12, the drain region 13, and the LDD regions 14 and 15. A P-type thin film transistor can also be formed.

  Furthermore, although the thin film transistor 4 used for the array substrate 2 of the liquid crystal display 1 has been described, even a thin film transistor used for an organic EL display using an organic EL (ElectroLuminescence) element as a light modulation layer may be used correspondingly. it can.

1 is an explanatory cross-sectional view showing a first embodiment of a thin film transistor of the present invention. It is an explanatory top view which shows a thin-film transistor same as the above. It is explanatory sectional drawing which shows the state in which the semiconductor layer of the thin-film transistor same as the above was formed. It is explanatory sectional drawing which shows the state which forms the high impurity concentration area | region of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the state which formed the gate electrode of the thin-film transistor same as the above. It is explanatory sectional drawing which shows the state which forms the low impurity concentration area | region of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the state which formed a pair of opening part in the insulating layer of a thin-film transistor same as the above. It is explanatory sectional drawing which shows the state in which the thin-film transistor same as the above was formed. It is an explanatory top view which shows 2nd Embodiment of the thin-film transistor of this invention. It is an explanatory top view which shows the mask used when forming the opening part of a thin-film transistor same as the above.

Explanation of symbols

4 Thin film transistor 5 Active layer as semiconductor layer
11 channel region
12 Source region as high impurity concentration region
13 Drain region as high impurity concentration region
14,15 LDD region as low impurity concentration region
16 Gate insulating film as an insulating layer
20 Gate electrode
21 Interlayer insulation film which is an interlayer insulation layer
22,23 Contact hole as opening
24 source electrode
25 Drain electrode
42 Resist mask as resist A Interval B Interval

Claims (2)

A semiconductor layer including a channel region, a low impurity concentration region provided on both sides of the channel region, and a high impurity concentration region having a higher impurity concentration than the low impurity concentration region provided on both sides of the low impurity concentration region;
An insulating layer provided on the semiconductor layer;
A gate electrode provided apart opposed via the insulating layer on the channel region of the semiconductor layer,
The low impurity concentration region and the high impurity concentration region which are provided in the insulating layer with a space smaller than the space between the high impurity concentration regions of the semiconductor layer and partially located in the low impurity concentration region of the semiconductor layer. A pair of openings that open at least a portion of each of
The low impurity concentration in a state where a part of the semiconductor layer is located in the low impurity concentration region of the semiconductor layer and is provided on the insulating layer including the opening through a space smaller than the space between the high impurity concentration regions of the semiconductor layer. A thin film transistor comprising: a source electrode and a drain electrode which are electrically connected to each of a region and a high impurity concentration region . Forming a semiconductor layer,
Form a resist on the center of this semiconductor layer,
Using this resist as a mask, impurities are implanted at a high concentration on both sides of the semiconductor layer to form a high impurity concentration region,
Remove the resist,
Forming an insulating layer on the semiconductor layer;
Forming a gate electrode having a width smaller than the width of the resist on the insulating layer opposed to the central portion of the semiconductor layer;
Using this gate electrode as a mask, impurities are implanted at low concentrations on both sides of the semiconductor layer to form low impurity concentration regions inside the high impurity concentration regions, and the semiconductor layer between these low impurity concentration regions is channel region. age,
Forming an interlayer insulating layer on the insulating layer including the gate electrode;
A pair of openings for opening at least a part of each of the high impurity concentration region and the low impurity concentration region in a state where a part is located in the low impurity concentration region of the semiconductor layer through the interlayer insulating layer and the insulating layer Are formed through each other at an interval smaller than the interval between the high impurity concentration regions,
A method of manufacturing a thin film transistor, comprising: forming a source electrode and a drain electrode that are electrically connected to each of the high impurity concentration region and the low impurity concentration region on the interlayer insulating layer including the opening.

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