KR101258080B1 - Liquid crystal display device and method for fabricating thereof - Google Patents

Abstract

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a structure of a polysilicon liquid crystal display device and a method for manufacturing the same. In particular, in the forming of the pixel electrode, the insulating layer formed in the display area of the unit pixel is removed to form a negative pattern in the display area, and the photosensitive film is filled and ashed in the negative area to form a predetermined pattern. By forming the pixel electrode without using a mask using the principle of forming, the effect of reducing the manufacturing process of the entire liquid crystal display device is obtained.

Polysilicon, liquid crystal display, pixel electrode

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THEREOF}

1 is a schematic plan view of a liquid crystal display panel integrated with a driving circuit unit;

2 is a plan view of a unit pixel of a conventional polysilicon liquid crystal display device;

3A to 3H are cross-sectional views sequentially illustrating a manufacturing process of a conventional polysilicon liquid crystal display device.

4A is a plan view showing a unit pixel of a liquid crystal display of the present invention.

4B is a cross-sectional view of a unit pixel of the liquid crystal display device of the present invention.

5A to 5M are cross-sectional views sequentially illustrating a manufacturing process of a liquid crystal display device of the present invention.

*********** Description of the symbols for the main parts of the drawings ***********

401: active pattern 402: gate line

402a: gate electrode 403: storage line

404: data line 405: source electrode

406: drain electrode 410: pixel electrode

420 insulating layer 460 display area

470: switch area 502, 503, 504: insulating layer

The present invention relates to a structure of a polysilicon liquid crystal display device and a method of manufacturing the same, and more particularly, to a method of manufacturing a liquid crystal display device to reduce the number of masks used in the pixel electrode forming step.

A separate liquid crystal display device having a separate driving circuit unit may be divided into a screen display unit on which an image is displayed and a driving circuit unit driving the screen display unit. The screen display unit and the driving circuit unit are connected to each other through a tape carrier package (TCP).

On the other hand, in the liquid crystal display device in which the driving circuit unit is integrated, the driving circuit unit and the screen display unit are formed on the same substrate. Therefore, the manufacturing process of the liquid crystal display device integrated with the driving circuit part is more convenient than the liquid crystal display device with the driving circuit part.

However, in order to construct a liquid crystal display device integrated with a driving circuit unit, a polysilicon thin film transistor having fine and excellent operating characteristics should be used. In addition, the liquid crystal display device employing the polysilicon thin film transistor is excellent in mobility compared to the liquid crystal display device using the amorphous silicon thin film transistor, and is suitable for manufacturing a liquid crystal display device requiring high-speed operation. Generally, the electrical mobility of amorphous thin film transistors (TFTs) is about 0.1-1 cm 2 / V sec, whereas the electrical mobility of polysilicon TFTs manufactured using excimer lasers is higher than 100 cm 2 / Vsec. Has

The driving circuit unit integrated liquid crystal display device using the polysilicon thin film transistor will be described with reference to FIG. 1.

Referring to FIG. 1, a driving circuit region for driving elements of the screen display unit, which is formed on the screen display unit 120 in which the unit pixels are arranged in a matrix form on a substrate 100 such as glass, and is formed outside the screen display unit 120. 110 is formed. In the driving circuit region 110, driving circuit parts such as a gate driver 130 and a data driver 140 are formed.

Particularly, in the driving circuit unit, a CMOS having a pair of P-type and N-type complementary metal oxide semiconductors (MOS) to function as a unit transistor forms a unit and is connected to the unit pixels of the screen display unit. .

The CMOS of the driver circuit portion includes a P-type and an N-type TFT, and the switching element formed on the screen display portion 120 may mainly be formed with an N-type TFT.

Hereinafter, referring to FIG. 2, a planar structure of a unit pixel of a screen display unit employing a polysilicon thin film transistor will be described.

Referring to FIG. 2, the unit pixel area of the screen display unit is defined by a plurality of gate lines 101 and a plurality of data lines 102 perpendicular to the gate lines. The thin film transistor 150 is formed as a switching element for controlling the unit pixel in a part of the unit pixel region.

The thin film transistor 150 includes an active pattern 104a constituting a channel of the thin film transistor, a gate electrode 101a formed on the active pattern 104a and branching from the gate line 101, and And a source 102a and a drain electrode 102b connected to the active pattern through a contact hole formed on the active pattern 104a. The source and drain electrodes 102a and 102b are formed of a conductive layer branching from the data line 102. The thin film transistor 150 is connected to the pixel electrode 105 of a unit pixel.

The unit pixel further includes a storage capacitor for holding an image signal provided to the unit pixel. The storage capacitor is formed by a storage line 103 formed in parallel with the gate line, a polysilicon pattern 104b extending from the active pattern 104a, and an insulating layer formed therebetween.

Meanwhile, the source and drain regions formed in the active pattern 104a are doped with impurity ions for ohmic contact with the source and drain electrodes, and the polysilicon pattern 104b constituting one electrode of the storage capacitor is made of metal. The impurity ions are doped to make it.

Typically, the thin film transistor of the unit pixel is an N-type TFT doped with N-type impurities.

The N-type TFT and the P-type TFT of the driving circuit region are usually formed at the same time. The manufacturing process of the N-type TFT of the screen display unit and the P-type TFT of the driving circuit region will be described with reference to FIGS. 3A to 3H.

In a typical polysilicon liquid crystal display device, an N-type TFT and a P-type TFT are simultaneously formed, and FIG. 3 exemplifies an N-type TFT and a storage capacitor formed in a pixel region, and a P-type TFT formed in a driving circuit region. The manufacturing process is shown.

Referring to FIG. 3A, a substrate 300 such as transparent glass is prepared, and a buffer layer 301 made of a silicon oxide film is formed on the substrate to a predetermined thickness.

Subsequently, an active pattern 104a is formed on the buffer layer 301 by plasma enhanced chemical vapor deposition (PECVD).

When the active pattern is formed, the first electrode 104b of the storage electrode is formed at the same time.

Subsequently, referring to FIG. 3B, after forming active patterns, dopant ions for metallizing the first electrode 104b of the storage capacitor are doped into the storage first electrode. Doping the polysilicon with impurities may improve conductivity to improve the capacitor.

Referring to FIG. 3B, the storage first electrode 104b is exposed, and other regions are covered by the photoresist pattern 310 and doped with impurity ions.

Subsequently, the photoresist pattern 310 is removed and a first insulating layer 301 is formed to insulate the active patterns.

A conductive thin film such as a metal is formed on the first insulating layer 301 and a photolithography process is performed to form a gate line (not shown), gate electrodes 101a and 321 branching from the gate line, and the storage agent. The storage line 103 constituting the capacitor corresponds to the first electrode 104b.

Subsequently, a low concentration of N-type impurities is doped into the active pattern 104a using the metal patterns as a mask.

Next, referring to FIG. 3D, an LDD region is defined in an active pattern of the N-type TFT, and a photoresist pattern 311 covering the storage capacitor and the P-type TFT is formed.

The N-type high concentration impurity ions are implanted into the active pattern 104a using the photoresist pattern 311 as a blocking mask for doping ions. As a result, a low concentration impurity is formed near the channel of the active pattern, and a high concentration impurity is doped out to form an LDD type N-type TFT that forms a source and a drain region.

Next, referring to FIG. 3E, the P-type TFT is formed by covering the screen display unit on which the N-type TFT and the storage capacitor are formed by the photoresist pattern 312 and doping a high concentration of P-type impurities into the active pattern 320 of the P-type TFT. Form. Since the P-type impurity is higher in concentration than the N-type impurity, it is counter-doped to complete the P-type TFT.

Next, referring to FIG. 3F, a second insulating layer 303 is formed on the gate electrode, and a plurality of contact holes 304 are formed through a photo mask process.

The contact holes expose source and drain regions of the N-type TFT and the P-type TFT.

3G, source and drain electrodes 102a, 102b, 322a, and 322b connected to the source and drain regions of the N-type TFT and the P-type TFT are formed. The source and drain electrodes may be formed by sputtering a conductive film such as a metal film on the second insulating layer 303 and then performing a photolithography process.

Next, referring to FIG. 3H, a passivation layer 304 is formed to insulate the source and drain electrodes and a contact hole is formed to further expose the drain region of the pixel region. Subsequently, a transparent electrode material such as ITO is deposited on the passivation layer 304 and the pixel electrode 105 is formed by a photolithography process. The pixel electrode is connected to the drain electrode through a contact hole.

The polysilicon liquid crystal display device may be formed by the above-described process. As described above, since the conventional manufacturing process includes a plurality of mask processes, the number of masks used for shortening the process and improving productivity is as follows. Research continues to shorten the process.

Therefore, an object of the present invention is to reduce the number of masks used in forming a polysilicon liquid crystal display device as described above. In addition, by reducing the number of masks used to shorten the process it is aimed to lower the manufacturing cost and improve productivity.

In order to achieve the above object, the present invention provides a display device comprising: a unit pixel defined by a plurality of gate lines and a plurality of data lines perpendicular to the gate lines; A switching element formed in the unit pixel and formed at an intersection of the gate line and the data line; A storage line formed in the unit pixel; An insulating layer which insulates the storage line and exposes the display area in the unit pixel; It provides a liquid crystal display device comprising a pixel electrode formed in the insulating layer and the display area.

In addition, the present invention comprises the steps of forming an active pattern on a substrate; Forming a first insulating layer to insulate the active pattern; Forming a gate line, a gate electrode branching from the gate line, and a storage line parallel to the gate line on the first insulating layer; Implanting impurity ions into the active pattern to form source and drain regions; Forming a second insulating layer on the gate electrode; Forming a contact hole exposing the source and drain regions; Forming a source electrode and a drain electrode connected to the source and drain regions, respectively, and a data line crossing the gate line; Forming a passivation layer covering the source and drain electrodes and the data line; Removing the passivation layer and the second insulating layer of the display area in the unit pixel defined by the gate line and the data line; It provides a method of manufacturing a liquid crystal display device comprising the step of forming a pixel electrode in the display area.

In particular, the forming of the pixel electrode may include removing the first photoresist pattern by acing the second photoresist pattern; Forming a transparent electrode material layer on the ace second photoresist pattern and display area; Applying a second photosensitive film to the transparent electrode material layer and the display area to completely fill the display area; Acing the second photoresist layer to form a third photoresist pattern defining a pixel electrode; Etching the transparent electrode material by applying the third photoresist pattern as a mask to form a pixel electrode; And removing the second photoresist pattern and the third photoresist pattern.

Hereinafter, the structure of the unit pixel of the liquid crystal display of the present invention will be described with reference to FIGS. 4A and 4B.

FIG. 4A is a plan view showing a unit pixel of the present invention, and FIG. 4B is a cross-sectional view shown by cutting line I-I of FIG. 4A.

Referring to FIG. 4A, a unit pixel is defined by a plurality of gate lines 402 parallel to each other and a plurality of data lines 404 perpendicular to the gate lines 402.

The unit pixel may be divided into a display area 460 that substantially serves as a display device and a thin film transistor area (TFT area) 470 that drives the display area 460.

The TFT region 470 forms a channel, an active pattern 401 made of polysilicon, a gate electrode 402a branching from the gate line 402, and providing a scan signal, and the data line 404. A thin film transistor including a source electrode 405 branching from the second electrode 405 and a drain electrode 406 providing the image signal provided from the source electrode 405 to the pixel electrode 410 formed in the display area. Is formed.

In the display area 460, a storage line 403 is formed in parallel with the gate line 402 to form a storage capacitor together with the pixel electrode 410 formed in the display area 460.

An insulating layer 420 is formed on the storage electrode 403 to insulate the pixel electrode 410 and the storage electrode 403 from each other.

Referring to FIG. 4B, the insulating layer 420 may be a laminate of several insulating layers.

In addition, referring to FIG. 4B, the display area 460 is removed except for an upper portion of the storage electrode 403, so that the display area 460 forms an intaglio.

A pixel electrode 410 connected to the drain electrode 406 and formed of a transparent electrode material is formed in the negative display area.

Hereinafter, a method of manufacturing a liquid crystal display device of the present invention will be described with reference to FIGS. 5A to 5M.

Referring to FIG. 5A, an active pattern 401 is formed on a substrate 501 such as transparent glass. Before forming the active pattern, a buffer layer (not shown) made of a silicon nitride layer may be first formed on a substrate to prevent impurities from penetrating into the active pattern during the active pattern forming process.

In addition, since the present invention describes a manufacturing process of a liquid crystal display device integrated with a driving circuit unit in which a P-type TFT and an N-type TFT are simultaneously formed on one substrate, the active pattern includes an N-type TFT and a P-type TFT. It is formed in both areas. However, FIGS. 5A to 5K-2 will be described based on a manufacturing process of one unit pixel having an LDD N-type TFT and a storage capacitor for convenience of description.

Looking at the formation process of the active pattern 401 in more detail as follows.

First, amorphous silicon is deposited on a buffer layer (not shown), and heat treatment is performed at a temperature of about 400 ° C. to dehydrogenate the hydrogen contained in the amorphous silicon film. In the dehydrogenation process, hydrogen gas is exploded in the process of crystallizing amorphous silicon to prevent damage to the substrate.

Next, in order to crystallize the amorphous silicon, the substrate on which the amorphous silicon layer is formed is heat-treated. The substrate forming the liquid crystal display device is a glass substrate, and the glass substrate may be denatured by heat when a high temperature heat treatment is performed. Thus, in the process of forming a polysilicon TFT using a glass substrate, amorphous silicon may be formed by instant heat treatment at a low temperature. A laser annealing method is used that can be made of crystalline silicon.

Therefore, the substrate on which amorphous silicon is formed is irradiated with an excimer laser to change the amorphous silicon formed on the entire substrate into polycrystalline silicon (polysilicon).

After the polysilicon is formed, the active pattern 401 of the pixel region is formed by dry etching the polysilicon. At this time, the active pattern of the P-type TFT constituting the CMOS of the driver circuit portion is also formed at the same time.

A first insulating layer 502 is formed on the active pattern 401 to insulate the active pattern 401. The gate insulating layer 502 may be formed by depositing a silicon nitride film or a silicon oxide film by PECVD.

Subsequently, referring to FIG. 5B, a first conductive layer (not shown) is deposited on the first insulating layer 502 by a sputtering method, and a photolithography process is performed to branch from the gate line and the gate line. 402a and a storage line 403 arranged in parallel with the gate line.

The photolithography process includes forming a first conductive layer on the first insulating layer 502 by a sputtering method, applying a photoresist on the first conductive layer, and forming a gate electrode and a storage line. Exposing the photoresist by applying a patterned first mask; developing the exposed photoresist to form a predetermined photoresist pattern defining a gate electrode and a storage electrode; using the photoresist pattern as a mask Applying and etching the first conductive layer to form a gate electrode, a gate line, and a storage line, and removing the photoresist pattern through a strip process.

FIG. 5B shows the photoresist pattern 510 defining the gate electrode 402a and the storage line 403.

Subsequently, referring to FIG. 5B, a high concentration of impurity ions are implanted into the active pattern 401 while leaving the photoresist pattern 510 on the gate electrode 402a and the storage line 403. The impurity ions are implanted into the active pattern to metallize the active region. The active region into which the impurities are implanted includes a source and a drain region.

The implanted impurity ions may be Group 5 ions, for example, phosphorus (P) or asceic (As) ions, when forming the N-type TFT, and when forming a P-type TFT, Group 3 ions, for example It may be boron (B) ion.

Subsequently, when the LDD type N-type TFT is formed, the photoresist pattern 510 left on the gate electrode 402a and the storage electrode 403 is aced to reduce its volume.

As a result, referring to FIG. 5C, the photoresist pattern 510a that is aced and decreases in volume defines an LDD region at both ends of the channel, and applies the ace photoresist pattern 510a as an etch mask to form the gate electrode. 402a) is further etched. As a result, the LDD region is exposed across the channel.

Subsequently, referring to FIG. 5D, low-density N-type impurity ions are implanted into the LDD region by applying the aced photosensitive film pattern 510a and the gate electrode pattern 402a as a mask to complete an LDD-type N-type TFT. .

When the LDD type TFT is not formed, a process of exposing the LDD region, that is, the photoresist pattern 510 is ashed, and the aced photoresist pattern 510a is applied as an etch mask to form a gate electrode 402a. ) And a low concentration impurity ion implantation process may be unnecessary.

Subsequently, although not shown in FIG. 5, a photoresist pattern is further formed to cover the N-type TFT and expose the P-type TFT region, and the photoresist pattern is applied as a blocking mask to apply a high concentration of P-type impurity ions to the P-type TFT region. The process of forming the source and drain regions by implanting into the active pattern is further performed. Active patterns of the N-type and P-type TFTs may be metallized through the ion implantation processes.

Subsequently, referring to FIG. 5E, a second insulating layer 503 is formed on the gate electrode 402a and the storage line 403. The second insulating layer 503 may be made of the same material as the first insulating layer.

Next, contact holes 505 and 506 exposing the source and drain regions of the active pattern 401 are formed. The contact holes 505 and 506 are formed through a photo mask process. That is, a photoresist film is coated on the second insulating layer 503, exposed by applying a mask, and then developed to form a photoresist pattern defining a contact hole. Subsequently, the photoresist pattern is applied as an etching mask and the first and second insulating layers 502 and 503 are dry etched to expose source and drain regions.

Next, referring to FIG. 5F, source and drain electrodes 405 and 406 connected to the source and drain regions are formed through the contact holes 505 and 506. The source and drain electrodes 405 and 406 are formed through a photolithography process. That is, a second conductive layer is deposited on the second insulating layer 503 on which the contact hole is formed, a photoresist pattern is formed on the second conductive layer, and then the photoresist pattern is applied as an etching mask and the second conductive layer is applied. Etching is performed to form the source 405 and the drain electrode 406.

5G and 5H, a passivation layer 504, which is a third insulating layer, is formed on the source and drain electrodes 405 and 406. The passivation layer 504 insulates the source and drain electrodes 405 and 406 and protects it from the external environment.

Subsequently, a photoresist film is coated on the passivation 504, and a first photoresist film pattern 520 is formed to cover the gate line, the data line, and the switch area while exposing the display area. In this case, the first photoresist pattern 520 includes a second photoresist pattern 520a formed on the storage line 403 formed in the display area. In particular, the second photoresist pattern 520a is formed by diffraction exposure and is smaller than the thickness of the first photoresist pattern 520. In addition, in the present invention, since the first photoresist pattern 520 has a function of forming a step so that the display area becomes intaglio, the thickness difference between the first photoresist pattern 520 and the second photoresist pattern 520a Larger is preferable.

FIG. 5H shows a first photoresist pattern 520 formed on the passivation layer 504. Referring to FIG. 5H, the first photoresist pattern 520 may include a second photoresist pattern 520a covering the storage line 403 formed in the display area 460. Therefore, the first photoresist layer pattern 520 exposes the display area 406 except for the upper portion of the storage line 403. In particular, the first photoresist pattern 520 exposes the drain electrode 406.

Subsequently, referring to FIG. 5G, the second insulating layer 503 and the passivation layer 504 of the display area 406 are applied by applying the first photoresist pattern 520 and the second photoresist pattern 520a as an etch mask. In this way, the display area 406 is a pattern of intaglios with large steps.

In the process, since the insulating layers on the storage line are etched off by the second photoresist pattern 520a, the second insulating layer 503 and the passivation layer 504 remain on the storage line 403. That is, the storage line 403 is insulated by the second insulating layer 503 and the passivation layer 504.

Subsequently, the first photoresist pattern 520 and the second photoresist pattern 520a are aced to completely remove the second photoresist pattern 520a. In this case, the second photoresist pattern 520a is formed by diffraction exposure and is thinner than the first photoresist pattern 520 so that the first photoresist pattern 520 is still applied to the gate line, the data line and the switch region even after the acing. Remains.

Subsequently, referring to FIG. 5I, a transparent electrode material 420a is deposited on the aced first photoresist pattern 520b and the display area 406.

The transparent electrode material 420a may be ITO or IZO. The transparent electrode material 420a may be formed by a sputtering method.

Subsequently, referring to FIG. 5J, a photoresist film is deposited on the transparent electrode material 420a to fill the display area 460 with the photoresist layer 530 at a negative angle. The photosensitive film 530 is coated to be flat on the entire substrate. In particular, since the display area 460 is stepped at an intaglio, the photoresist 530 is applied to the display area 460 thicker than other areas.

Subsequently, referring to FIG. 5K, the photoresist 530 is aced to form a third photoresist pattern 530a. The third photoresist pattern 530a exposes the transparent electrode material on the aced first photoresist pattern 520b and completely covers the transparent electrode material of the display area 460 to define the pixel electrode. In this case, the step by the insulating layer on the storage line 403 is completely covered by the third photoresist pattern 530a due to the step by the aced first photoresist pattern 520b. The pixel electrode is patterned by removing the exposed transparent electrode material by applying the third photoresist pattern 530a as an etching mask.

5L and 5M, the first photoresist pattern 520b and the second photoresist pattern 530a are removed by a strip process to complete the liquid crystal display of the present invention. As shown in FIG. 5M, a pixel electrode is formed in the display area of a unit pixel, but an insulating layer is left on the storage line to insulate the storage line.

As described above, the liquid crystal display device of the present invention does not use a separate mask in forming the pixel electrode, but instead, the photosensitive film pattern is filled in the intaglio pattern, and a predetermined pattern is formed by an acing process. By using this method, the manufacturing process of the entire liquid crystal display device can be reduced. As a result, the overall process of the liquid crystal display device manufacturing process can be reduced.

Claims (10)

delete delete delete delete Forming an active pattern on the substrate; Forming a first insulating layer on the substrate to insulate the active pattern; Forming a gate line, a gate electrode branching from the gate line, and a storage line parallel to the gate line on the first insulating layer; Implanting impurity ions into the active pattern to form a source region and a drain region; Forming a second insulating layer on the first insulating layer including the gate electrode, a gate line and a storage line; Forming a contact hole in the second insulating layer and the first insulating layer to expose the source region and the drain region in the active pattern; Forming a data line on the second insulating layer, the data line crossing the gate line together with a source electrode and a drain electrode respectively connected to the source and drain regions through the contact hole; Forming a passivation layer on the second insulating layer, the passivation layer covering the source and drain electrodes and the data line; Exposing a display area on the passivation layer but forming a first photoresist pattern on the storage line, the first photoresist pattern including a second photoresist pattern formed by diffraction exposure; Removing the second insulating layer and the passivation layer in the display area by applying the first photoresist pattern as a mask to expose a portion of the drain electrode and to form a negative pattern in the display area; Acing the first photoresist pattern including the second photoresist pattern to remove the second photoresist pattern on the storage line to expose the passivation layer on the storage line; Forming a transparent electrode material layer on an entire surface of the substrate including the exposed first insulating layer and the passivation layer and the exposed drain electrode on the display area having the first photoresist pattern and the engraved pattern, and the exposed drain electrode; Steps; Applying a photoresist on the transparent electrode material layer to completely fill the intaglio pattern of the display area; Acing the photoresist to form a third photoresist pattern exposing the transparent electrode material layer on the first photoresist pattern; Applying the third photoresist pattern as an etch mask to etch the exposed transparent electrode material layer to form a pixel electrode; And removing the first photoresist pattern and the third photoresist pattern. 6. The method of claim 5, wherein the removing of the passivation layer and the second insulating layer formed in the display area leaves the second insulating layer and the passivation layer on the storage line. delete delete 6. The method of claim 5, wherein forming the source and drain regions is Implanting high concentration impurity ions into the active pattern; And implanting low concentration impurity ions into both ends of the channel region of the active pattern. delete

Images