CN113871483B - Thin film transistor, display substrate and display device - Google Patents
Thin film transistor, display substrate and display device Download PDFInfo
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- CN113871483B CN113871483B CN202010614083.9A CN202010614083A CN113871483B CN 113871483 B CN113871483 B CN 113871483B CN 202010614083 A CN202010614083 A CN 202010614083A CN 113871483 B CN113871483 B CN 113871483B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
- G02B27/01—Head-up displays
- G02B27/017—Head mounted
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
- G02B27/01—Head-up displays
- G02B27/017—Head mounted
- G02B27/0172—Head mounted characterised by optical features
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Abstract
The disclosure provides a thin film transistor, a display substrate and a display device, and belongs to the technical field of display. A thin film transistor of the present disclosure, comprising: a substrate, a gate electrode, an active layer, a source electrode and a drain electrode on the substrate; the grid electrode comprises a first grid electrode and a second grid electrode which are sequentially arranged on the substrate and are electrically connected; the active layer is positioned between the first grid electrode and the second grid electrode; and the orthographic projections of the first grid electrode and the second grid electrode on the substrate are overlapped with the orthographic projection part of the active layer on the substrate; the orthographic projection portions of the first grid electrode and the second grid electrode on the substrate are overlapped.
Description
Technical Field
The disclosure belongs to the technical field of display, and in particular relates to a thin film transistor, a display substrate and a display device.
Background
Because Virtual Reality (VR) display devices have the characteristics of high resolution, fast response, high refresh frequency, high brightness backlight, high contrast, etc., the market is increasingly large, and the sales volume is increasing year by year.
In the manufacturing process of a thin film transistor used in the conventional low-temperature polysilicon VR display device, a gate is formed on the surface of a polysilicon material layer by adopting a wet etching process, and at the moment, on the premise that photoresist covered on the surface of the gate is not removed, ion implantation is performed on the polysilicon material layer by taking the photoresist on the surface of the gate as a mask plate to form a source electrode contact area and a drain electrode contact area of an active layer, then the photoresist on the surface of the gate is removed, and then lightly doped drain (Lightly Doped Drain, abbreviated as LDD) treatment is performed on the polysilicon material layer to form a lightly doped drain structure (namely an LDD structure).
The inventor finds that the electron mobility of the thin film transistor used in the conventional low-temperature polysilicon VR display device is higher, and the influence of high backlight brightness is added, so that the leakage current Ioff of the pixel where the thin film transistor is located is larger, and the production yield of the low-temperature polysilicon VR display device is reduced.
Disclosure of Invention
The disclosure aims to at least solve one of the technical problems in the prior art and provides a thin film transistor, a display substrate and a display device.
In a first aspect, embodiments of the present disclosure provide a thin film transistor, including: a substrate, a gate electrode, an active layer, a source electrode and a drain electrode on the substrate; the grid electrode comprises a first grid electrode and a second grid electrode which are sequentially arranged on the substrate and are electrically connected; the active layer is positioned between the first grid electrode and the second grid electrode; and the orthographic projections of the first grid electrode and the second grid electrode on the substrate are overlapped with the orthographic projection part of the active layer on the substrate;
The orthographic projection portions of the first grid electrode and the second grid electrode on the substrate are overlapped.
A first gate insulating layer is arranged between the first gate electrode layer and the active layer; a second gate insulating layer is arranged between the layer where the active layer is located and the layer where the second gate is located; a connecting part is arranged on one of the first grid electrode and the second grid electrode; the front projection of the connecting part on the substrate protrudes out of the overlapping area of the front projection of the first grid electrode and the second grid electrode on the substrate;
the thin film transistor further comprises a first via hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting portion electrically connects the first gate and the second gate through the first via hole.
The active layer comprises a channel region, and a source contact region and a drain contact region which are respectively arranged at two sides of the channel region; the ion doping concentration of the source contact region and the drain contact region is greater than the ion doping concentration of the channel region.
Wherein an overlapping region of the active layer and the orthographic projection of the gate electrode on the substrate is the channel region; the active layer further includes a first auxiliary region between the channel region and the source contact region, and a second auxiliary region between the channel region and the drain contact region; the first auxiliary area and the second auxiliary area are not overlapped with the orthographic projection of the grid electrode on the substrate; the ion doping concentrations of the first auxiliary region and the second auxiliary region are smaller than those of the source electrode contact region and the drain electrode contact region.
The ion doping concentration of the first auxiliary region and the ion doping concentration of the second auxiliary region are larger than or equal to the ion doping concentration of the channel region.
Wherein, a shading layer is arranged on one side of the active layer, which is close to the substrate; the light shielding layer at least partially overlaps with a projection of the active layer on the substrate.
Wherein the shading layer and the first grid electrode are arranged on the same layer and are the same in material; wherein, the front projection of the shading layer and the first grid electrode on the substrate approximately covers the front projection of the active layer on the substrate.
In a second aspect, an embodiment of the present disclosure provides a display substrate, including pixel units arranged in an array; each pixel unit comprises the thin film transistor.
A first gate insulating layer is arranged between the first gate electrode layer and the active layer; a second gate insulating layer is arranged between the layer where the active layer is located and the layer where the second gate is located; the first grid electrodes in the pixel units in the same row are connected to form a first grid electrode strip; the second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;
a second via hole penetrating through the first gate insulating layer and the second gate insulating layer is arranged between any two adjacent pixel units in the row direction; the first grid electrode strip and the second grid electrode strip which are positioned in the pixel units in the same row are connected through the second through holes.
A first gate insulating layer is arranged between the first gate electrode layer and the active layer; a second gate insulating layer is arranged between the layer where the active layer is located and the layer where the second gate is located; the first grid electrodes in the pixel units in the same row are connected to form a first grid electrode strip; the second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;
second through holes penetrating through the first gate insulating layer and the second gate insulating layer are respectively formed in two ends of each first gate bar in the extending direction; the first grid electrode strip and the second grid electrode strip overlapped with the projection of the first grid electrode strip on the substrate are connected through the second through hole.
Wherein, the orthographic projection of the connecting part on the substrate protrudes out of the overlapping area of orthographic projections of the first grid electrode and the second grid electrode on the substrate; the thin film transistor further comprises a first via hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part is used for electrically connecting the first gate and the second gate through the first via hole;
any two adjacent connection parts in the row direction are positioned on different sides in the column direction of the pixel units.
Wherein a connecting part is arranged on one of the first grid electrode and the second grid electrode, and the orthographic projection of the connecting part on the substrate protrudes out of an overlapping area of orthographic projections of the first grid electrode and the second grid electrode on the substrate; the thin film transistor further comprises a first via hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part is used for electrically connecting the first gate and the second gate through the first via hole; the first grid electrode in one of any two adjacent pixel units is provided with the connecting part, and the second grid electrode in the other pixel unit is provided with the connecting part.
In a third aspect, embodiments of the present disclosure provide a VR display device including the above display substrate.
Drawings
Fig. 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present disclosure;
fig. 2 is a schematic perspective view of a gate electrode and an active layer of a thin film transistor according to an embodiment of the present disclosure;
fig. 3a is a top view of a thin film transistor according to an embodiment of the present disclosure, in which a light shielding layer is formed;
FIG. 3b is a cross-sectional view of A-A' of FIG. 3 a;
fig. 4a is a top view of a thin film transistor forming a first gate thereof according to an embodiment of the present disclosure;
FIG. 4B is a cross-sectional view of B-B' of FIG. 4 a;
fig. 5a is a top view of a thin film transistor of an embodiment of the present disclosure with an active layer formed thereon;
FIG. 5b is a cross-sectional view of C-C' of FIG. 5 a;
fig. 6a is a top view of a thin film transistor of an embodiment of the present disclosure with a first via formed therein;
FIG. 6b is a cross-sectional view of D-D' of FIG. 6 a;
fig. 7a is a top view of a thin film transistor of an embodiment of the present disclosure with its second gate formed;
FIG. 7b is a cross-sectional view of E-E' of FIG. 7 a;
FIG. 8 is a schematic illustration of ion doping of source and drain contact regions of a thin film transistor according to an embodiment of the disclosure;
FIG. 9 is a schematic diagram of disposing a second via in a display substrate according to an embodiment of the disclosure;
FIG. 10 is a schematic diagram of forming a second gate stripe in a display substrate according to an embodiment of the disclosure;
fig. 11 is a schematic view of a display substrate according to an embodiment of the disclosure.
Wherein the reference numerals are as follows: 10. a substrate; 111. a first gate; 112. a second gate; 12. an active layer; 13. a source electrode; 14. a drain electrode; 15. a buffer layer; 16. a first gate insulating layer; 17. a second gate insulating layer; 18. a first interlayer insulating layer; 19. a second interlayer insulating layer; 20. a light shielding layer; 21. a planarization layer; 22. a pixel electrode; 23. a third interlayer insulating layer; 24. a common electrode; 100. a first gate bar; 200. a second gate bar; 30. a connection part; 40. a first via; 50. a second via; 60. and a photoresist pattern.
Detailed Description
In order that those skilled in the art will better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Before describing the thin film transistor, the method for manufacturing the thin film transistor, the array substrate and the display device according to the embodiments of the present disclosure, the following description will be made.
In an embodiment of the present disclosure, a patterning process, such as a photolithographic patterning process, includes: coating photoresist on the structural layer to be patterned, wherein the photoresist film can be coated by spin coating, knife coating or roller coating; then, exposing the photoresist by using a mask plate, and developing the exposed photoresist layer to obtain a photoresist pattern; then etching the structural layer by using the photoresist pattern, and optionally removing the photoresist; and finally stripping the residual photoresist to form a required structure.
In the embodiment of the disclosure, the "same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then forming the film layer by using the same mask through a one-time patterning process. Depending on the particular pattern, the sequential patterning process may include multiple exposure, development, or etching processes, while the particular patterns of the same layer formed may be continuous or discontinuous, and may be at different heights or have different thicknesses.
In the embodiment of the disclosure, the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor; the N-type thin film transistor is formed by performing N-type ion doping on an active layer of the thin film transistor; the P-type thin film transistor refers to P-type ion doping in the active layer of the thin film transistor. The working level signal of the N-type thin film transistor is a high level signal; the working level signal of the P-type thin film transistor is a low level signal. In the following embodiments, the thin film transistor is described as an N-type thin film transistor, but the present disclosure is not limited to the N-type thin film transistor.
Hereinafter, a thin film transistor, a method for manufacturing the thin film transistor, an array substrate, and a display device according to embodiments of the present disclosure will be described with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.
Fig. 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present disclosure; fig. 2 is a schematic perspective view of a gate electrode and an active layer of a thin film transistor according to an embodiment of the present disclosure.
In a first aspect, as shown in fig. 1 and 2, an embodiment of the present disclosure provides a thin film transistor, the thin film transistor including: a substrate 10 disposed on the substrate 10, a gate electrode, an active layer 12, a source electrode 13, and a drain electrode 14; the thin film transistor in the embodiment of the present disclosure is specifically a dual-gate thin film transistor, and the gate thereof specifically includes a first gate 111 and a second gate 112 that are sequentially disposed on the substrate 10 and are electrically connected; the layer of the active layer 12 is located between the layer of the first grid 111 and the layer of the second grid 112, and the orthographic projections of the first grid 111 and the second grid 112 on the substrate 10 are overlapped with the orthographic projection part of the active layer 12 on the substrate 10; in particular, the orthographic projections of the first gate 111 and the second gate 112 on the substrate 10 partially overlap in the disclosed embodiment.
It should be noted that, the overlapping area of the gate electrode and the active layer 12 projected on the substrate 10 defines the channel region Q1 of the active layer 12; in the embodiment of the disclosure, the channel region Q1 of the active layer 12 is a region where the active layer 12 overlaps with the orthographic projections of the first gate 111 and the second gate 112 on the substrate 10. The source contact region Q2 and the drain contact region Q3 of the active layer 12 are respectively located at both ends of the channel region Q1 of the active layer 12. Wherein, the source electrode 13 and the drain electrode 14 of the thin film transistor are respectively connected to the source contact region Q2 and the drain contact region Q3 of the active layer 12. A first gate insulating layer 16 is provided between the layer where the first gate electrode 111 is located and the layer where the active layer 12 is located; a second gate insulating layer 17 is provided between the layer of the active layer 12 and the layer of the second gate electrode 112. The first gate electrode 111 and the second gate electrode 112 may be electrically connected through the first via hole 40 penetrating the first gate insulating layer 16 and the second gate insulating layer 17.
In the thin film transistor of the embodiment of the present disclosure, since the first gate electrode 111 and the second gate electrode 112 are electrically connected, when a high level signal is applied to one of the first gate electrode 111 and the second gate electrode 112, an electric field is generated in the first gate insulating layer 16 and the second gate insulating layer 17 at this time, electric lines of force in the first gate electrode 111 insulating layer are directed from the first gate electrode 111 to the lower surface (surface close to the substrate 10) of the active layer 12, and induced charges are generated in the lower surface of the active layer 12; the electric lines of force in the second gate insulating layer 17 are directed by the second gate electrode 112 toward the upper surface of the active layer 12 (the surface facing away from the substrate 10) and induce charges on the upper surface of the active layer 12; with the application of the high-level signal on the first gate 111 and the second gate 112, the upper surface and the lower surface of the active layer 12 are changed from the depletion layer to the electron accumulation layer, so as to form an inversion layer, when the inversion is strong (i.e. when the turn-on voltage is reached), the channel region Q1 where carriers pass through the active region is generated by applying a voltage between the source electrode 13 and the drain electrode 14, so that the thin film transistor is in a conductive state. Meanwhile, it can be seen that, since the first gate electrode 111 and the second gate electrode 112 in the thin film transistor are disposed on the upper and lower surfaces of the active layer 12, the electron mobility of the thin film transistor is higher than that of a single gate thin film transistor, and the turn-on performance of the thin film transistor is better.
In addition, in the thin film transistor of the embodiment of the present disclosure, the orthographic projections of the first gate electrode 111 and the second gate electrode 112 on the substrate 10 partially overlap, and since the electric signals applied to the first gate electrode 111 and the second gate electrode 112 are the same, there is no electric field at the overlapping position of the two, and thus, the orthographic projections of the active layer 12 on the substrate 10 and the orthographic projections of the first gate electrode 111 and the second gate electrode 112 on the substrate 10 overlap regions (i.e., the a regions shown in fig. 2) are not driven by the electric field, and thus, when the transistor is turned off, since the active layer 12 has the a regions, the leakage current of the thin film transistor can be effectively reduced.
In some embodiments, a connection 30 is provided on one of the first gate 111 and the second gate 112, and at least a portion of the orthographic projection of the first via 40 on the substrate 10 through the first gate insulating layer 16 and the second gate insulating layer 17 falls within the orthographic projection of the connection 30 on the substrate 10. It should be noted that, the connection portion 30 may be a bump structure connected to the first gate 111 or the second gate 112, so that the front projection of the connection portion on the substrate 10 protrudes from the overlapping area of the front projections of the first gate 111 and the second gate 112 on the substrate.
Specifically, when the connection portion 30 is disposed on the first gate electrode 111, the first gate electrode 111 is connected to the connection portion 30, and the orthographic projection of the connection portion 30 on the substrate 10 overlaps with the orthographic projection of the second gate electrode 112 on the substrate 10, for example: orthographic projection of the connection portion 30 on the substrate 10 and orthographic projection of the second gate 112 on the substrate 10 are covered; the connection portion 30 is connected to the second gate 112 through the first via hole 40, so as to complete the electrical connection between the first gate 111 and the second gate 112; when the connection portion 30 is disposed on the second gate electrode 112, the second gate electrode 112 is connected to the connection portion 30, and the orthographic projection of the connection portion 30 on the substrate 10 overlaps with the orthographic projection of the first gate electrode 111 on the substrate 10, for example: orthographic projection of the connection portion 30 on the substrate 10 and orthographic projection of the first gate 111 on the substrate 10 are covered; the connection portion 30 is connected to the first gate 111 through the second via hole 50, so as to electrically connect the first gate 111 and the second gate 112; the reason why the connection portion 30 is used to electrically connect the first gate electrode 111 and the second gate electrode 112 is that the size of the overlapping region of the first gate electrode 111 and the second gate electrode 112 should not be too wide in order to secure the electron mobility of the thin film transistor, and thus, in order to make the first gate electrode 111 and the second gate electrode 112 well electrically connected, the connection portion 30 is added to connect the two, thereby securing the electron mobility of the thin film transistor.
It should be noted that, the first via hole 40 may be a metal via hole, that is, a layer of metal is formed on the sidewall of the first via hole 40 to electrically connect the first gate 111, the connection portion 30, and the second gate 112; of course, the first gate 111, the connection portion 30, and the second gate 112 may be electrically connected by filling the first via 40 with a metal conductive material.
In some embodiments, when the connection portion 30 is disposed on the first gate 111, the first gate 111 and the connection portion 30 are integrally formed, i.e., the first gate 111 and the connection portion 30 are disposed in the same layer and made of the same material, so that a pattern including the first gate 111 and the connection portion 30 may be formed in one patterning process. Similarly, when the connection portion 30 is disposed on the second gate electrode 112, the second gate electrode 112 and the connection portion 30 are integrally formed, i.e., the second gate electrode 112 and the connection portion 30 are disposed on the same layer and made of the same material, so that a pattern including the second gate electrode 112 and the connection portion 30 can be formed in one patterning process. 4a is a top view of the thin film transistor of an embodiment of the present disclosure, in which the first gate 111 is formed; in the embodiment of the present disclosure, the integral structure of the first gate 111 and the connection part 30 shown in fig. 4a is described as an example.
In some embodiments, the active layer 12 includes a channel region Q1, and source and drain contact regions Q2 and Q3 located at both ends of the channel region Q1; the ion doping concentration of the source contact region Q2 and the drain contact region Q3 is greater than that of the channel region Q1, so that the source contact region Q2 and the drain contact region Q3 of the active layer 12 have good ohmic contact with the source electrode 13 and the drain electrode 14 connected thereto, respectively. Specifically, the active layer 12 may be channel-doped after the first patterning of the active layer 12 to adjust the threshold voltage Vth of the thin film transistor. After the second gate 112 is patterned, the source contact region Q2 and the drain contact region Q3 of the active layer 12 are heavily doped such that the ion doping concentration of the source contact region Q2 and the drain contact region Q3 of the active layer 12 is greater than the ion doping concentration of the channel region Q1.
In some embodiments, as shown in fig. 2, the active layer 12 includes not only the channel region Q1, the source contact region Q2, and the drain contact region Q3 described above; and further includes a first auxiliary region Q4 between the channel region Q1 and the source contact region Q2, and a second auxiliary region Q5 between the channel region Q1 and the drain contact region Q3; it is understood that the overlapping area of the active layer 12 and the gate electrode in the front projection on the substrate 10 defines the channel region Q1 of the active layer 12, that is, the position of the overlapping area of the active layer 12 and the first gate electrode 111 and the second gate electrode 112 in the front projection is the channel region Q1 of the active layer 12, and for the active layer 12, the front projections of the source contact region Q2, the drain contact region Q3, the first auxiliary region Q4 and the second auxiliary region Q5 on the substrate 10 overlap with the first gate electrode 111 and the second gate electrode 112. The ion doping concentrations of the first auxiliary region Q4 and the second auxiliary region Q5 are smaller than those of the source electrode contact region Q2 and the drain electrode contact region Q3; therefore, the first auxiliary region Q4 and the second auxiliary region Q5 of the active layer 12 are semiconductor, and compared with the source contact region Q2 and the drain contact region Q3, the first auxiliary region Q4 and the second auxiliary region Q5 are lightly doped (i.e. the first auxiliary region Q4 and the second auxiliary region Q5 are lightly doped after the channel doping), and the orthographic projections of the first auxiliary region Q4 and the second auxiliary region Q5 and the first gate 111 and the second gate 112 on the substrate 10 are not overlapped, so that when the transistor is turned off, the leakage current of the thin film transistor can be effectively reduced because the active layer 12 has the first auxiliary region Q4 and the second auxiliary region Q5.
Of course, the first auxiliary region Q4 and the second auxiliary region Q5 correspond to channel doping, that is, the ion doping concentration of the first auxiliary region Q4 and the second auxiliary region Q5 is the same as that of the channel region Q1, that is, when patterning the active layer 12 for the first time, the channel region Q1, the source contact region Q2 and the drain contact region Q3 of the active layer 12 are performed, and at the same time, the first auxiliary region Q4 and the second auxiliary region Q5 are lightly doped to adjust the threshold voltage Vth of the thin film transistor.
Fig. 3a is a top view of a thin film transistor according to an embodiment of the present disclosure, in which a light shielding layer 20 is formed; FIG. 3b is a cross-sectional view of A-A' of FIG. 3 a; in some embodiments, as shown in fig. 3a and 3b, in order to avoid light from irradiating the active layer 12 and causing a large leakage current of the thin film transistor, a light shielding layer 20 is formed on a side of the active layer 12 near the substrate 10, and an orthographic projection of the light shielding layer 20 on the substrate 10 covers at least a portion of the channel region Q1 of the active layer 12.
In one example, the light shielding layer 20 is disposed on a side of the first gate electrode 111 near the substrate 10, and the buffer layer 15 is disposed between the light shielding layer 20 and the first gate electrode 111, and the front projection of the light shielding layer 20 on the substrate 10 completely covers the front projection of the channel region Q1 of the active layer 12 on the substrate 10.
In another example, the light shielding layer 20 may also be disposed in the same layer as the first gate 111, and the front projection of the light shielding layer 20 and the first gate 111 on the substrate 10 covers substantially the front projection of the channel region Q1 of the active layer 12 on the substrate 10. It should be noted that, the front projection of the light shielding layer 20 and the first gate 111 on the substrate 10 covers the front projection of the channel region Q1 of the active layer 12 on the substrate 10 substantially completely, because a certain gap exists between the light shielding layer 20 and the first gate 111, so as to avoid that the light shielding layer 20 is electrically connected with the first gate 111, which affects the switching characteristics of the thin film transistor.
In order to make the layer structures of the thin film transistor in the embodiments of the present disclosure clearer, the thin film transistor in the embodiments of the present disclosure is further described with reference to the following method for manufacturing the thin film transistor.
The embodiment of the disclosure provides a preparation method of a thin film transistor, which specifically comprises the following steps:
step one, a substrate 10 is provided, and a pattern including a light shielding layer 20 is formed on the substrate 10 through a patterning process, as shown in fig. 3a and 3 b.
In some embodiments, the material of the light shielding layer 20 may employ a light shielding metal material including, but not limited to, molybdenum Mo. Taking the material of the light shielding layer 20 as metal Mo as an example, the first step may specifically include: mo metal material is deposited on the substrate 10, and exposure, development, and etching processes are performed right under a position corresponding to the channel region Q1 of the active layer 12 to be formed to form a pattern including the light shielding layer 20.
The substrate 10 in the embodiment of the present disclosure is a transparent insulating substrate 10, and the material of the substrate 10 includes, but is not limited to, glass and quartz, and other suitable materials may be used.
Step two, fig. 4a is a top view of forming a first gate 111 of the thin film transistor according to an embodiment of the disclosure;
FIG. 4B is a cross-sectional view of B-B' of FIG. 4 a; as shown in fig. 4a and 4b, a buffer layer 15 is formed on the substrate 10 on which the light shielding layer 20 is formed, and a pattern of a first gate electrode 111 including a gate electrode is formed through a patterning process on a side of the buffer layer 15 facing away from the substrate 10.
Wherein the material of the buffer layer 15 in the embodiments of the present disclosure may be selected to be similar to the lattice structure of Si, such as Si x N y Or Si (or) x O y : silicon nitride or silicon oxide. Specifically, the silicon nitride/silicon oxide composite film can be a single-layer structure with silicon nitride or silicon oxide, and of course, a silicon nitride or silicon oxide composite film structure can also be adopted.
The first gate 111 is formed of a conductive material such as molybdenum Mo, molybdenum-niobium alloy, aluminum Al, aluminum-neodymium alloy, titanium Ti, or copper Gu. The first gate electrode 111 may have a single layer structure or a multi-layer structure, such as a Ti/Al/Ti three-layer structure.
In some embodiments, the step two may specifically include: a buffer layer 15 is formed on the substrate 10 on which the light shielding layer 20 is formed by a method including, but not limited to, deposition to provide a thermal insulating layer and a heat conductive layer when the active layer 12 is subsequently formed through an annealing process. A first gate metal material layer is formed on the substrate 10 on which the buffer layer 15 is formed, and a pattern including the first gate electrode 111 and the connection portion 30 is formed through exposure, development, and etching processes.
Step three, fig. 5a is a top view of the thin film transistor according to the embodiment of the disclosure, in which the active layer 12 is formed; FIG. 5b is a cross-sectional view of C-C' of FIG. 5 a; as shown in fig. 5a and 5b, a first gate insulating layer 16 is formed on the substrate 10 on which the first gate electrode 111 is formed, and a pattern including the active layer 12 is formed through a patterning process on a side of the first gate insulating layer 16 facing away from the substrate 10.
Wherein in embodiments of the present disclosure, the material of the first gate insulating layer 16 may be selected to be similar to the lattice structure of Si, such as Si x N y Or Si (or) x O y : silicon nitride or silicon oxide. Specifically, the silicon nitride/silicon oxide composite film can be a single-layer structure with silicon nitride or silicon oxide, and of course, a silicon nitride or silicon oxide composite film structure can also be adopted.
In the embodiment of the present disclosure, the material of the active layer 12 is amorphous silicon, polysilicon, or an oxide semiconductor. The polycrystalline silicon may be high-temperature polycrystalline silicon or low-temperature polycrystalline silicon, and the oxide semiconductor may be Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), zinc oxide (ZnO), gallium Zinc Oxide (GZO), or the like. The active layer 12 is exemplified as low temperature polysilicon in the embodiments of the present disclosure.
In some embodiments, step three may specifically include: firstly, a gate insulating layer and an amorphous silicon film (a-Si) are sequentially formed by a deposition mode, wherein the deposition mode comprises a plasma enhanced chemical vapor deposition mode and a low-pressure chemical vapor deposition mode.
Next, the amorphous silicon film is crystallized, and the crystallization method includes an excimer laser crystallization method, a metal induced crystallization method or a solid phase crystallization method, so that the amorphous silicon film is converted into a polysilicon film (P-Si), and then the polysilicon film (P-Si) is doped (P-type doping or N-type doping) to determine the conductivity type of the channel region Q1 of the TFT, which is exemplified by the N-type TFT in the embodiment of the present disclosure, so that the doping is N-type doping. Wherein, the doping of the amorphous silicon film in the step is channel doping, and can be specifically doped with 3-valent boron ions. Here, since the ion concentration of the amorphous silicon film is responsible for the threshold voltage Vth of the thin film transistor, the ion concentration of the amorphous silicon film needs to be adjusted according to the threshold voltage Vth of the thin film transistor.
In addition, in this step, the excimer laser crystallization method and the metal induced crystallization method are two low-temperature polysilicon methods, and are relatively common methods for converting amorphous silicon into polysilicon. However, the method of converting amorphous silicon into polysilicon according to the present disclosure is not limited to the method of using low-temperature polysilicon, as long as the active layer 12 can be converted into a desired polysilicon thin film.
Finally, a photoresist layer is formed on the polysilicon film, the photoresist is exposed and developed, and then the polysilicon film is dry etched to form a pattern including the active layer 12.
Step four, fig. 6a is a top view of forming a first via 40 of the thin film transistor according to an embodiment of the disclosure; FIG. 6b is a cross-sectional view of D-D' of FIG. 6 a; as shown in fig. 6a and 6b, on the substrate 10 on which the active layer 12 is formed, a second gate insulating layer 17 is formed, and a first via hole 40 penetrating through the first gate insulating layer 16 and the second gate insulating layer 17 is formed at a position of the second gate insulating layer 17 corresponding to the connection portion 30, and for the subsequent formation of the second gate electrode 112, the connection portion 30 may be connected through the first via hole 40 to complete the electrical connection of the first gate electrode 111 and the second gate electrode 112.
The material of the second gate insulating layer 17 may be the same as that of the first gate insulating layer 16, and thus the material of the second insulating layer will not be described here.
In some embodiments, the fourth step may specifically include: the second gate insulating layer 17 is deposited, and the first via hole 40 penetrating the first gate insulating layer 16 and the second gate insulating layer 17 is formed at a position corresponding to the connection portion 30 through exposure, development, and etching processes.
Step five, fig. 7a is a top view of the thin film transistor according to the embodiment of the disclosure, in which the second gate 112 is formed; FIG. 7b is a cross-sectional view of E-E' of FIG. 7 a; as shown in fig. 7a and 7b, on the substrate 10 formed with the second gate insulating layer 17, a pattern including the second gate electrode 112 is formed through a patterning process. The second gate 112 is connected to the connection portion 30 through the first via 40, and the second gate 112 overlaps the orthographic projection portion of the first gate 111 on the substrate 10.
The material and the manufacturing process of the second gate electrode 112 may be the same as those of the first gate electrode 111, so the forming process of the second gate electrode 112 will not be described herein.
Step six, ion implantation (i.e. heavy doping) is performed on the source contact region Q2 and the drain contact region Q3 of the active layer 12 on the substrate 10 where the second gate 112 is formed, so as to enhance ohmic contact between the active layer 12 and the source 13 and the drain 14, and ensure that P-Si forms good ohmic contact with the source 13 and the drain 14.
In some embodiments, fig. 8 is a schematic illustration of ion doping of the source contact region Q2 and the drain contact region Q3 of a thin film transistor of an embodiment of the present disclosure; as shown in fig. 8, step six may specifically include forming a photoresist layer on a side of the second gate electrode 112 facing away from the substrate 10, exposing the photoresist layer to light to form a photoresist pattern 60, and heavily doping the source contact region Q2 and the drain contact region Q3 of the active layer 12 by including, but not limited to, 5-valent phosphorus ions to enhance ohmic contact of the active layer 12 with the source electrode 13 and the drain electrode 14 by using the photoresist pattern 60 as a mask for ion implantation of the source contact region Q2 and the drain contact region Q3 of the active layer 12.
In addition, in some embodiments, the width of the patterned photoresist is greater than the line width of the gate formed by the first gate 111 and the second gate 112, so that after heavily doping the source contact region Q2 and the drain contact region Q3, a portion of the active layer 12 structure is not heavily doped between the channel region Q1 and the source contact region Q2 and between the channel region Q1 and the drain contact region Q3, respectively, which are the first auxiliary region Q4 and the second auxiliary region Q5, respectively; the first auxiliary region Q4 and the second auxiliary region Q5 are implanted with only 3-valent boron ions, and the projections of the first auxiliary region Q4 and the second auxiliary region Q5 and the first gate 111 and the second gate 112 on the substrate 10 are not overlapped, so that the first auxiliary region Q4 and the second auxiliary region Q5 are equivalent to lightly doped drain structures, and thus leakage current can be effectively reduced, as shown in fig. 2. It should be noted that the first auxiliary region Q4 and the second auxiliary region Q5 may include only one doping during channel doping, or the first auxiliary region Q4 and the second auxiliary region Q5 may be lightly doped after heavily doping, where the ion concentration doped in the first auxiliary region Q4 and the second auxiliary region Q5 depends on the switching characteristic requirement of the thin film transistor.
The ion implantation method includes an ion implantation method including a mass analyzer, an ion cloud implantation method including no mass analyzer, a plasma implantation method, and a solid diffusion implantation method. That is, in this embodiment, the active layer 12 with good semiconductor properties is finally formed by a plurality of steps such as crystallization, doping, ion implantation, and the like, from the low-temperature polysilicon material.
Step seven, as shown in fig. 1, after heavily doping the source contact region Q2 and the drain contact region Q3 of the active layer 12, forming a first interlayer insulating layer 18 on the substrate 10 on which the second gate 112 is formed, exposing, developing and etching the position where the first interlayer insulating layer 18 is formed corresponding to the source contact region Q2 to form a source 13 contact via penetrating the first interlayer insulating layer 18 and the second gate insulating layer 17; then forming a pattern comprising a source electrode 13 through a patterning process, wherein the source electrode 13 is connected with the source electrode 13 through a source electrode 13 contact via hole; next, a second interlayer insulating layer 19 is formed on the substrate 10 on which the source electrode 13 is formed, and the source electrode 13 contact via hole penetrating the second interlayer insulating layer 19, the first interlayer insulating layer 18 and the second gate insulating layer 17 is formed by exposing, developing and etching the position where the second interlayer insulating layer 19 is formed corresponding to the drain electrode contact region Q3; thereafter, a pattern including the drain electrode 14 is formed through a patterning process, and the drain electrode 14 is connected to the drain electrode 14 through a drain electrode 14 contact via.
It should be noted that, in the seventh step, the source electrode 13 and the drain electrode 14 are formed in a layered structure, that is, are separately disposed in a two-layer structure, where the preparation order of the source electrode 13 and the drain electrode 14 may be changed, in the embodiment of the present disclosure, the drain electrode 14 is formed above the source electrode 13 as an example, so that the size of the thin film transistor may be reduced, which is beneficial to improving the aperture ratio of the display substrate of the thin film transistor; of course, it is also possible to form the source electrode 13 and the drain electrode 14 of the thin film transistor in the same layer by one patterning process.
In some embodiments, an active hydrogenation process may be performed to repair the crystal lattice of the active layer 12 when forming the source 13 contact via penetrating the first interlayer insulating layer 18 and the second gate insulating layer 17.
The materials of the first interlayer insulating layer 18 and the second interlayer insulating layer 19 in the seventh step may be the same as those of the first gate insulating layer 16, and thus a description thereof will not be repeated here. The material and the manufacturing process of the formed source electrode 13 and drain electrode 14 are the same as those of the formed gate electrode, and thus a description thereof will not be repeated here.
The preparation of the thin film transistor in the presently disclosed embodiments is completed.
In a second aspect, an embodiment of the present disclosure provides a display substrate, where the display substrate may be used in a VR display device, where the display substrate includes pixel units arranged in an array, and each pixel unit may include any one of the thin film transistors described above.
Since the display substrate in the embodiment of the disclosure includes any one of the thin film transistors, the thin film transistor has small leakage current and good performance.
In some embodiments, fig. 9 is a schematic diagram of disposing a second via 50 in a display substrate according to an embodiment of the disclosure; fig. 10 is a schematic diagram illustrating formation of a second gate stripe 200 in a display substrate according to an embodiment of the disclosure; as shown in fig. 9 and 10, a first gate insulating layer 16 is provided between the first gate electrode 111 and the active layer 12 of each thin film transistor, and a second gate insulating layer 17 is provided between the active layer 12 and the second gate electrode 112; wherein, the first gates 111 in the pixel units in the same row are connected to form a first gate bar 100; the second gates 112 in the pixel cells in the same row are connected as the first gate bar 100. A second via hole 50 penetrating the first gate insulating layer 16 is provided between any two adjacent pixel cells; the first gate 111 and the second gate bar 200 located in the same row of pixel cells are electrically connected through the second via 50. The second via hole 50 penetrating the first gate insulating layer 16 is disposed between any two adjacent pixel units to ensure good electrical connection between the first gate electrode stripe 100 and the second gate electrode stripe 200, so that the electrical signals inputted to the first gate electrode stripe 100 and the second gate electrode stripe 200 are the same. Meanwhile, in the embodiment of the present disclosure, since the second via hole 50 and the first via hole 40 electrically connecting the first gate 111 and the second gate 112 are all penetrating the first gate insulating layer 16, the first via hole 40 and the second via hole 50 may be formed in the same patterning process, so that the process steps are not increased.
Of course, the second via holes 50 penetrating the first gate insulating layer 16 and the second gate insulating layer 17 may be formed only at the two ends of the first gate bar 100 and the second gate bar 200, so that the first gate 111 and the second gate bar 200 may be electrically connected, and the gate scan signal may be introduced from the two ends of the first gate bar 100 and the second gate bar 200.
In some embodiments, as shown in fig. 9, a connection part 30 is provided on one of the first gate electrode 111 and the second gate electrode 112 of the thin film transistor in each pixel unit, and the first gate electrode 111 and the second gate electrode 112 are electrically connected through the first connection part 30 through the first via hole 40 on the first gate insulating layer 16 and the second gate insulating layer 17. In the embodiment of the disclosure, the connection portion 30 is disposed on the first gate 111 of one of the thin film transistors in any two adjacent pixel units in the same row, and the connection portion 30 is disposed on the second gate 112 of the other pixel unit, so that the scanning signals input on the first gate 111 and the second gate 112 in the same row are consistent. Of course, it is also possible to use the connection portion 30 on the first gate 111 for each pixel unit located in the same row, and use the connection portion 30 on the second gate 112 for each pixel unit located in an adjacent row, which is within the protection scope of the embodiments of the present disclosure.
In addition, the connection portions 30 in any two adjacent pixel cells in the row direction are located on different sides in the column direction of the pixel cell in which each is located, for example: the connection portion 30 in one pixel unit is located at the left side of the pixel unit, and the connection portion 30 in the adjacent pixel unit is located at the right side of the pixel unit. Of course, it is also possible that the connection portions 30 in each pixel unit are located on the same side of each pixel unit, which is within the protection scope of the embodiments of the present disclosure.
In the embodiment of the present disclosure, fig. 11 is a schematic diagram of a display substrate according to the embodiment of the present disclosure, and as shown in fig. 11, each pixel unit on the display substrate is further provided with a pixel electrode 22 and a common electrode 24; in some embodiments, a planarization layer 21 is disposed on a side of the layer where the drain electrode 14 of the thin film transistor is located away from the substrate 10, a third via hole is formed at a position of the planarization layer 21 corresponding to the drain electrode 14, and a pixel electrode 22 is formed on a side of the planarization layer 21 away from the substrate 10 and is connected to the drain electrode 14 of the thin film transistor through the third via hole; a third interlayer insulating layer 23 is provided on the side of the layer where the pixel electrode 22 is located facing away from the substrate 10; a common electrode 24 may also be provided on a side of the third interlayer insulating layer 23 facing away from the substrate 10. The pixel electrode 22 is a plate electrode, and the common electrode 24 is a slit electrode. Of course, when the pixel electrode 22 and the common electrode 24 are both provided on the display substrate, both of them may be slit electrodes. When the pixel electrode 22 and the common electrode 24 are slit electrodes, they may be disposed on the same layer or may be layered, so long as they are alternately disposed. In the embodiment of the present disclosure, the common electrode 24 may not be disposed on the display substrate, but may be disposed on an opposite pair of box substrates, wherein the pair of box substrates in the embodiment of the present disclosure include, but are not limited to, color film substrates.
In a third aspect, an embodiment of the present disclosure provides a display device including the display substrate described above. The display device in embodiments of the present disclosure includes, but is not limited to, a VR display device. The thin film transistor is adopted in the display panel of the display device, so that the leakage current is small, and the display effect is better.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.
Claims (7)
1. A thin film transistor applied to a virtual reality technology VR display device; the thin film transistor includes: a substrate, a gate electrode, an active layer, a source electrode and a drain electrode on the substrate; the grid electrode comprises a first grid electrode and a second grid electrode which are sequentially arranged on the substrate and are electrically connected; the active layer is positioned between the first grid electrode and the second grid electrode; and the orthographic projections of the first grid electrode and the second grid electrode on the substrate are overlapped with the orthographic projection part of the active layer on the substrate; the material of the active layer is low-temperature polysilicon;
A first gate insulating layer is arranged between the first gate layer and the active layer, the surface of the first gate insulating layer close to the first gate is in direct contact with the surface of the first gate close to the first gate insulating layer, and the surface of the first gate insulating layer close to the active layer is in direct contact with the surface of the active layer close to the first gate insulating layer;
a second gate insulating layer is arranged between the layer where the active layer is arranged and the layer where the second gate is arranged, the surface of the second gate insulating layer close to the second gate is in direct contact with the surface of the second gate close to the second gate insulating layer, and the surface of the second gate insulating layer close to the active layer is in direct contact with the surface of the active layer close to the second gate insulating layer;
one of the first grid electrode and the second grid electrode is provided with a connecting part which is in the same layer with the first grid electrode and the second grid electrode; the front projection of the connecting part on the substrate protrudes out of the overlapping area of the front projection of the first grid electrode and the second grid electrode on the substrate; the thin film transistor further comprises a first via penetrating through the first gate insulating layer and the second gate insulating layer, the first gate and the second gate are electrically connected through the first via by the connecting part, one end of the connecting part, which is close to the first gate, is in direct contact with the surface of the first gate, which is close to the active layer, and one end of the connecting part, which is close to the second gate, is in contact with the surface of the second gate, which is close to the active layer;
The orthographic projection part of the first grid electrode and the second grid electrode on the substrate is overlapped;
the active layer comprises a channel region, a source contact region and a drain contact region which are respectively arranged at two sides of the channel region, a first auxiliary region arranged between the channel region and the source contact region, and a second auxiliary region arranged between the channel region and the drain contact region; the first auxiliary area and the second auxiliary area are not overlapped with the orthographic projection of the grid electrode on the substrate;
wherein the ion doping concentration of the source contact region and the drain contact region is greater than the ion doping concentration of the first auxiliary region and the second auxiliary region; the ion doping concentration of the first auxiliary region and the ion doping concentration of the second auxiliary region are both greater than or equal to the ion doping concentration of the channel region;
a shading layer is arranged on one side of the active layer, which is close to the substrate; the light shielding layer at least partially overlaps with the projection of the active layer on the substrate;
the shading layer and the first grid electrode are arranged on the same layer and are the same in material; wherein, the front projection of the shading layer and the first grid electrode on the substrate approximately covers the front projection of the active layer on the substrate.
2. A display substrate includes pixel units arranged in an array; each pixel cell includes the thin film transistor of claim 1.
3. The display substrate according to claim 2, wherein a first gate insulating layer is provided between the layer where the first gate electrode is provided and the layer where the active layer is provided; a second gate insulating layer is arranged between the layer where the active layer is located and the layer where the second gate is located; the first grid electrodes in the pixel units in the same row are connected to form a first grid electrode strip; the second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;
a second via hole penetrating through the first gate insulating layer and the second gate insulating layer is arranged between any two adjacent pixel units in the row direction; the first grid electrode strip and the second grid electrode strip which are positioned in the pixel units in the same row are connected through the second through holes.
4. The display substrate according to claim 2, wherein a first gate insulating layer is provided between the layer where the first gate electrode is provided and the layer where the active layer is provided; a second gate insulating layer is arranged between the layer where the active layer is located and the layer where the second gate is located; the first grid electrodes in the pixel units in the same row are connected to form a first grid electrode strip; the second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;
Each first gate bar is provided with a second via hole penetrating through the first gate insulating layer and the second gate insulating layer at two ends of the extending direction of the first gate bar; the first grid electrode strip and the second grid electrode strip overlapped with the projection of the first grid electrode strip on the substrate are connected through the second through hole.
5. The display substrate according to claim 2, wherein a connection portion is provided on one of the first gate electrode and the second gate electrode; the front projection of the connecting part on the substrate protrudes out of the overlapping area of the front projection of the first grid electrode and the second grid electrode on the substrate; the thin film transistor further comprises a first via hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part is used for electrically connecting the first gate and the second gate through the first via hole;
any two adjacent connection parts in the row direction are positioned on different sides in the column direction of the pixel units.
6. The display substrate according to claim 2, wherein a connection portion is provided on one of the first gate electrode and the second gate electrode; the front projection of the connecting part on the substrate protrudes out of the overlapping area of the front projection of the first grid electrode and the second grid electrode on the substrate; the thin film transistor further comprises a first via hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part is used for electrically connecting the first gate and the second gate through the first via hole;
The first grid electrode in one of any two adjacent pixel units is provided with the connecting part, and the second grid electrode in the other pixel unit is provided with the connecting part.
7. A VR display device comprising the display substrate of any one of claims 2-6.
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| CN202010614083.9A CN113871483B (en) | 2020-06-30 | 2020-06-30 | Thin film transistor, display substrate and display device |
| PCT/CN2021/095028 WO2022001468A1 (en) | 2020-06-30 | 2021-05-21 | Thin film transistor, display substrate and display apparatus |
| US17/772,785 US20220406945A1 (en) | 2020-06-30 | 2021-05-21 | Thin film transistor, display substrate and display device |
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| CN202010614083.9A CN113871483B (en) | 2020-06-30 | 2020-06-30 | Thin film transistor, display substrate and display device |
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| CN113871483B true CN113871483B (en) | 2024-04-16 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229347A (en) * | 2016-08-24 | 2016-12-14 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and manufacture method thereof |
| CN106684155A (en) * | 2017-01-05 | 2017-05-17 | 京东方科技集团股份有限公司 | Dual-gate thin film transistor and preparation method therefor, array substrate and display apparatus |
| CN110730984A (en) * | 2017-06-08 | 2020-01-24 | 夏普株式会社 | Active matrix substrate and display device |
| CN110931566A (en) * | 2018-09-20 | 2020-03-27 | 三星显示有限公司 | Transistor substrate, method of manufacturing the same, and display device including the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102194235B1 (en) * | 2013-09-05 | 2020-12-22 | 삼성전자주식회사 | Thin film transistor and method for driving the same |
| KR102548001B1 (en) * | 2015-07-08 | 2023-06-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
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- 2020-06-30 CN CN202010614083.9A patent/CN113871483B/en active Active
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- 2021-05-21 WO PCT/CN2021/095028 patent/WO2022001468A1/en active Application Filing
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229347A (en) * | 2016-08-24 | 2016-12-14 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and manufacture method thereof |
| CN106684155A (en) * | 2017-01-05 | 2017-05-17 | 京东方科技集团股份有限公司 | Dual-gate thin film transistor and preparation method therefor, array substrate and display apparatus |
| CN110730984A (en) * | 2017-06-08 | 2020-01-24 | 夏普株式会社 | Active matrix substrate and display device |
| CN110931566A (en) * | 2018-09-20 | 2020-03-27 | 三星显示有限公司 | Transistor substrate, method of manufacturing the same, and display device including the same |
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| US20220406945A1 (en) | 2022-12-22 |
| WO2022001468A1 (en) | 2022-01-06 |
| CN113871483A (en) | 2021-12-31 |
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