KR20010046328A - a thin film transistor array panel for a liquid crystal display and a manufacturing method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor(TFT) substrate for use in a liquid crystal display(LCD) device and a method for manufacturing the same are to prevent data interconnections to be shorted by applying a double layer of a main and an auxiliary data interconnection. CONSTITUTION: Gate interconnections(21-25) are formed on a substrate(10) using a photolithography. A gate insulating layer(30), a semiconductor layer(40) and the first conductive layer(50) are sequently deposited to enclose the gate interconnection. The first conductive layer and the semiconductor layer are patterned using the photolithography. The second conductive layer(60) is deposited and patterned using the photolithography, thereby forming auxiliary data interconnections(71-76). Main data interconnections(61-63, 66-68) are obtained by patterning the first conducive layer whose portion is not enclosed by the auxiliary data interconnection. A passivation layer(80) is deposited on the auxiliary data interconnection. The passivation layer is patterned using the photolithography, thereby forming contact holes(81-83). The third conductive layer is deposited and patterned to form a pixel electrode(91) using the photolithography.

Description

A thin film transistor array panel for a liquid crystal display and a manufacturing method

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

In general, a liquid crystal display device has a structure in which a liquid crystal is injected between two substrates, and light transmittance is controlled by adjusting the intensity of an electric field applied between the two substrates. One of the two substrates is a substrate including a thin film transistor, which includes a plurality of gate wirings, data wirings, and pixel electrodes, and is formed by repeating a process of forming a thin film and etching a plurality of times.

Recently, as the size of liquid crystal displays increases, the wiring length of the thin film transistor substrate becomes longer, and thus signal delay occurs. Therefore, it is necessary to use low-resistance metal as the wiring material to reduce this. Alloys. Meanwhile, in the conventional manufacturing process of the thin film transistor substrate, the data lines are formed before the pixel electrodes, and some of the data lines are connected to the pixel electrodes. However, when Al or an Al alloy is used as the data line, the ITO etchant easily corrodes the data line when the indium-tin-oxide (ITO) is etched to form the pixel electrode. As a result, the contact between the data line and the pixel electrode is poor, and even when the contact is made, the contact resistance is high and there is a possibility that the contact portion is broken with time. In addition, since the wiring is long, the probability that the data wiring is disconnected increases.

There is a method of preventing this by completely covering the Al wiring by using an extra data line, but this increases the number of photo etching processes, which causes a large manufacturing cost.

An object of the present invention is to prevent the data line from being corroded by the etchant of the pixel electrode.

Another object of the present invention is to prevent the data wiring from being disconnected.

Another object of the present invention is to provide a method in which the number of processes is not increased while using an extra data line.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1;

3 is a layout view of a thin film transistor substrate in a first step of manufacturing according to an embodiment of the present invention,

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3;

FIG. 5 is a cross-sectional view taken along line IV-IV ′ of FIG. 3, and is a cross-sectional view at a next step of FIG. 4.

FIG. 6 is a layout view of a thin film transistor substrate in a next step of FIG. 5;

FIG. 7 is a cross-sectional view taken along the line VII-VII 'of FIG. 6,

FIG. 8 is a layout view of a thin film transistor substrate in a next step of FIG. 7;

FIG. 9 is a cross-sectional view taken along the line VII-VII 'of FIG. 8;

FIG. 10 is a cross-sectional view taken along the line VII-VII 'of FIG. 8, and is a cross-sectional view in the next step of FIG. 9,

FIG. 11 is a layout view of a thin film transistor substrate in a next step of FIG. 10;

FIG. 12 is a cross-sectional view taken along the line II-XII 'of FIG. 11.

In the present invention, the data wiring is formed into a double layer of the main data wiring and the auxiliary data wiring to prevent disconnection of the data wiring, the semiconductor layer and the main data wiring are patterned together, and then the auxiliary data wiring is used to form the main wiring on the thin film transistor channel portion. Eliminating the data wiring does not increase the number of processes.

In the present invention, a gate wiring including a plurality of gate lines and gate electrodes is formed on a substrate by using a first photolithography process, and then a gate insulating film, a semiconductor layer, and a first conductor layer are sequentially deposited. The first conductor layer and the semiconductor layer are patterned by a second photolithography process. Subsequently, the second conductor layer is deposited and patterned by a third photolithography process to form an auxiliary data line including an auxiliary data line, an upper layer of a source electrode, and an upper layer of a drain electrode. Next, the first conductor layer not covered with the auxiliary data wiring is etched to complete the main data wiring including the main data line, the source electrode lower layer, and the drain electrode lower layer. A protective insulating layer covering the auxiliary data line is deposited, and then patterned by a fourth photolithography process to form a first contact hole exposing an upper layer of the drain electrode. Subsequently, a third conductor layer is deposited and etched by a fifth photolithography process to form a pixel electrode.

Here, the first conductor layer may be made of chromium that is hardly etched into the pixel electrode etchant, and the thickness may be 1,500 to 2,000 kPa.

In addition, the second conductor layer may be made of ITO.

In the manufacturing method according to the present invention, the method may further include depositing an ohmic contact layer on the semiconductor layer, patterning the second photolithography process, and then removing the ohmic contact layer that is not covered by the main data line.

Meanwhile, the gate wiring further includes a gate pad connected to an end of the gate line, forming a second contact hole to expose the gate pad by etching the protective insulating film and the gate insulating film by a fourth photolithography process, and the gate by a fifth photolithography process. The method may further include forming an auxiliary gate pad on the pad.

The auxiliary data line further includes a data pad connected to an end of the auxiliary data line, forming a third contact hole for exposing the data pad by a fourth photolithography process, and forming the auxiliary data pad on the data pad by a fifth photolithography process. It may further comprise the step of forming.

In the present invention, the third conductor layer may be made of ITO.

In the thin film transistor substrate for a liquid crystal display according to the present invention, a gate wiring including a plurality of gate lines and gate electrodes connected to the gate lines and a gate pad is formed on the substrate, and a gate insulating film covers the gate wiring on the substrate. A semiconductor pattern is formed on the gate insulating layer, and a main data line including a main data line and a source electrode under layer connected to the main data line, and a main data line including a drain electrode under layer separated from the main data line and the source electrode under layer is formed thereon. It is. An auxiliary data line including an auxiliary data line, an upper layer of a source electrode and a drain electrode, and a data pad connected to the auxiliary data line is formed on the main data line. A protective insulating film is formed on the auxiliary data line, and has a first insulating layer and a third contact hole exposing the upper layer of the gate pad, the data pad, and the drain electrode. A pixel electrode connected to the upper layer of the drain electrode through the third contact hole is formed on the protective insulating layer.

Here, the main data wiring may be made of chromium, and in this case, the thickness of the main data wiring is preferably 1,500 to 2,000 Å.

In addition, the auxiliary data line may be formed of a transparent conductive material such as ITO.

In the thin film transistor substrate for a liquid crystal display according to the present invention, the semiconductor pattern has the same form as the main data wiring except between the source electrode and the drain electrode.

Here, an ohmic contact layer pattern having the same shape as the main data wiring may be further formed between the semiconductor pattern and the data wiring.

On the other hand, the thin film transistor substrate for a liquid crystal display according to the present invention is a gate line short band connected to the gate pad, a data line short band connected to the data line and a short circuit band connecting the gate line short band and the data line short band. The connection portion may be further formed.

In the present invention, an extra data line is formed on the main data line to prevent the main data line from being disconnected, and the number of steps is not increased because the semiconductor pattern and the main data line are formed in one photolithography process. In addition, since chromium, which does not corrode relatively well in the pixel electrode etchant, is used for the main data wiring, the main data wiring is less likely to be corroded.

Next, a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

First, the structure of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

First, a plurality of gate lines 21 extending in the horizontal direction on the substrate 10, the gate electrodes 22 of the thin film transistors that are branches of the gate lines 21, and the ends of the gate lines 21 are connected to each other. A gate wiring including a gate pad 23 for receiving a scan signal and a vertical gate line shorting bar 25 in which a connection portion 24 is connected to the gate pad 23 is formed. In the present exemplary embodiment, the gate wirings 21, 22, 23, 24, and 25 may be formed as a single layer, but may also be formed as a double layer or a triple layer of a chromium (Cr) layer and an aluminum alloy (Al—Nd) layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Relatively small resistivity among metals is Al or Al alloy, which has good contact characteristics with ITO (indium-tin-oxide), which is used as pixel electrode, and chromium (Cr), molybdenum (Mo), titanium (Ti) and tantalum (Ta) and the like, when forming a double layer, the gate wirings may be formed using a material other than Cr / Al (or Al alloy). Here, the gate line short circuit 25 connected to all the gate lines 21 serves to dissipate static electricity generated during the process.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 21, 22, 23, 24, and 25 to cover the gate wirings 21, 22, 23, 24, and 25.

A semiconductor pattern 41 made of a material such as amorphous silicon is formed on the gate insulating layer 30, and a material such as amorphous silicon doped with a high concentration of n-type impurities such as phosphorus (P) is formed on the semiconductor pattern 41. The resistive contact layer patterns 51 and 52 are formed.

On the contact layer patterns 51 and 52, main data wirings 61, 62, 63, 66, 67 and 68 made of a conductive material such as Cr are formed. The main data wirings are formed in a vertical direction and connected to the plurality of main data lines 61 intersecting the gate lines 21 and the data pad lower layer 66 and the main data lines 61 at the ends of the main data lines 61. The horizontal data line short circuit 68 connected to the data pad lower layer 66 through the source electrode lower layer 62 connected thereto, the drain electrode lower layer 63 separated therefrom, and the connecting portion 67 is connected to each other. Include. The source electrode lower layer 62 and the drain electrode lower layer 63 face each other with respect to the gate electrode 22.

The contact layer patterns 51 and 52 have the same shape as that of the main data wirings 61, 62, 63, 66, 67 and 68, and the semiconductor pattern 41 has the channel portion of the thin film transistor, that is, the lower layer 62 of the source electrode. The upper contact layer patterns 51 and 52 and the main data wirings 61, 62, 63, 66, 67, and 68 are formed except for the gap between the bottom layer 63 and the drain electrode 63.

On the main data wirings 61, 62, 63, 66, 67, and 68, auxiliary data wirings 71, 72, 73, 74, 75, and 76 made of a transparent conductive material such as ITO are connected to the main data wirings 61, 62, 63, 66, 67, 68). The auxiliary data wires 71, 72, 73, 74, 75, and 76 may include the auxiliary data line 71, the source electrode upper layer 72, and the drain electrode upper layer 73, the data pad upper layer 74, and the auxiliary short circuit 76. ) And an auxiliary connection 75.

Here, the auxiliary data wirings 71, 72, 73, 74, 75, and 76 are supplementary wirings in which the main data wirings 61, 62, 63, 66, 67, and 68 are disconnected, and the data line short circuit ( 68) is to prevent device destruction due to electrostatic discharge.

A protective insulating film 80 is formed on the auxiliary data wirings 71, 72, 73, 74, 75, and 76, and the protective insulating film 80 includes a data pad 74, a drain electrode upper layer 73, and an auxiliary shorting band. The contact holes 82, 83, and 85 respectively exposing 76 are exposed, and the contact holes 81 and 84 are respectively exposed together with the gate insulating film 30 to expose the gate pad 23 and the gate line shorting band 24, respectively. Has)

A pixel electrode 91 made of a transparent conductive material such as ITO, an auxiliary gate pad 92, an auxiliary data pad 93, and a short circuit connection portion 94 are formed on the passivation insulating layer 80. The pixel electrode 91 is connected to the drain electrode upper layer 73 through the contact hole 83, and the auxiliary gate pad 92 and the auxiliary data pad 93 are gate pads through the contact holes 81 and 82, respectively. 23 is connected to the data pad 74. In this case, the auxiliary gate pad 92 and the auxiliary data pad 93 may be omitted. The short-circuit connecting portion 94 is connected to the gate line short-circuit 25 and the auxiliary short-circuit 76 through the contact holes 84 and 85, so that the gate wirings 21, 22, 23, 24, and 25 And even if static electricity is applied to any of the auxiliary data wires 61, 62, 63, 66, 67, 68, 71, 72, 73, 74, 75, and 76. However, these short bands 25, 68, 76 are later removed, and the substrate is cut along line 1 when removing them.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 11 and FIGS. 1 and 2.

First, as shown in FIGS. 3 and 4, a conductive material is deposited on the substrate 10, and the gate line 21, the gate electrode 22, the gate pad 23, and the gate are formed by using a first photolithography process. Gate wirings 21, 22, 23, 24 and 25 including the line short circuit 25 and the connection portion 24 are formed. In this case, a storage electrode line (not shown) may be formed between the two adjacent gate lines 21 in parallel with the gate line 21. This storage electrode line overlaps with the pixel electrode to form a storage capacitor.

Next, as shown in FIG. 5, the gate insulating film 30, the semiconductor layer 40, and the ohmic contact layer 50 are successively formed on the gate wirings 21, 22, 23, 24, and 25 by CVD. After the deposition, the Cr layer 60 is deposited to a thickness of 1,500 to 2,000 mW using a sputtering method.

In this case, it is important to select the thickness of the Cr layer 60 properly. If the thickness of the Cr layer is formed to be 1,500 Hz or less, the resistance is large and signal delay occurs. Since the stress increases, the main data wirings 61, 62, 63, 66, 67, and 68 are likely to be disconnected at the part where the step difference occurs such as where the gate line 21 or the gate electrode 22 meets. .

6 and 7, the Cr layer 60, the contact layer 50, and the semiconductor layer 40 are sequentially patterned by using a second photolithography process to form the data line pattern 65 and data. The line shorting band 68, the connecting portion 67, the contact layer pattern 55, and the semiconductor pattern 41 are formed. The data line pattern 65, the data line short circuit 68, and the connecting portion 67 are similar to the main data lines 61, 62, 63, 66, 67, and 68 in FIG. The difference is that the drain electrode lower layer 63 is connected.

8 and 9, the auxiliary data line 71, the source electrode upper layer 72, and the drain electrode upper layer 73 are deposited by depositing a transparent conductive material such as ITO and patterning using a third photolithography process. ), And an auxiliary data line 71, 72, 73, 74, 75, or 76 including a data pad upper layer 74, an auxiliary short circuit 76, and a connection 75.

The auxiliary data lines 71, 72, 73, 74, 75, and 76 are formed of ITO because ITO is a material having good step coverage and good contact characteristics with Cr.

Next, as illustrated in FIG. 10, the data line pattern 65 and the contact layer pattern 55 which are not covered by the auxiliary data lines 71, 72, 73, 74, 75, and 76 are etched to etch the source electrode lower layer 62. ) And the drain electrode lower layer 63 are separated to complete the contact layer patterns 51 and 52.

Next, as shown in FIGS. 11 and 12, the protective insulating film 80 is deposited and etched together with the gate insulating film 30 using a fourth photolithography process to form the gate pad 23, the data pad 74, and the drain. Contact holes 81, 82, 83 exposing the upper electrode 73, and contact holes 84, 85 exposing the gate line short band 25 and the auxiliary short band 76 are formed, respectively.

Subsequently, when the gate wirings 21, 22, and 23 are formed of a double layer of Cr / Al-Nd, it is necessary to remove the Al-Nd layer, which is the upper layer of the gate pad 23 exposed through the contact hole 81, by the front surface etching. good.

Next, as illustrated in FIGS. 1 and 2, a transparent conductive material such as ITO is deposited, and then etched by a fifth photolithography process to etch the pixel electrode 91, the auxiliary gate pad 92, the auxiliary data pad 93, and the like. The short-circuit connecting portion 94 is formed.

Finally, the substrate is cut along the dotted line 1 in FIG. 1 to remove the gate line short band 25, the data line short band 68, and the auxiliary short band 76.

In this embodiment, ITO was deposited and patterned twice, but it may be applied only once. That is, the pixel electrodes 91 may be formed together when the auxiliary data lines 71, 72, 73, 74, 75, and 76 are formed (in this case, the gate line short circuit 25 and the data line short circuit ( 68 is difficult to connect. In this case, the auxiliary data line 71 and the pixel electrode 91 may be short-circuited.

In the reflective liquid crystal display, the pixel electrode 91 may be formed of an opaque conductive material instead of ITO.

In the thin film transistor substrate for a liquid crystal display according to the present invention, the data line may be formed of Cr to prevent corrosion of the data line in the etchant of the pixel electrode. In addition, although the data line may be prevented from being disconnected using the auxiliary data line, the number of photolithography processes does not increase.

Claims (18)

Forming a gate wiring on the substrate by a first photolithography process; Sequentially depositing a gate insulating film, a semiconductor layer, and a first conductor layer covering the gate wiring; Patterning the first conductor layer and the semiconductor layer by a second photolithography process; Depositing a second conductor layer, Patterning the second conductor layer using a third photolithography process to form an auxiliary data line including an auxiliary data line, an auxiliary source electrode, and an auxiliary drain electrode; Etching the first conductor layer not covered with the auxiliary data wiring to complete main data wiring; Depositing a protective insulating film covering the auxiliary data line; Patterning the protective insulating layer by a fourth photolithography process to form a first contact hole exposing the auxiliary drain electrode; Depositing a third conductor layer, and Etching the third conductor layer to form a pixel electrode by a fifth photolithography process Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And the first conductor layer is made of chromium. In claim 2, The thickness of the said 1st conductor layer is a manufacturing method of the thin-film transistor board | substrate for liquid crystal display devices. The method according to any one of claims 1 to 3, And the second conductor layer is made of ITO. In claim 4, Depositing an ohmic contact layer over the semiconductor layer; Patterning the ohmic contact layer by the second photolithography process, and Removing the ohmic contact layer that is not covered by the main data wiring. Method of manufacturing a thin film transistor substrate for a liquid crystal display device further comprising. In claim 1, The gate line further includes a gate pad connected to an end of the gate line, Forming a second contact hole exposing the gate pad by etching the protective insulating layer and the gate insulating layer by the fourth photolithography process and forming an auxiliary gate pad on the gate pad by the fifth photolithography process Method of manufacturing a thin film transistor substrate for a liquid crystal display device further comprising. In claim 1, The auxiliary data line further includes a data pad connected to an end of the auxiliary data line. And forming a third contact hole exposing the data pad by the fourth photolithography process. In claim 7, And forming an auxiliary data pad on the data pad by the fifth photolithography process. In claim 1, The third conductor layer is a method for manufacturing a thin film transistor substrate for a liquid crystal display device made of ITO. Board, A gate wiring formed on the substrate and including a plurality of gate lines and gate electrodes and gate pads connected to the gate lines, A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating layer; A main data line formed on the semiconductor pattern and including a main data line and a source electrode underlayer connected to the main data line, and a drain electrode underlayer separated from the main data line and the source electrode underlayer; An auxiliary data line including an auxiliary data line formed on the main data line, an upper layer of the source electrode and a lower layer of the drain electrode, an upper layer of a source electrode and a drain electrode, and a data pad connected to the auxiliary data line; A protective insulating layer covering the auxiliary data line and having first to third contact holes respectively exposed together with the gate insulating layer to expose the gate pad, the data pad, and an upper layer of the drain electrode; A pixel electrode formed on the protective insulating layer and connected to the upper layer of the drain electrode through the third contact hole; Thin film transistor substrate for a liquid crystal display device comprising a. In claim 10, The main data line is a thin film transistor substrate for a liquid crystal display device made of chromium. In claim 11, The thin film transistor substrate for liquid crystal display device of which said main data wiring is 1,500-2,000 micrometers in thickness. The method according to any one of claims 10 to 12, The auxiliary data line is a thin film transistor substrate for a liquid crystal display device made of ITO. In claim 10, The semiconductor pattern has the same shape as the main data line except between the source electrode lower layer and the drain electrode lower layer. The method of claim 14, And a resistive contact layer pattern formed between the semiconductor pattern and the main data wiring and having the same shape as the main data wiring. In claim 10, And a gate line short circuit formed on the substrate and connected to the gate pad. The method of claim 16, And a data line short circuit formed on the gate insulating layer and connected to the data pad. The method of claim 17, And a short circuit connection unit formed on the passivation layer and connecting the gate line short circuit and the data line short circuit.