KR100583313B1 - Liquid crystal display and fabricating method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a method of manufacturing the same that can reduce the number of mask process.

A liquid crystal display according to the present invention includes a gate line formed on a substrate; A data line intersecting the gate line and a gate insulating layer to determine a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode formed in the pixel region and connected to the thin film transistor; A gate pad connected to the gate line; A data pad connected to said data line; The data pad is formed to expose a transparent conductive film on the substrate in contact with the substrate.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY AND FABRICATING METHOD THEREOF}             

1 is a plan view illustrating a thin film transistor array substrate of a conventional liquid crystal display panel.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate shown in FIG. 1 taken along the line "II-II '".

3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to a first embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along the line "V-V '".

6A and 6B are plan and cross-sectional views illustrating a first mask process in a method of manufacturing a lower array substrate according to a first embodiment of the present invention.

7A and 7B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

8A to 8C are cross-sectional views for describing in detail the second mask process illustrated in FIGS. 7A and 7B.

9A and 9B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

10A through 10E are cross-sectional views illustrating in detail the third mask process illustrated in FIGS. 9A and 9B.

11 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to a second exemplary embodiment of the present invention.

FIG. 12 is a cross-sectional view of the thin film transistor array substrate of FIG. 11 taken along the line " XII-XII '.

13A to 13C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

14 is a plan view illustrating a liquid crystal display including the thin film transistor array substrate of FIG. 4.

FIG. 15 is a cross-sectional view illustrating the liquid crystal display taken along the line "V-V" in FIG. 14.

16 is a plan view illustrating a liquid crystal display including the thin film transistor array substrate of FIG. 11.

FIG. 17 is a cross-sectional view illustrating the liquid crystal display taken along the line “ⅩⅦ-ⅩⅦ” in FIG. 16.

<Description of Symbols for Main Parts of Drawings>

2,102: gate line 4,104: data line

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 12112 gate insulating film

14,114 active layer 16,116 ohmic contact layer

18,118: Shield 20,42,56,66,162,180: Contact hole

22,122: pixel electrode 28,128: storage electrode

40,140: Storage capacitor 50,150: Gate pad

52: gate pad lower electrode 54: gate pad upper electrode

60, 160: data pad 62: data pad lower electrode

64: data pad upper electrode 170: transparent conductive film

172: gate metal film

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same that can simplify the process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display device, the liquid crystal display device drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display includes a thin film transistor array substrate (lower array substrate) and a color filter array substrate (upper array substrate) bonded together to face each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap. Equipped.

The thin film transistor array substrate is composed of a plurality of signal wires and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, an inspection process, and the like. Accordingly, in recent years, a four-mask process that reduces one mask process in a five-mask process, which is a standard mask process of a thin film transistor array substrate, has emerged.

FIG. 1 is a plan view illustrating a thin film transistor array substrate using a conventional four mask process, and FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along a line “II-II ′” in FIG. 1.

1 and 2, a thin film transistor array substrate of a conventional liquid crystal display panel includes a gate line 2 and a data line 4 formed to intersect a gate insulating layer 12 therebetween on a lower substrate 1; A thin film transistor 30 formed at each intersection thereof, a pixel electrode 22 formed at the pixel region provided at the intersection structure, a storage capacitor 40 formed at an overlapping portion of the gate line 2 and the storage electrode 28, and And a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region 5.

The thin film transistor 30 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 22 in response to the gate signal of the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode connected to the pixel electrode 22. 10). In addition, the thin film transistor 30 further includes an active layer 14 overlapping with the gate electrode 6 and the gate insulating layer 12 therebetween to form a channel between the source electrode 8 and the drain electrode 8. .

The active layer 14 also overlaps the data line 4, the data pad lower electrode 62, and the storage electrode 28. On the active layer 14, an ohmic contact layer 16 for ohmic contact with the data line 4, the source electrode 8, the drain electrode 10, the data pad lower electrode 62, and the storage electrode 28 is further included. Is formed.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 through the first contact hole 20 penetrating the passivation layer 18 and is formed in the pixel region 5.

Accordingly, an electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor 30 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the lower array substrate and the upper array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 40 includes a gate line 2, a storage electrode 28 overlapping the gate line 2 with the gate insulating layer 12, the active layer 14, and the ohmic contact layer 16 therebetween. do. The storage electrode 28 is connected to the pixel electrode 22 through the second contact hole 42 formed in the passivation layer 18. The storage capacitor 40 allows the pixel signal charged in the pixel electrode 22 to remain stable until the next pixel signal is charged.

The gate pad 50 is connected to a gate driver (not shown) to supply a gate signal to the gate line 2. The gate pad 50 has a gate pad lower electrode 52 extending from the gate line 2 and a third contact hole 56 penetrating the gate insulating layer 12 and the passivation layer 18. And a gate pad upper electrode 54 connected to 52.

The data pad 60 is connected to a data driver (not shown) to supply a data signal to the data line 4. The data pad 60 is connected to the data pad lower electrode 62 through a data pad lower electrode 62 extending from the data line 4 and a fourth contact hole 66 passing through the passivation layer 18. It consists of a data pad upper electrode 64.

A method of manufacturing a thin film transistor array substrate of a liquid crystal display panel having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, a gate pattern including a gate line 2, a gate electrode 6, and a gate pad lower electrode 52 is formed on the lower substrate 1 using a first mask process.

In detail, the gate metal layer is formed on the lower substrate 1 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate pattern including the gate line 2, the gate electrode 6, and the gate pad lower electrode 52. Here, an aluminum metal or the like is used as the gate metal layer.

Referring to FIG. 3B, a gate insulating layer 12 is coated on the lower substrate 1 on which the gate pattern is formed. A semiconductor pattern including an active layer 14 and an ohmic contact layer 16 on the gate insulating layer 12 using a second mask process; A data pattern including a data line 4, a source electrode 8, a drain electrode 10, a data pad lower electrode 62, and a storage electrode 28 is formed.

In detail, the gate insulating layer 12, the amorphous silicon layer, the n + amorphous silicon layer, and the data metal layer are sequentially formed on the lower substrate 1 on which the gate pattern is formed by a deposition method such as PECVD or sputtering. Here, as the material of the gate insulating film 12, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the data metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

Subsequently, a photoresist pattern is formed on the data metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the data metal layer is patterned by a wet etching process using a photoresist pattern to include a data line 4, a source electrode 8, a drain electrode 10 integrated with the source electrode 8, and a storage electrode 28. A data pattern is formed.

Then, the ohmic contact layer 14 and the active layer 16 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

After the photoresist pattern having a relatively low height is removed from the channel portion by an ashing process, the data metal layer and the ohmic contact layer 16 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 8 and the drain electrode 10.

Subsequently, the photoresist pattern remaining on the data pattern is removed by a stripping process.

Referring to FIG. 3C, the passivation layer 18 including the first to fourth contact holes 20, 42, 56, and 66 is formed on the gate insulating layer 12 on which the data pattern is formed by using a third mask process. do.

In detail, the protective film 18 is entirely formed on the gate insulating film 12 on which the data pattern is formed by a deposition method such as PECVD. Subsequently, the passivation layer 18 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 20, 42, 56, and 66. The first contact hole 20 penetrates the passivation layer 18 to expose the drain electrode 10, and the second contact hole 42 penetrates the passivation layer 18 to expose the storage electrode 28. The third contact hole 56 penetrates the passivation layer 18 and the gate insulating layer 12 to expose the gate pad lower electrode 52, and the fourth contact hole 66 penetrates the passivation layer 18 to lower the data pad. The electrode 62 is exposed. Here, when a dry etching ratio metal such as molybdenum (Mo) is used as the data metal, each of the first, second, and fourth contact holes 20, 42, and 66 may have a drain electrode 10 and a storage electrode 28. As a result, the data pad lower electrode 62 penetrates to expose side surfaces thereof.

As the material of the protective film 18, an inorganic insulating material such as the gate insulating film 12 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, a transparent conductive pattern including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64 is formed on the passivation layer 18 using a fourth mask process. .

In detail, the transparent conductive film is apply | coated on the protective film 18 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive layer is patched through a photolithography process and an etching process using a fourth mask, thereby forming a transparent conductive pattern including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64. . The pixel electrode 22 is electrically connected to the drain electrode 10 through the first contact hole 20 and electrically connected to the storage electrode 28 through the second contact hole 42. The gate pad upper electrode 54 is electrically connected to the gate pad lower electrode 52 through the third contact hole 56. The data pad upper electrode 64 is electrically connected to the data pad lower electrode 62 through the fourth contact hole 66.

Herein, materials of the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (IZO). ) Is used.

As described above, the conventional thin film transistor array substrate and the method of manufacturing the same can reduce the number of manufacturing steps and reduce manufacturing costs in proportion to the case of using the 5 mask process by employing a four mask process. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for a method of further reducing the manufacturing cost by simplifying the manufacturing process.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can reduce the number of mask processes.

In order to achieve the above object, the liquid crystal display device according to the present invention comprises a gate line formed on the substrate; A data line intersecting the gate line and a gate insulating layer to determine a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode formed in the pixel region and connected to the thin film transistor; A gate pad connected to the gate line; A data pad connected to said data line; The data pad is formed to expose a transparent conductive film on the substrate in contact with the substrate.

The liquid crystal display device further comprises a conductive film connected to the transparent conductive film.

The data line may be connected to the data pad through a first data contact hole exposing the data pad.

The data pad may include the transparent conductive film and a gate metal film formed on a region overlapping the data line on the transparent conductive film.

The data pad may include the transparent conductive layer and a gate metal layer having a second data contact hole on the transparent conductive layer.

The transparent conductive film of the data pad may be connected to the conductive film via the second data contact hole penetrating through the gate insulating film and the gate metal film of the data pad.

The thin film transistor may include a gate electrode connected to the gate line; A source electrode connected to the data line; And a semiconductor pattern for forming a channel between the pixel electrode and the drain electrode connected to the pixel electrode.

The pixel electrode may include a transparent conductive film and a gate metal film formed on a region overlapping the drain electrode on the transparent conductive film.

The transparent conductive layer may include at least one of TO, ITO, IZO, and ITZO, and the gate metal layer may include at least one of aluminum-based metal, Mo, Cu, Cr, Ta, and Ti.

In order to achieve the above object, a method of manufacturing a liquid crystal display according to the present invention includes a signal line including a gate line and a data line intersecting a gate insulating film on a substrate, and an intersection portion of the gate line and the data line. And forming a formed thin film transistor, a pixel electrode connected to the thin film transistor, a gate pad connected to the gate line, and a data pad connected to the data line, wherein the data pad is in contact with the substrate. It characterized in that the transparent conductive film is formed to expose.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 17.

4 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating a thin film transistor array substrate taken along a line "V-V '" in FIG. 4. .

4 and 5 may include a gate line 102 and a data line 104 formed on the lower substrate 101 to intersect with the gate insulating pattern 112 interposed therebetween, and formed at each intersection thereof. The thin film transistor 130, the pixel electrode 122 formed in the pixel region 105 provided in an intersecting structure, the storage capacitor 140 formed in an overlapping portion of the pixel electrode 122 and the gate line 102, and the gate. A gate pad 150 extending at line 102 and a data pad 160 extending at data line 104.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in an intersecting structure to define the pixel region 105.

The thin film transistor 130 keeps the pixel signal of the data line 104 charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line 102. To this end, the thin film transistor 130 may include a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode connected to the pixel electrode 122. 110). In addition, the thin film transistor 130 includes semiconductor patterns 114 and 116 that form a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 and the gate insulating pattern 112 therebetween. do.

The gate pattern including the gate electrode 106 and the gate line 102 has a structure in which a transparent conductive film 170 and a gate metal film 172 are stacked on the transparent conductive film 170.

The semiconductor pattern includes an active layer 114 that forms a channel between the source electrode 108 and the drain electrode 110 and partially overlaps the gate pattern with the gate insulating pattern 112 therebetween. The semiconductor pattern is formed on the active layer 114 and further includes an ohmic contact layer 116 for ohmic contact with the storage electrode 128, the source electrode 108, and the drain electrode 110. The semiconductor pattern is formed to be separated between the cell and the cell to prevent signal interference between the cells by the semiconductor pattern.

The pixel electrode 122 includes a transparent conductive film 170 in the pixel region 105 and a gate metal formed on the transparent conductive film 170 in an area overlapping the drain electrode 110 and the storage electrode 128 of the thin film transistor. Film 172. The pixel electrode 122 is directly connected to the drain electrode 110 of the thin film transistor 130.

Accordingly, a vertical electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor 130 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the upper array substrate and the lower array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 105 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 140 overlaps the gate line 102 with the gate line 102, the gate insulating pattern 112, the active layer 114, and the ohmic contact layer 116 interposed therebetween, and the pixel electrode 122. The storage electrode 128 is directly connected. The storage capacitor 140 allows the pixel signal charged in the pixel electrode 122 to be stably maintained until the next pixel signal is charged.

The gate pad 150 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the gate line 102. The gate pad 150 is formed in a structure in which at least a portion of the transparent conductive film 170 extending from the gate line 102 is exposed. That is, the gate pad 150 may be formed of the transparent conductive film 170 or may be formed of the transparent conductive film 170 and the gate metal layer 172 formed on the transparent conductive film 170. When formed of the gate metal layer and the transparent conductive layer, the gate pad 150 is formed to partially expose the transparent conductive layer 170 through the gate contact hole penetrating through the gate insulating pattern 112 and the gate metal layer.

The data pad 160 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104. To this end, the data pad 160 is electrically connected to the data pad 104 and the data contact hole 180 formed of a metal different from the data pad 160. The data pad 160 may include a transparent conductive film 170 and a gate metal film 172 formed on the transparent conductive film 170 in an area overlapping the data line 104. The data contact hole 180 penetrates through the ohmic contact layer 116, the active layer 114, and the gate insulating pattern 112 to expose the gate metal layer 172 of the data pad.

As described above, in the thin film transistor array substrate according to the present invention, the transparent conductive film 170 of the gate pad 150 and the data pad 160 is exposed, thereby improving reliability of corrosion. In addition, the gate pad 150 and the data pad 160 formed to expose the transparent conductive film 170 may prevent a disconnection failure even in a repetitive attach process of TCP.

6A and 6B are plan and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

6A and 6B, a pixel electrode 122 including a gate metal film 172 on the lower substrate 101 by a first mask process; A gate pattern including a two-layered gate line 102, a gate electrode 106, a gate pad 150, and a data pad 160 is formed.

To this end, the transparent conductive film 170 and the gate metal film 172 are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Here, the transparent conductive film 170 is a transparent conductive material such as ITO, TO, ITZO, IZO, etc., the gate metal film 172 is an aluminum (Al) -based metal, including molybdenum (AlNd), molybdenum ( Metals such as Mo, copper (Cu), chromium (Cr), tantalum (Ta), titanium (Ti) and the like are used. Subsequently, the transparent conductive film 170 and the gate metal layer 172 are patterned by a photolithography process and an etching process using a first mask to form the gate line 102, the gate electrode 106, and the gate pad 150 having a two-layer structure. A gate pattern including a data pad 160; The pixel electrode 122 including the gate metal film 172 is formed.

7A and 7B are plan views and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

7A and 7B, the gate insulating pattern 112 is formed on the lower substrate 101 on which the gate pattern, the data pad 160, and the pixel electrode 122 are formed by the second mask process; A semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed. A data contact hole 180 is formed through the semiconductor pattern and the gate insulating pattern 112 to expose the gate metal layer 172 of the data pad 160. The second mask process will be described in detail with reference to FIGS. 8A to 8C as follows.

First, as shown in FIG. 8A, the gate insulating layer 111 and the first and second semiconductor layers 115 and 117 are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. . In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the material of the gate insulating layer 111, and the first semiconductor layer 115 may be formed of amorphous silicon that is not doped with impurities. As the second semiconductor layer 117, amorphous silicon doped with N-type or P-type impurities is used. Subsequently, the photoresist film 216 is entirely formed on the second semiconductor layer 117, and then the second mask 210 is aligned on the lower substrate 101. The second mask 210 includes a mask substrate 212 made of a transparent material and a blocking portion 214 formed in the blocking region S2 of the mask substrate 212. Here, the region where the mask substrate 212 is exposed becomes the exposure region S1. By exposing and developing the photoresist film 216 using the second mask 210, the photoresist pattern 218 is formed to correspond to the blocking portion 214 of the second mask 210 as shown in FIG. 8B. do. As the first and second semiconductor layers 115 and 117 and the gate insulating layer 111 are patterned by an etching process using the photoresist pattern 218, the gate line 102, the gate electrode 106, and A gate insulating pattern 112 overlapping the gate pattern including the gate pad 150, and an active layer 114 and an ohmic contact layer 116 having a wider width than the gate pattern on the gate insulating pattern 112. A semiconductor pattern is formed. This is to prevent the channel characteristics when the semiconductor pattern is narrower than the width of the gate electrode 106. In addition, a data contact hole 180 is formed through the gate insulating pattern 112 and the semiconductor pattern to expose the gate metal layer 172 of the data pad 160.

9A and 9B are plan views and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

As shown in FIGS. 9A and 9B, the data line 104, the source electrode 108, and the drain electrode 110 are formed on the lower substrate 101 on which the gate insulating pattern 112 and the semiconductor pattern are formed by the third mask process. And a data pattern including the storage electrode 128. In addition, at least a portion of the gate metal layer 172 included in the data pad 160 and the pixel electrode 122 is removed to expose the transparent conductive layer 170.

The third mask process will be described in detail with reference to FIGS. 10A to 10E as follows.

As shown in FIG. 10A, the data metal layer 109 and the photoresist film 228 are sequentially formed on the lower substrate 101 on which the semiconductor pattern is formed by a deposition method such as sputtering. Here, the data metal layer 109 is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Then, the third mask 220, which is a partial exposure mask, is aligned above the lower substrate 101. The third mask 220 includes a mask substrate 222 made of a transparent material, a blocking portion 224 formed in the blocking region S2 of the mask substrate 222, and a partial exposure region S3 of the mask substrate 222. The formed diffraction exposure part 226 (or semi-transmissive part) is provided. Here, the region where the mask substrate 222 is exposed becomes the exposure region S1. After exposing and developing the photoresist film 228 using the third mask 220, as shown in FIG. 10B, the blocking part 224 and the diffraction exposure part 226 of the third mask 220 may be formed. A photoresist pattern 230 having a step is formed in the blocking region S2 and the partial exposure region S3. That is, the photoresist pattern 230 formed in the partial exposure region S3 has a second height lower than that of the photoresist pattern 230 having the first height formed in the blocking region S2.

The data metal layer 109 is patterned by a wet etching process using the photoresist pattern 230 as a mask, so that the storage electrode 128, the data line 104, the source electrode 108 connected to the data line 104, and the drain are formed. The data pattern including the electrode 110 is formed.

Thereafter, the exposed gate metal layer 172 is removed by wet etching using the gate insulating patterns 112 and the semiconductor patterns 114 and 116 as masks. That is, the gate metal film 172 included in the data pad 160 and the pixel electrode 122 is removed to expose the transparent conductive film 170 included in the 160 and 122.

The active layer 114 and the ohmic contact layer 116 are formed along the data pattern by a dry etching process using the photoresist pattern 230 as a mask. At this time, the active layer 114 and the ohmic contact layer 116 positioned in the remaining region except for the active layer 114 and the ohmic contact layer 116 overlapping the data pattern are removed. This is to prevent a short circuit between cells due to the semiconductor pattern including the active layer 114 and the ohmic contact layer 116.

Subsequently, in the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 230 having the second height in the partial exposure area S3 is removed as shown in FIG. 10C, and the blocking area S2 is removed. The photoresist pattern 230 having the first height is in a state where the height is lowered. In the etching process using the photoresist pattern 230, the data metal layer and the ohmic contact layer 116 formed in the channel portion of the thin film transistor, ie, the channel portion of the thin film transistor, are removed, thereby draining the drain electrode 110 and the source electrode 108. This is separated. The photoresist pattern 230 remaining on the data pattern is removed by a stripping process as shown in FIG. 10D.

Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed, as shown in FIG. 10E. As the passivation layer 118, an inorganic insulating material such as the gate insulating pattern 112 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB may be used.

FIG. 11 is a plan view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view illustrating a thin film transistor array substrate taken along a line “XII-XII ′” in FIG. 11.

11 and 12, in the thin film transistor array substrate according to the second embodiment of the present invention, the data pad has a transparent conductive film through the second data contact hole in comparison with the thin film transistor array substrate illustrated in FIGS. 4 and 5. It is provided with the same components except that it is formed to be exposed. Accordingly, detailed description of the same components will be omitted.

The data pad 160 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104. The data pad 160 passes through the ohmic contact layer 116, the active layer 114, and the gate insulating pattern 112 to expose the gate metal layer 172 of the data pad through the first data contact hole 180. It is connected to the data line 104.

The data pad 160 includes a transparent conductive film 170 and a gate metal film 172 having a second data contact hole 162 on the transparent conductive film 170. The data pad 160 exposes the transparent conductive film 170 through the second contact hole 162.

As described above, in the thin film transistor array substrate according to the second embodiment of the present invention, since the transparent conductive film 170 of the gate pad 150 and the data pad 160 is exposed, reliability of corrosion is improved. In addition, the gate pad 150 and the data pad 160 formed to expose the transparent conductive film 170 may prevent a disconnection failure even in a repetitive attach process of TCP.

13A to 13C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

Referring to FIG. 13A, the pixel electrode 122 is disposed on the lower substrate 101 by a first mask process; A gate pattern including a two-layered gate line 102, a gate electrode 106, a gate pad 150, and a data pad 160 is formed.

To this end, the transparent conductive film and the gate metal film are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Subsequently, the transparent conductive film and the gate metal layer are patterned by a photolithography process and an etching process using a first mask to form a gate layer 102, a gate electrode 106, a gate pad 150, and a data pad 160 having a two-layer structure. A gate pattern comprising a; The pixel electrode 122 including the gate metal film 172 is formed.

Referring to FIG. 13B, a gate insulating pattern 112 is formed on a lower substrate 101 on which a gate pattern, a data pad 160, and a pixel electrode 122 are formed in a second mask process; A semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed. The first and second data contact holes 180 and 162 penetrating the gate insulating pattern 112 and the semiconductor pattern are formed.

To this end, the gate insulating film and the first and second semiconductor layers are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. Subsequently, the gate insulating layer and the first and second semiconductor layers are patterned by a photolithography process and an etching process using a second mask, so that the width of the gate insulation pattern 112 and the gate insulation pattern 112 is greater than that of the gate pattern. A semiconductor pattern including a wide active layer 114 and an ohmic contact layer 116 is formed. In addition, first and second data contact holes 180 and 162 may be formed through the gate insulating pattern 112 and the semiconductor pattern to expose the gate metal layer 172 of the data pad 160.

Referring to FIG. 13C, a data line 104, a source electrode 108, a drain electrode 110, and a storage electrode may be formed on a lower substrate 101 on which a gate insulating pattern 112 and a semiconductor pattern are formed in a third mask process. A data pattern including 128) is formed. In addition, the gate metal layer 172 included in the gate pad 150 and the pixel electrode 122 is partially removed to expose the transparent conductive layer 170, and the data pad exposed through the second data contact hole 162. The gate metal layer 172 of the 160 is removed to expose the transparent conductive layer 170 of the data pad 160.

To this end, a data metal layer is formed on the lower substrate 101 by a deposition method such as sputtering. The data metal layer 109 is patterned by a wet etching process using a stepped photoresist pattern formed by a photolithography process using a partial exposure mask as a mask so that the storage electrode 128, the data line 104, and the data line 104 are formed. The data pattern including the connected source electrode 108 and the drain electrode 110 is formed. The data line 104 is in contact with the gate metal layer 172 of the data pad 160 through the first data contact hole 180.

Thereafter, the exposed gate metal layer 172 is partially removed by wet etching using the gate insulating patterns 112 and the semiconductor patterns 114 and 116 as masks. That is, the gate metal layer 172 included in the gate pad 150 and the pixel electrode 122 is partially removed to expose the transparent conductive layer 170 included in the 150 and 122 and the second data contact hole 162. The gate metal layer 172 of the data pad 160 exposed through the gate metal layer 172 is removed to expose the transparent conductive layer 170 of the data pad 160.

The active layer 114 and the ohmic contact layer 116 are formed along the data pattern by a dry etching process using the photoresist pattern as a mask. Subsequently, a relatively low height photoresist pattern is removed by an ashing process, and a relatively high height photoresist pattern is reduced in height. The drain electrode 110 and the source electrode 108 are separated by removing the data metal layer and the ohmic contact layer 116 formed in the channel portion of the thin film transistor using the photoresist pattern. Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed.

14 and 15 are a plan view and a cross-sectional view of a liquid crystal display including the thin film transistor array substrate illustrated in FIGS. 4 and 5, and FIGS. 16 and 17 illustrate the thin film transistor array substrate illustrated in FIGS. 11 and 12. It is a top view and sectional drawing which shows the liquid crystal display device containing.

The liquid crystal display shown in FIGS. 14 to 17 uses the thin film transistor array substrate and the upper substrate 300 on which the color filter array 302 is formed using the material 304 according to the first and second embodiments of the present invention. To be completed. In this case, the upper substrate 300 is bonded to the pad region where the gate pad 150 and the data pad 160 are formed in the thin film transistor array substrate.

Thereafter, the passivation layer 118 of the pad region exposed by the upper substrate 300 is removed through the pad open process to expose the transparent conductive layer 170 included in the gate pad 150 and the data pad 160. In this case, the transparent conductive film 170 is completely exposed in the data pad 160 illustrated in FIGS. 14 and 15, and the data pad 170 illustrated in FIGS. 16 and 16 includes the second data contact hole 162. Through the transparent conductive film 170 is partially exposed.

Subsequently, TCPs 250 and 260 in which drive ICs are mounted on the pad region of the thin film transistor array substrate are attached using an anisotrophic conductive film (ACF) 192 including conductive balls 190. Accordingly, the output pads 176 and 182 formed on the TCP 250 and 260 are electrically connected to the gate pad 150 and the data pad 160 through the conductive ball 190 of the ACF 192. Specifically, the gate TCP pad 182 formed on the base film 174 of the gate TCP 260 is formed on the transparent conductive film 170 of the gate pad 150 and the base film 174 of the data TCP 250. The formed data TCP pad 176 is electrically connected to the data pad 160 through the ACF 192. In this case, since the gate pad 150 and the data pad 160 have a structure in which the transparent conductive film 170, which is a metal layer having high strength and corrosion resistance, is exposed, even if the TCP (250, 260) attaching process is repeated, failure of the pad is prevented. .

Meanwhile, in the pad opening process, each pad exposed by the upper substrate 300 is sequentially scanned by using the plasma generated by the atmospheric pressure plasma generator, or the pads are collectively scanned for each pad unit to generate the gate pad 150 and the data. The transparent conductive film 170 of the pad 160 is exposed. Alternatively, a plurality of liquid crystal panels in which the upper substrate 300 and the thin film transistor array substrate are bonded to each other are inserted into the chamber, and the protective layer 118 of the pad region exposed by the upper array substrate 300 is etched using atmospheric pressure plasma to etch the gate. The transparent conductive film 170 of the pad 150 and the data pad 160 is exposed. Alternatively, the entire liquid crystal cell to which the upper substrate 300 and the thin film transistor array substrate are bonded is immersed in an etchant, or only a pad region including the gate pad 150 and the data pad 160 is immersed in the etchant, thereby providing the gate pad 150 and The transparent conductive film 170 of the data pad 160 is exposed.

Meanwhile, the pad opening process of exposing the pads by partially removing the protective film of the thin film transistor array substrate may also be performed by an etching process using the alignment layer as a mask before bonding.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention form the pixel electrode and the gate pattern in the first mask process, the gate insulating film and the semiconductor pattern in the second mask process, A thin film transistor array substrate is completed by forming a data pattern and exposing a transparent conductive film included in the pixel electrode, the gate pad, and the data pad. As such, by forming the thin film transistor array substrate in a three mask process, the structure and manufacturing process may be simplified, manufacturing cost may be reduced, and manufacturing yield may be improved. In addition, the liquid crystal display according to the present invention and a manufacturing method thereof have a structure in which a transparent conductive film, which is a metal having high strength and corrosion resistance, is exposed so as to prevent disconnection of data pads, and is connected to TCP through ACF.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A gate line formed on the substrate; A data line intersecting the gate line and a gate insulating layer to determine a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode formed in the pixel region and connected to the thin film transistor; A gate pad connected to the gate line; A data pad formed to expose a transparent conductive film on the substrate so as to be in contact with the substrate, and connected through a first contact hole at an end of the data line, the data pad including the transparent conductive film; It is provided with a conductive film connected to the transparent conductive film, And the transparent conductive film of the data pad is connected to the conductive film via a second data contact hole penetrating through the gate insulating film and the gate metal film of the data pad. delete delete The method of claim 1, The data pad is And a gate metal film formed on the transparent conductive film and a region overlapping the data line on the transparent conductive film. The method of claim 1, The data pad is And a gate metal film having the second data contact hole on the transparent conductive film. delete The method of claim 1, The thin film transistor is A gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode connected to the pixel electrode; And a semiconductor pattern for forming a channel between the source electrode and the drain electrode. The method of claim 7, wherein And the pixel electrode includes a transparent conductive film and a gate metal film formed on a region of the transparent conductive film overlapping with the drain electrode. The method according to any one of claims 1, 4, 5 and 8, The transparent conductive film includes at least one of TO, ITO, IZO, and ITZO, And the gate metal layer comprises at least one of aluminum-based metal, Mo, Cu, Cr, Ta, and Ti. A signal line including a gate line and a data line intersecting a gate insulating film on a substrate, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, and a connection with the gate line Forming a gate pad, wherein the data pad is formed to expose a transparent conductive film on the substrate to be in contact with the substrate and is connected through a first contact hole at an end of the data line; And Attaching a conductive film on the transparent conductive film of the data pad, And the transparent conductive film of the data pad is connected to the conductive film via a second data contact hole penetrating through the gate insulating film and the gate metal film of the data pad. delete delete The method of claim 10, The data pad is And a gate metal film formed on the transparent conductive film and a region overlapping the data line on the transparent conductive film. The method of claim 10, The data pad is And a gate metal film having the second data contact hole on the transparent conductive film and the transparent conductive film. delete The method of claim 10, And the pixel electrode comprises a transparent conductive film and a gate metal film formed on a region of the transparent conductive film overlapping with a drain electrode of the thin film transistor. The method according to any one of claims 10, 13, 14 and 16, The transparent conductive film includes at least one of TO, ITO, IZO, and ITZO, The gate metal film may include at least one of aluminum-based metal, Mo, Cu, Cr, Ta, and Ti.

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