KR20050055384A - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a method of manufacturing the same that can reduce the number of mask processes.

The liquid crystal display panel according to the present invention comprises the steps of preparing a color filter array substrate; A gate line and a data line facing the color filter array substrate and intersecting a gate insulating pattern on a lower substrate, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, A gate pad connected to the gate line to expose the transparent conductive film, a data pad connected to the data line to expose the transparent conductive film, and a transparent conductive layer formed in an area overlapping the color filter array substrate; Providing a thin film transistor array substrate having a protective film exposing the film; Bonding the thin film transistor array substrate and the color filter array substrate to each other using a material to expose a pad region including the gate pad and the data pad; Exposing the transparent conductive film in a pad region by removing the protective film using the color filter array substrate as a mask; At least one of the gate line and the data line may be formed in at least one layer structure including a copper metal layer.

Description

Liquid crystal display panel and manufacturing method therefor {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}

The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel and a method of manufacturing the same that can simplify the process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display device, the liquid crystal display device drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display includes a thin film transistor array substrate (lower array substrate) and a color filter array substrate (upper array substrate) bonded together to face each other, a spacer for keeping a cell gap constant between the two substrates, and a liquid crystal filled in the cell gap. Equipped.

The thin film transistor array substrate is composed of a plurality of signal wires and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation and a black matrix for light leakage prevention, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, an inspection process, and the like. Accordingly, in recent years, a four-mask process that reduces one mask process in a five-mask process, which is a standard mask process of a thin film transistor array substrate, has emerged.

FIG. 1 is a plan view illustrating a thin film transistor array substrate using a conventional four mask process, and FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along a line “II-II ′” in FIG. 1.

1 and 2, a thin film transistor array substrate of a conventional liquid crystal display panel includes a gate line 2 and a data line 4 formed to intersect a gate insulating layer 12 therebetween on a lower substrate 1; A thin film transistor 30 formed at each intersection thereof, a pixel electrode 22 formed at the pixel region provided at the intersection structure, a storage capacitor 40 formed at an overlapping portion of the gate line 2 and the storage electrode 28, and And a gate pad 50 connected to the gate line 2, and a data pad 60 connected to the data line 4.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region 5.

The thin film transistor 30 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 22 in response to the gate signal of the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode connected to the pixel electrode 22. 10). In addition, the thin film transistor 30 further includes an active layer 14 which overlaps with the gate electrode 6 and the gate insulating layer 12 therebetween to form a channel between the source electrode 8 and the drain electrode 10. .

The active layer 14 also overlaps the data line 4, the data pad lower electrode 62, and the storage electrode 28. On the active layer 14, an ohmic contact layer 16 for ohmic contact with the data line 4, the source electrode 8, the drain electrode 10, the data pad lower electrode 62, and the storage electrode 28 is further included. Is formed.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 through the first contact hole 20 penetrating the passivation layer 18 and is formed in the pixel region 5.

Accordingly, an electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor 30 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the lower array substrate and the upper array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 40 includes a gate line 2, a storage electrode 28 overlapping the gate line 2 with the gate insulating layer 12, the active layer 14, and the ohmic contact layer 16 therebetween. do. The storage electrode 28 is connected to the pixel electrode 22 through the second contact hole 42 formed in the passivation layer 18. The storage capacitor 40 allows the pixel signal charged in the pixel electrode 22 to remain stable until the next pixel signal is charged.

The gate pad 50 is connected to a gate driver (not shown) to supply a gate signal to the gate line 2. The gate pad 50 has a gate pad lower electrode 52 extending from the gate line 2 and a third contact hole 56 penetrating the gate insulating layer 12 and the passivation layer 18. And a gate pad upper electrode 54 connected to 52.

The data pad 60 is connected to a data driver (not shown) to supply a data signal to the data line 4. The data pad 60 is connected to the data pad lower electrode 62 through a data pad lower electrode 62 extending from the data line 4 and a fourth contact hole 66 passing through the passivation layer 18. It consists of a data pad upper electrode 64.

A method of manufacturing a thin film transistor array substrate of a liquid crystal display panel having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, a gate pattern including a gate line 2, a gate electrode 6, and a gate pad lower electrode 52 is formed on the lower substrate 1 using a first mask process.

In detail, the gate metal layer is formed on the lower substrate 1 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate pattern including the gate line 2, the gate electrode 6, and the gate pad lower electrode 52. Here, an aluminum metal or the like is used as the gate metal layer.

Referring to FIG. 3B, a gate insulating layer 12 is coated on the lower substrate 1 on which the gate pattern is formed. A semiconductor pattern including an active layer 14 and an ohmic contact layer 16 on the gate insulating layer 12 using a second mask process; A data pattern including a data line 4, a source electrode 8, a drain electrode 10, a data pad lower electrode 62, and a storage electrode 28 is formed.

In detail, the gate insulating layer 12, the amorphous silicon layer, the n + amorphous silicon layer, and the data metal layer are sequentially formed on the lower substrate 1 on which the gate pattern is formed by a deposition method such as PECVD or sputtering. Here, as the material of the gate insulating film 12, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the data metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

Subsequently, a photoresist pattern is formed on the data metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the data metal layer is patterned by a wet etching process using a photoresist pattern to include a data line 4, a source electrode 8, a drain electrode 10 integrated with the source electrode 8, and a storage electrode 28. A data pattern is formed.

Then, the ohmic contact layer 14 and the active layer 16 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

After the photoresist pattern having a relatively low height is removed from the channel portion by an ashing process, the data metal layer and the ohmic contact layer 16 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 8 and the drain electrode 10.

Subsequently, the photoresist pattern remaining on the data pattern is removed by a stripping process.

Referring to FIG. 3C, the passivation layer 18 including the first to fourth contact holes 20, 42, 56, and 66 is formed on the gate insulating layer 12 on which the data pattern is formed by using a third mask process. do.

In detail, the protective film 18 is entirely formed on the gate insulating film 12 on which the data pattern is formed by a deposition method such as PECVD. Subsequently, the passivation layer 18 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 20, 42, 56, and 66. The first contact hole 20 penetrates the passivation layer 18 to expose the drain electrode 10, and the second contact hole 42 penetrates the passivation layer 18 to expose the storage electrode 28. The third contact hole 56 penetrates the passivation layer 18 and the gate insulating layer 12 to expose the gate pad lower electrode 52, and the fourth contact hole 66 penetrates the passivation layer 18 to lower the data pad. The electrode 62 is exposed. Here, when a dry etching ratio metal such as molybdenum (Mo) is used as the data metal, each of the first, second, and fourth contact holes 20, 42, and 66 may have a drain electrode 10 and a storage electrode 28. As a result, the data pad lower electrode 62 penetrates to expose side surfaces thereof.

As the material of the protective film 18, an inorganic insulating material such as the gate insulating film 12 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, a transparent conductive pattern including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64 is formed on the passivation layer 18 using a fourth mask process.

In detail, the transparent conductive film is apply | coated on the protective film 18 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive layer is patterned through a photolithography process and an etching process using a fourth mask to form a transparent conductive pattern including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64. The pixel electrode 22 is electrically connected to the drain electrode 10 through the first contact hole 20 and electrically connected to the storage electrode 28 through the second contact hole 42. The gate pad upper electrode 54 is electrically connected to the gate pad lower electrode 52 through the third contact hole 56. The data pad upper electrode 64 is electrically connected to the data pad lower electrode 62 through the fourth contact hole 66.

Herein, materials for the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (IZO). ) Is used.

As described above, the conventional thin film transistor array substrate and the method of manufacturing the same can reduce the number of manufacturing steps and reduce manufacturing costs in proportion to the case of using the 5 mask process by employing a four mask process. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for a method of further reducing the manufacturing cost by simplifying the manufacturing process.

Also, in recent years, as the substrate becomes larger, signal lines made of low-resistance metals are required to prevent image degradation due to signal delay.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can reduce the number of mask processes.

In order to achieve the above object, the liquid crystal display panel according to the present invention includes a color filter array substrate; A gate line and a data line opposed to and bonded to the color filter array substrate, the thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, and the gate A gate pad connected to a line, the gate pad including a transparent conductive film, a data pad connected to the data line, and a transparent pad formed in an area overlapping the color filter array substrate. A thin film transistor array substrate having a protective film exposing a conductive film, wherein at least one of the gate line and the data line is formed in at least one layer structure including a copper metal layer.

The liquid crystal display panel includes: a gate insulating pattern formed to insulate a gate pattern including the gate line and a gate electrode and a source / drain pattern including the data line, a source electrode, and a drain electrode; A semiconductor pattern formed on the gate insulating pattern and partially overlapping the gate pattern; And a barrier metal pattern formed between the semiconductor pattern and the source / drain pattern and formed in the same pattern as the semiconductor pattern.

The semiconductor pattern may include an active layer forming a channel between the source and drain electrodes and overlapping the gate pattern; And an ohmic contact layer formed on the active layer and formed in the same pattern as the barrier metal pattern.

The barrier metal pattern is formed of at least one of molybdenum (Mo), chromium (Cr), tungsten (W) and titanium (Ti).

In order to achieve the above object, the manufacturing method of the liquid crystal display panel according to the present invention comprises the steps of preparing a color filter array substrate; A gate line and a data line facing the color filter array substrate and intersecting a gate insulating pattern on a lower substrate, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, A gate pad connected to the gate line to expose the transparent conductive film, a data pad connected to the data line to expose the transparent conductive film, and a transparent conductive layer formed in an area overlapping the color filter array substrate; Providing a thin film transistor array substrate having a protective film exposing the film; Bonding the thin film transistor array substrate and the color filter array substrate to each other using a material to expose a pad region including the gate pad and the data pad; Exposing the transparent conductive film in a pad region by removing the protective film using the color filter array substrate as a mask; At least one of the gate line and the data line may be formed in at least one layer structure including a copper metal layer.

The preparing of the thin film transistor array substrate may include forming gate patterns and pixel electrodes including a gate line, a gate electrode, a first gate pad electrode, and a second data pad electrode including a transparent conductive layer and a copper metal layer on the substrate. Making a step; A gate insulating pattern, a semiconductor pattern having the same pattern as the gate insulating pattern, and a barrier metal pattern are formed on the substrate on which the gate patterns and the pixel electrode are formed, and the transparent conductive film included in the data pad electrode, the gate pad electrode, and the pixel electrode is formed. Exposing; Forming a data pattern including at least one layer of a metal including a copper metal layer on the substrate on which the barrier metal pattern, the semiconductor pattern, and the gate insulating pattern are formed, the data pattern including a data line, a source electrode, and a drain electrode connected to the data pad electrode; Steps; And forming a protective film on the substrate on which the data pattern is formed.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 14.

4 is a plan view illustrating a thin film transistor array substrate according to a first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating a thin film transistor array substrate taken along the line “V-V ′” in FIG. 4.

The thin film transistor array substrate illustrated in FIGS. 4 and 5 includes a gate line 102 and a data line 104 formed to intersect on the lower substrate 101 with a gate insulating layer 112 interposed therebetween, and a thin film formed at each intersection thereof. The transistor 130, the pixel electrode 122 formed in the pixel region 105 provided in an intersecting structure, the storage capacitor 140 formed in an overlapping portion of the pixel electrode 122 and the gate line 102, and the gate line. A gate pad 150 extending from 102 and a data pad 160 extending from data line 104.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in an intersecting structure to define the pixel region 105.

The thin film transistor 130 keeps the pixel signal of the data line 104 charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line 102. To this end, the thin film transistor 130 may include a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode connected to the pixel electrode 122. 110).

In addition, the thin film transistor 130 includes semiconductor patterns 114 and 116 that form a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 and the gate insulating layer 112 therebetween. .

The semiconductor pattern includes an active layer 114 that forms a channel between the source electrode 108 and the drain electrode 110 and partially overlaps the gate pattern with the gate insulating layer 112 therebetween. In addition, the semiconductor pattern is formed on the active layer 114 to contact the barrier metal pattern 180 that is in contact with the data line 104, the storage electrode 128, the source electrode 108, and the drain electrode 110. The contact layer 116 is further provided. The semiconductor pattern is formed to be separated between the cell and the cell to prevent signal interference between the cells by the semiconductor pattern.

The pixel electrode 122 is formed of the transparent conductive film 170 in the pixel region 105 to be directly connected to the drain electrode 110 of the thin film transistor 130.

Accordingly, a vertical electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor 130 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the upper array substrate and the lower array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 105 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 140 overlaps the gate line 102 with the gate line 102 and the gate insulating layer 112, the active layer 114, the ohmic contact layer 116, and the barrier metal pattern 180 interposed therebetween. The storage electrode 128 is directly connected to the pixel electrode 122. The storage capacitor 140 allows the pixel signal charged in the pixel electrode 122 to be stably maintained until the next pixel signal is charged.

The gate pad 150 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the gate line 102. To this end, the gate pad 150 includes a gate pad electrode 152 extending from the gate line 102 and a gate contact hole 154 exposing the transparent conductive film 170 of the gate pad electrode 152. The gate pad electrode 152 includes a transparent conductive film 170 and a gate metal film 172 formed on the transparent conductive film 170. The gate contact hole 154 penetrates through the gate insulating film 112 and the gate metal film 172 to expose the transparent conductive film 170 of the gate pad electrode 152. As such, the gate pad 150 is formed to expose the transparent conductive film 170 that is resistant to corrosion, thereby preventing oxidation corrosion due to moisture, thereby improving reliability.

The data pad 160 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104. To this end, the data pad 160 includes a data pad electrode 162 in contact with the data line 104 and a data contact hole 164 exposing the transparent conductive film 170 of the data pad electrode 162. . Here, the data pad electrode 162 is made of a transparent conductive film 170 and a gate metal film formed on the transparent conductive film 170. The data contact hole 164 penetrates the barrier metal pattern 180, the ohmic contact layer 116, the active layer 114, the gate insulating layer 112, and the gate metal layer 172 of the data pad electrode 160. The transparent conductive film 170 of the electrode 162 is exposed. As such, the data pad 160 is formed to expose the transparent conductive film 170 resistant to corrosion, thereby preventing oxidation corrosion due to moisture, thereby improving reliability.

Meanwhile, in the thin film transistor array substrate according to the present invention, a gate pattern including the gate electrode 106, the gate line 102, and the gate pad electrode 152 may be formed on the transparent conductive layer 170 and the transparent conductive layer 170. The gate metal film 172 is formed in a stacked structure. Here, the transparent conductive film 170 is made of a transparent conductive material such as ITO, TO, ITZO, IZO, etc., and the gate metal film 172 is made of a metal including copper (Cu). Here, the gate line 102 formed of copper has a lower resistivity than the gate line formed of a metal having a relatively large resistivity value (0.046) such as AlNd, Al, Cr, etc., thereby preventing signal delay in a large area panel. can do.

The data pattern including the source electrode 108, the drain electrode 110, the data line 104, and the storage electrode 128 is formed of a metal including copper (Cu) or the like. Here, the data line 104 formed of copper has a relatively lower resistivity value than the data line formed of a metal having a relatively large resistivity value (0.046), such as AlNd, Al, Cr, etc., thereby preventing signal delay in a large area panel. Can be.

A barrier metal pattern 180 formed of molybdenum (Mo), chromium (Cr), tungsten (W) or titanium (Ti) is disposed between the data pattern and the semiconductor pattern. In particular, the barrier metal pattern 180 improves the adhesion between the data pattern and the semiconductor pattern and melts the data pattern formed of copper (Cu) at a high temperature (for example, about 200 ° C.) to the channel portion of the thin film transistor 130. It prevents penetration and diffusion to prevent deterioration of thin film transistor characteristics.

6A and 6B are plan and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

6A and 6B, a pixel electrode 122 is formed on the lower substrate 101 by a first mask process; A gate pattern including a gate line 102, a gate electrode 106, a gate pad electrode 152, and a data pad electrode 162 having a two-layer structure is formed.

To this end, the transparent conductive film 170 and the gate metal film 172 are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Here, the transparent conductive film 170 is a transparent conductive material such as ITO, TO, ITZO, IZO, etc., the gate metal film 172 is a good electrical conductivity metal containing copper (Cu). Subsequently, the transparent conductive film 170 and the gate metal layer 172 are patterned by a photolithography process and an etching process using a first mask to form a gate line 102, a gate electrode 106, and a gate pad electrode 152 having a two-layer structure. ), A pixel electrode 122 including a data pad electrode 162 and a gate metal film 172 is formed.

7A and 7B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

7A and 7B, a gate insulating film 112 is formed on a lower substrate 101 on which a gate pattern is formed by a second mask process; A semiconductor pattern including an active layer 114 and an ohmic contact layer 116; The barrier metal pattern 180 having the same pattern as the semiconductor pattern is formed. The gate metal layer 172 included in the pixel electrode 122 is removed to expose the transparent conductive layer 170. In addition, a data contact hole 164 and a gate contact hole 154 exposing the transparent conductive film included in each of the data pad electrode 162 and the gate pad electrode 152 are formed.

To this end, the gate insulating layer, the first and second semiconductor layers, and the barrier metal layer are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. Herein, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film, and the first semiconductor layer is made of amorphous silicon without doping impurities, and the second semiconductor layer is made of N. Amorphous silicon doped with an impurity of a type or P type is used, and as the barrier metal layer, molybdenum (Mo), chromium (Cr), tantalum (Ta), tungsten (W), titanium (Ti), and the like are used. Subsequently, the gate insulating film, the first and second semiconductor layers, and the barrier metal layer are patterned by a photolithography process and an etching process using a second mask, thereby forming a semiconductor pattern including an active layer 114 and an ohmic contact layer 116, and a semiconductor. The gate insulating film 112 and the barrier metal pattern 180 having the same pattern as the pattern are formed. In this case, the semiconductor pattern and the gate insulating layer are formed to expose the pixel electrode 122, the gate pad 150, and the data pad 160.

Thereafter, the exposed gate metal layer 172 is removed by wet etching using the gate insulating layer 112, the semiconductor patterns 114 and 116, and the barrier metal pattern 180 as a mask. That is, the transparent conductive film 170 included in the 122 is removed by the gate metal film 172 included in the pixel electrode 122. In addition, a portion of the gate metal layer 172 included in each of the gate pad electrode 152 and the data pad electrode 162 is removed to expose the gate contact hole 154 and the data contact to expose the transparent conductive layer 170 included therein. Holes 164 are formed. The data contact hole 164 may pass through the gate metal layer 172, the gate insulating layer 112, the semiconductor patterns 114 and 116, and the barrier metal pattern 180 of the data pad electrode 162 to pass through the transparent conductive layer 170. The gate contact hole 154 penetrates the gate metal layer 172, the gate insulating layer 112, the semiconductor patterns 114 and 116, and the barrier metal pattern 180 of the gate pad electrode 152 to expose the transparent conductive layer 170. Expose

8A and 8B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

8A and 8B, the data line 104, the source electrode 108, and the lower portion of the substrate 101 on which the gate insulating layer 112, the semiconductor pattern, and the barrier metal pattern 180 are formed in the third mask process are formed. A data pattern including the drain electrode 110 and the storage electrode 128 is formed. A detailed description thereof will be described in detail with reference to FIGS. 9A to 9E.

First, as illustrated in FIG. 9A, the data metal layer 109 and the photoresist layer 328 are sequentially formed on a lower substrate 101 on which the barrier metal pattern 180 is formed, such as sputtering. Here, the data metal layer 109 is made of a metal such as copper (Cu).

Then, the third mask 320, which is a partial exposure mask, is aligned above the lower substrate 101. The third mask 320 includes a mask substrate 322 made of a transparent material, a blocking portion 324 formed in the blocking region S2 of the mask substrate 322, and a partial exposure region S3 of the mask substrate 322. The formed diffraction exposure part 326 (or semi-transmissive part) is provided. Here, the region where the mask substrate 322 is exposed becomes the exposure region S1. By exposing and developing the photoresist film 328 using the third mask 320, the blocking portion 324 and the diffraction exposure portion 326 of the third mask 320 are shown in FIG. 9B. A photoresist pattern 330 having a step is formed in the blocking region S2 and the partial exposure region S3. That is, the photoresist pattern 330 formed in the partial exposure area S3 has a second height lower than that of the photoresist pattern 330 having the first height formed in the blocking area S2.

The data metal layer 109 is patterned by a wet etching process using the photoresist pattern 330 as a mask, so that the storage electrode 128, the data line 104, the source electrode 108 connected to the data line 104, and the drain are formed. The data pattern including the electrode 110 is formed.

The active layer 114, the ohmic contact layer 116, and the barrier metal pattern 180 are formed along the data pattern by a dry etching process using the photoresist pattern 330 as a mask. In this case, the active layer 114, the ohmic contact layer 116, and the barrier metal pattern 180 positioned in the remaining regions except for the active layer 114, the ohmic contact layer 116, and the barrier metal pattern 180 that overlap the data pattern. ) Is removed.

Subsequently, the photoresist pattern 330 having the second height in the partial exposure area S3 is removed by an ashing process using an oxygen (O ₂ ) plasma as illustrated in FIG. 9C, and the blocking area S2 is removed. The photoresist pattern 330 having the first height is in a state where the height is lowered. In the etching process using the photoresist pattern 330, the data metal layer, the barrier metal pattern 180, and the ohmic contact layer 116 formed on the partial exposure region S3, that is, the channel portion of the thin film transistor, are illustrated in FIG. 9D. The source electrode 108 and the drain electrode 110 are separated by being removed together. The photoresist pattern 330 remaining on the data pattern is removed by a stripping process.

Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed, as shown in FIG. 9E. As the passivation layer 118, an inorganic insulating material such as the gate insulating film 112 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

FIG. 10 is a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor array substrate illustrated in FIGS. 4 and 5.

In the liquid crystal display panel shown in FIG. 10, the liquid crystal display panel includes a color filter array substrate 302 and a thin film transistor array substrate 300 bonded by a material 308.

The color filter array substrate 302 includes an upper array 306 including a black matrix and a color filter formed on the upper substrate 304.

In this case, the upper substrate 304 is bonded to the pad region where the gate pad 150 and the data pad 160 are formed in the thin film transistor array substrate 300.

Thereafter, the passivation layer 118 of the pad region exposed by the upper substrate 304 is removed through the pad opening process, so that the transparent conductive layer 170 included in each of the gate pad 150 and the data pad 160 is gate contacted. Exposed through the hole 154 and the data contact hole 164.

In this case, the pad opening process sequentially scans each pad exposed by the upper substrate 304 using the plasma generated by the atmospheric pressure plasma generator, or collectively scans each pad unit for the gate pad 150 and the data. The transparent conductive film 170 of the pad 160 is exposed. Alternatively, a plurality of liquid crystal panels in which the upper substrate 304 and the thin film transistor array substrate 300 are bonded to each other are inserted into the chamber, and then the protective layer 118 of the pad region exposed by the upper array substrate 302 is removed using an atmospheric pressure plasma. Etching exposes the transparent conductive layer 170 of the gate pad 150 and the data pad 160. Alternatively, the entire liquid crystal cell to which the upper substrate 304 and the thin film transistor array substrate 300 are bonded is immersed in an etchant, or only a pad region including the gate pad 150 and the data pad 160 is immersed in the etchant to form a gate pad ( 150 and the transparent conductive film 170 of the data pad 160 are exposed. Alternatively, the transparent conductive film of the gate pad and the data pad is exposed by an etching process using an alignment layer (not shown) as a mask before bonding.

FIG. 11 is a plan view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view illustrating a thin film transistor array substrate taken along a line “XII-XII ′” in FIG. 11.

11 and 12, the gate pad 150 and the data pad 160 are formed in a multi-layered structure in comparison with the thin film transistor array substrates shown in FIGS. 4 and 5, and the source electrode 108 is formed. ), Except that the data pattern including the drain electrode 110, the data line 104, and the storage electrode 128 is formed of different dissimilar metals.

The gate pad 150 is connected to the gate pad lower electrode 152 connected to the gate line 102, the gate pad lower electrode 152 and the gate contact hole 154, and is formed of the same metal as the data pattern. The pad upper electrode 156 is provided.

The gate pad lower electrode 152 includes a transparent conductive film 170 and a gate metal film 172 formed on the transparent conductive film 170. The gate pad upper electrode 156 includes a first data metal film 182 and a second data metal film 184 formed on the first data metal film 182. The gate contact hole 154 penetrates through the gate insulating film 112 and the gate metal film 172 of the gate pad lower electrode 152 to expose the transparent conductive film 170 of the gate pad lower electrode 152. Accordingly, the gate pad upper electrode 156 is in plane contact with the transparent conductive layer 170 of the gate pad lower electrode 152 through the gate contact hole 154 and the gate metal layer 172 of the gate pad lower electrode 152 is in contact with each other. And side contact.

The data pad 150 is formed on the barrier metal pattern 180 and includes a data pad electrode 162 connected to the data line 104. The data pad electrode 162 includes a first data metal film 182 and a second data metal film 184 formed on the first data metal film 182.

The data pattern including the source electrode 108, the drain electrode 110, the data line 104, the storage electrode 128, the gate pad upper electrode 156, and the data pad electrode 162 includes a first data metal film ( 182 and a second data metal film 184 formed on the first data metal film 182. Here, the first data metal film 182 is formed of a metal including copper, and the second data metal film 184 is formed of a transparent conductive material such as ITO, TO, ITZO, IZO, or the like.

As described above, the thin film transistor array substrate according to the second embodiment of the present invention may include a gate metal layer including the gate line 102 and copper (Cu) and first data including the data line 104 and copper (Cu). By forming the metal film, it is possible to prevent signal delay due to the enlargement of the substrate.

In addition, the thin film transistor array substrate according to the second embodiment of the present invention is formed in a multilayer structure in which the gate pad 150 and the data pad 160 have a second data conductive film formed of a transparent conductive material having high strength and corrosion resistance as a top layer. do. Accordingly, even if the tape carrier package is repeatedly attached, the disconnection failure of the gate pad 150 and the data pad 160 is prevented, thereby facilitating a rework process. In addition, the gate pad 150 and the data pad 160 are formed to expose the transparent conductive film 170 that is resistant to corrosion, thereby preventing oxidation corrosion due to moisture, thereby improving reliability.

13A to 13C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

Referring to FIG. 13A, a pixel electrode 122 including a gate metal film on a lower substrate 101 in a first mask process; A gate pattern including a two-layer gate line 102, a gate electrode 106, and a gate pad lower electrode 152 is formed.

To this end, the transparent conductive film and the gate metal film are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Subsequently, the transparent conductive film and the gate metal layer are patterned by a photolithography process and an etching process using a first mask, thereby forming a gate including a gate line 102, a gate electrode 106, and a gate pad lower electrode 152 having a two-layer structure. Patterns; The pixel electrode 122 including the gate metal film 172 is formed.

Referring to FIG. 13B, the gate insulating layer 112 is formed on the lower substrate 101 on which the gate pattern and the pixel electrode 122 are formed by the second mask process; Semiconductor patterns 114 and 116 including an active layer 114 and an ohmic contact layer 116; The barrier metal pattern 180 having the same pattern as the semiconductor pattern is formed. A gate contact hole 156 is formed through the gate metal layer 172, the gate insulating layer 112, and the semiconductor patterns 114 and 116 of the gate pad lower electrode 152.

To this end, the gate insulating layer, the first and second semiconductor layers, and the barrier metal layer are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. Subsequently, the gate insulating film, the first and second semiconductor layers, and the barrier metal layer are patterned by a photolithography process and a dry etching process using a second mask, thereby forming an active layer 114 on the gate insulating film 112 and the gate insulating film 112. And a semiconductor pattern including an ohmic contact layer 116; The barrier metal pattern 180 having the same pattern as the semiconductor pattern is formed.

Thereafter, the gate metal film 172 included in the gate pad lower electrode 152 and the pixel electrode 122 is formed by a wet etching process using the gate insulating film 112, the semiconductor pattern, and the barrier metal pattern 180 as a mask. By patterning, the transparent conductive film 170 of the pixel electrode 122 is exposed, and a gate contact hole 154 exposing the transparent conductive film 170 of the gate pad lower electrode 152 is formed.

Referring to FIG. 13C, a data line 104, a source electrode 108, and a drain electrode 110 having a two-layer structure are formed on a lower substrate 101 on which a gate insulating pattern 112 and a semiconductor pattern are formed in a third mask process. The data pattern including the storage electrode 128, the gate pad upper electrode 156, and the data pad electrode 162 is formed.

To this end, the first and second data metal layers are formed on the lower substrate 101 by a deposition method such as sputtering. The gate pad upper electrode 156 and the data pad electrode 162 by patterning the first and second data metal layers 109 by a wet etching process using a stepped photoresist pattern formed by a photolithography process using a partial exposure mask as a mask. ), A data pattern including a storage electrode 128, a data line 104, a source electrode 108 and a drain electrode 110 connected to the data line 104 is formed. Here, the gate pad upper electrode 156 is connected to the gate pad lower electrode 152 through the gate contact hole 154. That is, the first data conductive layer 184 of the gate pad upper electrode 156 is in plane contact with the transparent conductive layer 170 of the gate pad lower electrode 152 and is in side contact with the gate conductive layer 172.

The active layer 114, the ohmic contact layer 116, and the barrier metal pattern 180 are formed along the data pattern by a dry etching process using the photoresist pattern as a mask. Subsequently, a relatively low height photoresist pattern is removed by an ashing process, and a relatively high height photoresist pattern is reduced in height. By using the photoresist pattern, the drain electrode 110 and the source electrode 108 are removed by removing the first and second data metal layers, the barrier metal pattern 180 and the ohmic contact layer 116 formed on the channel portion of the thin film transistor. Are separated. Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed.

FIG. 14 is a cross-sectional view illustrating a liquid crystal display panel including the thin film transistor array substrate illustrated in FIGS. 11 and 12.

In the liquid crystal display panel illustrated in FIG. 14, the liquid crystal display panel includes a color filter array substrate 302 and a thin film transistor array substrate 300 bonded by an actual material 308.

The color filter array substrate 302 includes an upper array 306 including a black matrix and a color filter formed on the upper substrate 304. The upper substrate 304 is bonded to the pad region where the gate pad 150 and the data pad 160 are formed in the thin film transistor array substrate 300.

Thereafter, the passivation layer 118 of the pad region exposed by the upper substrate 304 is removed through the pad opening process to expose the second data metal layer 184 included in the gate pad upper electrode 156. The second data metal film 184 included in the pad electrode 162 is exposed.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention form the pixel electrode and the gate pattern by the first mask process, the semiconductor pattern and the barrier metal pattern by the second mask process, and the third mask process. By forming a data pattern of at least one layer structure, a thin film transistor array substrate is completed. Thus, by forming the thin film transistor array substrate in a three mask process, the structure and manufacturing process can be simplified, manufacturing cost can be reduced, and manufacturing yield can be improved. In addition, the liquid crystal display panel and the method of manufacturing the same according to the present invention can prevent the signal delay due to the enlargement of the substrate by forming a signal line including a gate line and a data line made of a metal containing copper. In addition, the liquid crystal display panel and the method of manufacturing the same according to the present invention facilitate the rework process by forming the gate pad and the data pad in a multilayer structure.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view illustrating a thin film transistor array substrate of a conventional liquid crystal display panel.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate shown in FIG. 1 taken along the line "II-II '".

3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to a first embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along the line "V-V '".

6A and 6B are plan views and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

7A and 7B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

8A and 8B are plan views and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

9A to 9E are cross-sectional views for describing in detail the third mask process illustrated in FIGS. 8A and 8B.

10 is a cross-sectional view of a liquid crystal display panel including a thin film transistor array substrate according to a first embodiment of the present invention.

11 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display panel according to a second exemplary embodiment of the present invention.

FIG. 12 is a cross-sectional view of the thin film transistor array substrate of FIG. 11 taken along the line " XII-XII '.

13A to 13C are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 12.

14 is a cross-sectional view of a liquid crystal display panel including a thin film transistor array substrate of a liquid crystal display panel according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2,102: gate line 4,104: data line

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 12112 gate insulating film

14,114 active layer 16,116 ohmic contact layer

18,118: Shield 20,42,56,66,162,164: Contact hole

22,122: pixel electrode 28,128: storage electrode

40,140: Storage capacitor 50,150: Gate pad

52: gate pad lower electrode 54: gate pad upper electrode

60, 160: data pad 62: data pad lower electrode

64: data pad upper electrode 170: transparent conductive film

172: gate metal film

Claims (13)

A color filter array substrate; A gate line and a data line opposed to and bonded to the color filter array substrate, the thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, and the gate A gate pad connected to a line, the gate pad including a transparent conductive film, a data pad connected to the data line, and a transparent pad formed in an area overlapping the color filter array substrate. A thin film transistor array substrate having a protective film exposing the conductive film, And at least one of the gate line and the data line has at least one layer structure including a copper metal layer. The method of claim 1, A gate insulating pattern formed to insulate the gate pattern including the gate line and the gate electrode and the source / drain pattern including the data line, the source electrode, and the drain electrode; A semiconductor pattern formed on the gate insulating pattern and partially overlapping the gate pattern; And a barrier metal pattern formed between the semiconductor pattern and the source / drain pattern and formed in the same pattern as the semiconductor pattern. The method of claim 2, The semiconductor pattern is An active layer forming a channel between the source and drain electrodes and overlapping the gate pattern; And an ohmic contact layer formed on the active layer and formed in the same pattern as the barrier metal pattern. The method of claim 2, The barrier metal pattern is formed of at least one of molybdenum (Mo), chromium (Cr), tungsten (W) and titanium (Ti). The method of claim 2, The gate pattern is And the copper metal layer formed on the transparent conductive film and the transparent conductive film. The method of claim 2, The source / drain pattern is And the transparent conductive film formed on the copper metal layer and the copper metal layer. The method of claim 1, At least one of the gate pad and the data pad And a gate pad electrode including the transparent conductive film and the copper metal layer formed to expose the transparent conductive film on the transparent conductive film. The method of claim 1, The gate pad A first gate pad electrode formed on the transparent conductive film and a first copper metal layer formed on the transparent conductive film and exposing the transparent conductive film; And a second gate pad electrode including a first metal layer in contact with the first copper metal layer and including a second copper metal layer, and a second metal layer on the first metal layer, the second metal layer being formed of the same metal as the transparent conductive film. A liquid crystal display panel characterized by. The method of claim 2, The data pad is And a second data pad electrode including a first metal layer including the copper metal layer in contact with the barrier metal pattern, and a second metal layer formed of the same metal as the transparent conductive film on the first metal layer. LCD panel. Providing a color filter array substrate; A gate line and a data line facing the color filter array substrate and intersecting a gate insulating pattern on a lower substrate, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, A gate pad connected to the gate line to expose the transparent conductive film, a data pad connected to the data line to expose the transparent conductive film, and a transparent conductive layer formed in an area overlapping the color filter array substrate; Providing a thin film transistor array substrate having a protective film exposing the film; Bonding the thin film transistor array substrate and the color filter array substrate to each other using a material to expose a pad region including the gate pad and the data pad; Exposing the transparent conductive film in a pad region by removing the protective film using the color filter array substrate as a mask; And at least one of the gate line and the data line is formed in at least one layer structure including a copper metal layer. The method of claim 10, Preparing the thin film transistor array substrate Forming gate patterns and pixel electrodes including a gate line including a transparent conductive layer and a copper metal layer, a gate electrode, a first gate pad electrode, and a second data pad electrode on the substrate; A gate insulating pattern, a semiconductor pattern having the same pattern as the gate insulating pattern, and a barrier metal pattern are formed on the substrate on which the gate patterns and the pixel electrode are formed, and the transparent conductive film included in the data pad electrode, the gate pad electrode, and the pixel electrode is formed. Exposing; Forming a data pattern including at least one layer of a metal including a copper metal layer on the substrate on which the barrier metal pattern, the semiconductor pattern, and the gate insulating pattern are formed, the data pattern including a data line, a source electrode, and a drain electrode connected to the data pad electrode; Steps; And forming a passivation layer on the substrate on which the data pattern is formed. The method of claim 11, The barrier metal pattern may be formed of at least one of molybdenum (Mo), chromium (Cr), tungsten (W), and titanium (Ti). The method of claim 11, Forming a data pattern including at least one layer of a metal including a copper metal layer on the substrate on which the barrier metal pattern, the semiconductor pattern, and the gate insulating pattern are formed, the data pattern including a data line, a source electrode and a drain electrode connected to the data pad electrode Step is And forming the data line, the source electrode, the drain electrode, the second gate pad electrode, and the second data pad electrode from a metal including the copper metal layer and the transparent conductive film formed on the copper metal layer. Method of manufacturing a liquid crystal display panel.