KR101432571B1 - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The liquid crystal display device and the method of manufacturing the same according to the present invention can form active films, source / drain electrodes, and pad contact holes using a multiple exposure mask, and form a protective film on the pixel portion using a metal mask that does not require a photolithography process Thereby reducing the number of masks and simplifying the fabrication process and reducing manufacturing costs, comprising the steps of: providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode and a gate line in a pixel portion of the first substrate through a first mask process and forming a gate pad line in a gate pad portion of the first substrate; Forming a gate insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a conductive film on a first substrate on which the gate electrode, the gate line, and the gate pad line are formed; Forming a first photoresist pattern to a fifth photoresist pattern on a first substrate on which the conductive layer is formed through a second mask process using a multiple exposure mask; Selectively removing a portion of the gate insulating film, the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the first to fifth photoresist pattern to the gate pad portion of the first substrate, Forming a first pad hole such that a portion thereof is removed to have a first thickness; Forming a sixth photoresist pattern to a ninth photoresist pattern by removing the fifth photoresist pattern through a first ashing process and removing a portion of the thicknesses of the first photoresist pattern to the fifth photoresist pattern; Selectively removing the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the sixth photoresist pattern to the ninth photoresist pattern as masks to form an active pattern of the amorphous silicon thin film in the pixel portion of the first substrate, Forming a data line and a first data pad line made of the conductive film on the pixel portion and the data pad portion of the first substrate, respectively; The gate insulating layer is selectively removed by using the sixth to ninth photoresist pattern as a mask so that a part of the gate insulating layer of the first thickness is further removed from the gate pad portion of the first substrate, Forming two pad holes; Forming a tenth photosensitive film pattern to a twelfth photosensitive film pattern by removing the ninth photosensitive film pattern and removing a part of the thickness of the sixth photosensitive film pattern to the eighth photosensitive film pattern through a second ashing process; The conductive film is selectively removed by using the tenth photosensitive film pattern to the twelfth photosensitive film pattern as masks to form a source electrode and a drain electrode of the conductive film in the pixel portion of the first substrate, Forming a first contact hole exposing a portion of the gate pad line in the gate pad portion; Forming a pixel electrode directly connected to the drain electrode in the pixel portion of the first substrate through a third mask process and electrically connecting the gate pad portion of the first substrate with the gate pad line via the first contact hole Forming a gate pad electrode to be connected; Forming a protective layer on a pixel portion of the first substrate in a state where the data pad portion and the gate pad portion of the first substrate on which the pixel electrode and the gate pad electrode are formed are masked with a metal mask; And bonding the first substrate and the second substrate on which the protective film is formed.

Liquid crystal display, multiple exposure mask, metal mask, number of masks

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a liquid crystal display device and a method of manufacturing the same that can simplify a manufacturing process by reducing the number of masks, .

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using a thin film transistor (TFT) as a switching element.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constructed as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal display panel, (Not shown) formed on the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (that is, a photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required ought.

2A to 2E are cross-sectional views sequentially showing the steps of manufacturing an array substrate in the liquid crystal display device shown in Fig.

As shown in Fig. 2A, a gate electrode 21 made of an opaque conductive film is formed on the array substrate 10 by using a photolithography process (first mask process).

Next, as shown in FIG. 2B, a first insulating film 15a, an amorphous silicon thin film and an n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed The amorphous silicon thin film and the n + amorphous silicon thin film are selectively patterned using a photolithography process (second mask process) to form an active pattern 24 made of the amorphous silicon thin film on the gate electrode 21.

At this time, an n + amorphous silicon thin film pattern 25 patterned in the same manner as the active pattern 24 is formed on the active pattern 24.

Then, as shown in FIG. 2C, an opaque conductive film is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (a third mask process) The source electrode 22 and the drain electrode 23 are formed. At this time, the n + amorphous silicon thin film pattern formed on the active pattern 24 is removed by the third mask process, and the ohmic-and-amorphous silicon thin film pattern is formed between the active pattern 24 and the source / drain electrodes 22, Thereby forming an ohmic contact layer 25 '.

2d, a second insulating layer 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process A part of the second insulating film 15b is removed through the contact hole 40 to expose a part of the drain electrode 23.

Finally, as shown in FIG. 2E, a transparent conductive film is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (fifth mask process) A pixel electrode 18 electrically connected to the pixel electrode 23 is formed.

As described above, the fabrication of the array substrate including the thin film transistor requires at least five photolithography processes for patterning the gate electrode, the active pattern, the source / drain electrode, the contact hole, and the pixel electrode.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as a photoresist application, an exposure, and a development process. There is a disadvantage that it falls.

In particular, the mask designed to form the pattern is very expensive, so that the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

An object of the present invention is to provide a method of manufacturing a liquid crystal display device in which an array substrate of a liquid crystal display device is manufactured by three mask processes.

It is another object of the present invention to provide a liquid crystal display device and a method of manufacturing the liquid crystal display device in which a failure due to the lift-off process is prevented by not applying a lift-off process in the three mask processes.

It is still another object of the present invention to provide a liquid crystal display device and a method of manufacturing the same that can prevent a short-circuit failure of upper and lower substrates which are problematic in realizing a low cell gap.

Other objects and features of the present invention will be described in the following description of the invention and claims.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; A gate electrode and a gate line formed in a pixel portion of the first substrate and made of a first conductive film; A gate pad line formed in the gate pad portion of the first substrate and made of the first conductive film; A gate insulating film formed on the first substrate; An active pattern formed on the gate electrode; A source / drain electrode electrically connected to a source / drain region of the active pattern and made of a second conductive film; A data line crossing the gate line and defining a pixel region, the data line comprising the second conductive film; A first contact hole for removing a part of the gate insulating film to expose a part of the gate pad line; A pixel electrode directly connected to the drain electrode in a pixel portion of the first substrate, the pixel electrode being a third conductive film; A gate pad electrode formed on the gate pad portion of the first substrate and electrically connected to the gate pad line through the first contact hole; A protective film formed on a pixel portion of the first substrate; And a second substrate bonded to be opposite to the first substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display, including: providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode and a gate line in a pixel portion of the first substrate through a first mask process and forming a gate pad line in a gate pad portion of the first substrate; Forming a gate insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a conductive film on a first substrate on which the gate electrode, the gate line, and the gate pad line are formed; Forming a first photoresist pattern to a fifth photoresist pattern on a first substrate on which the conductive layer is formed through a second mask process using a multiple exposure mask; Selectively removing a portion of the gate insulating film, the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the first to fifth photoresist pattern to the gate pad portion of the first substrate, Forming a first pad hole such that a portion thereof is removed to have a first thickness; Forming a sixth photoresist pattern to a ninth photoresist pattern by removing the fifth photoresist pattern through a first ashing process and removing a portion of the thicknesses of the first photoresist pattern to the fifth photoresist pattern; Selectively removing the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the sixth photoresist pattern to the ninth photoresist pattern as masks to form an active pattern of the amorphous silicon thin film in the pixel portion of the first substrate, Forming a data line and a first data pad line made of the conductive film on the pixel portion and the data pad portion of the first substrate, respectively; The gate insulating layer is selectively removed by using the sixth to ninth photoresist pattern as a mask so that a part of the gate insulating layer of the first thickness is further removed from the gate pad portion of the first substrate, Forming two pad holes; Forming a tenth photosensitive film pattern to a twelfth photosensitive film pattern by removing the ninth photosensitive film pattern and removing a part of the thickness of the sixth photosensitive film pattern to the eighth photosensitive film pattern through a second ashing process; The conductive film is selectively removed by using the tenth photosensitive film pattern to the twelfth photosensitive film pattern as masks to form a source electrode and a drain electrode of the conductive film in the pixel portion of the first substrate, Forming a first contact hole exposing a portion of the gate pad line in the gate pad portion; Forming a pixel electrode directly connected to the drain electrode in the pixel portion of the first substrate through a third mask process and electrically connecting the gate pad portion of the first substrate with the gate pad line via the first contact hole Forming a gate pad electrode to be connected; Forming a protective layer on a pixel portion of the first substrate in a state where the data pad portion and the gate pad portion of the first substrate on which the pixel electrode and the gate pad electrode are formed are masked with a metal mask; And bonding the first substrate and the second substrate on which the protective film is formed.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention reduce the number of masks used in the manufacture of thin film transistors, thereby reducing the manufacturing process and cost.

Further, the liquid crystal display device and the manufacturing method thereof according to the present invention provide an effect of improving the yield by preventing defects caused by the lift-off process.

In addition, the liquid crystal display device and the manufacturing method thereof according to the present invention can prevent a short-circuit failure of the upper and lower substrates, which is a problem in realizing the low cell gap for improving the response speed, and improve the yield.

As described above, the photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a photolithography process, a photolithography process, Has the disadvantage of lowering the production yield.

Thus, a technology has been developed in which an array substrate can be fabricated by a total of four mask processes by forming an active pattern and source / drain electrodes in a single mask process using a diffraction mask.

Also, a transparent conductive metal material such as indium tin oxide (ITO) is deposited on the photosensitive material patterned in a predetermined shape to a predetermined thickness, and then deposited in a solution such as a stripper to deposit the metal material There is an effort to reduce the number of masks used in the fabrication of the array substrate by using a lift off process for removing the photosensitive material together with the metal material.

At this time, the ITO thin film is deposited without removing the photoresist film used in the previous mask process, compared with the general method of depositing the ITO thin film and patterning the ITO thin film in a predetermined pattern by using the photolithography process, And the ITO thin film are removed at once, which has an advantage that no additional mask process is required in forming the ITO thin film pattern.

However, in the lift-off process, an optimal condition for properly stripping the ITO thin film together with the photoresist and a predetermined time for stripping the photoresist layer is required. When the process conditions are not satisfied, The ITO thin film pattern may be short-circuited.

Accordingly, in the present invention, the active pattern, the source / drain electrodes and the pad portion contact holes are formed using a multiple exposure mask, and a protective film is formed on the pixel portion using a metal mask which does not require a photolithography process, FIG. 2 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a plan view schematically showing a part of an array substrate of a liquid crystal display according to an embodiment of the present invention, and shows one pixel including a gate pad portion, a data pad portion and a thin film transistor of a pixel portion for convenience of explanation .

In an actual liquid crystal display device, N number of gate lines and M number of data lines intersect to form MxN pixels, but one pixel is shown in the figure for simplicity.

As shown in the figure, a gate line 116 and a data line 117 are vertically and horizontally arranged on the array substrate 110 to define a pixel region in the array substrate 110 of the embodiment of the present invention. A thin film transistor, which is a switching element, is formed in the intersection region of the gate line 116 and the data line 117. A common electrode of the color filter substrate (not shown) is connected to the thin film transistor And a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

Although the exemplary embodiments of the present invention describe an array substrate of a twisted nematic (TN) type liquid crystal display device that drives nematic liquid crystal molecules in a direction perpendicular to a substrate, But the present invention is not limited thereto. The present invention is also applicable to an in-plane switching (IPS) liquid crystal display device in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve a viewing angle to 170 degrees or more.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected directly to the pixel electrode 118 have. The thin film transistor includes an active pattern (not shown) which forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121 .

A part of the source electrode 122 extends in one direction to form a part of the data line 117. A part of the drain electrode 123 extends toward the pixel region and is directly connected to the pixel electrode 118 without a contact hole. Respectively.

At this time, a portion of the gate line 116 located at the front end overlaps with a part of the pixel electrode 118 above the gate insulating layer (not shown) to form a storage capacitor Cst. The storage capacitor Cst serves to keep the voltage applied to the liquid crystal capacitor constant until the next signal is received. That is, the pixel electrode 118 of the array substrate 110 forms a liquid crystal capacitor together with the common electrode of the color filter substrate. Generally, the voltage applied to the liquid crystal capacitor is not maintained until the next signal is received, Disappear. Therefore, in order to maintain the applied voltage, the storage capacitor Cst must be connected to the liquid crystal capacitor.

The storage capacitor Cst has effects such as stabilization of gray scale display and reduction of flicker and afterimage in addition to signal retention.

A gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in an edge region of the array substrate 110, And transmits a scan signal and a data signal applied from a driving circuit unit (not shown) to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend to the driving circuit portion and are connected to the corresponding gate pad line 116p and the first data pad line 117p, respectively, The first data pad line 117p is connected to the gate pad line 116p and the first data pad line 117p through a gate pad electrode 126p and a data pad electrode 127p, The scanning signal and the data signal are received.

The gate pad electrode 126p is electrically connected to the gate pad line 116p through the first contact hole 140a and the data pad electrode 127p is electrically connected to the gate pad line 116p through the second contact hole 140b. 2 data pad line 117p 'and is directly connected to the first data pad line 117p.

Although not shown in the drawing, a passivation layer is formed on the pixel portion of the array substrate 110 according to an embodiment of the present invention having a small thickness to realize a good cell gap. At this time, in the embodiment of the present invention, in order to prevent the short-circuit failure of the upper and lower substrates due to the foreign material in the process of implementing the low cell gap for improving the response speed of the liquid crystal display device, (118).

Here, a liquid crystal display device according to an embodiment of the present invention includes a plurality of exposure masks, that is, a blocking region made up of a dark region, a first transmissive region transmitting all light, a second transmissive region having a half- The active pattern, the source / drain electrode, and the pad portion contact hole are formed by a single mask process using a multi-tone mask in the third transmission region, and a metal mask, which does not require a photolithography process, By forming the above-described protective film, an array substrate can be manufactured by a total of three mask processes, which will be described in detail through the following manufacturing method of a liquid crystal display device.

4A to 4C are cross-sectional views sequentially showing a manufacturing process according to lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc of the array substrate shown in FIG. 3. In the left side, And an array substrate of a data line portion and a gate pad portion is sequentially formed on the right side.

5A to 5C are cross-sectional views sequentially showing a manufacturing process according to lines IIId-IIId 'of the array substrate shown in FIG. 3, and show a process of manufacturing an array substrate of a data pad portion.

4A and 5A, a gate electrode 121 and a gate line 116 are formed in a pixel portion of an array substrate 110 made of a transparent insulating material such as glass and a gate pad line 116p.

A second data pad line 117p 'made of the same conductive material as the gate pad line 116p is formed on the data pad of the array substrate 110. [

In this case, the first conductive layer is deposited on the entire surface of the array substrate 110, and then the gate electrode 121, the gate line 116, the gate pad line 116p, and the second data pad line 117p ' (A first mask process).

Here, the first conductive layer may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum The same low resistance opaque conductive material can be used. The first conductive layer may have a multi-layer structure in which two or more low resistance conductive materials are stacked.

4B and 5B, the array substrate 110 having the gate electrode 121, the gate line 116, the gate pad line 116p, and the second data pad line 117p ' The gate insulating film 115a, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are deposited on the entire surface, and then selectively removed through a photolithography process (second mask process) The active pattern 124 is formed of the amorphous silicon thin film and the source and drain electrodes 122 and 123 are formed of the second conductive film and electrically connected to the source and drain regions of the active pattern 124 do.

At this time, a data line 117 made of the second conductive film is formed in the data line portion of the array substrate 110 through the second mask process, and a data line 117 made of the second conductive film Thereby forming a data pad line 117p.

A first contact hole 140a exposing a part of the gate pad line 116p is formed by selectively removing a part of the gate insulating film 115a through the second mask process, And a second contact hole 140b exposing a part of the pad line 117p 'is formed.

At this time, an ohmic contact layer 125n formed of the n + amorphous silicon thin film and patterned in the same shape as the source / drain electrodes 122 and 123 is formed on the active pattern 124.

The amorphous silicon thin film and the n + amorphous silicon thin film are formed under the data line 117 and the first data pad line 117p and have the same shape as the data line 117 and the first data pad line 117p, The first amorphous silicon thin film pattern 120 ', the second n + amorphous silicon thin film pattern 125 ", the second amorphous silicon thin film pattern 120" and the third n + amorphous silicon thin film pattern 125' .

Here, the active pattern 124, the source / drain electrodes 122 and 123, and the pad contact holes 140a and 140b according to the embodiment of the present invention may be subjected to a single mask process The second mask process will be described in detail with reference to the drawings.

6A to 6H are cross-sectional views illustrating a second mask process according to an embodiment of the present invention shown in FIG. 4B.

A gate insulating layer 115a is formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the gate pad line 116p and the second data pad line 117p are formed, ), An amorphous silicon thin film 120, an n + amorphous silicon thin film 125, and a second conductive film 130 are formed.

The second conductive layer 130 may be a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form a source electrode, a drain electrode, a data line, ≪ / RTI >

6B, a photoresist layer 170 made of a photosensitive material such as a photoresist is formed on the entire surface of the array substrate 110, and then, a plurality of exposure masks 180 according to an embodiment of the present invention are formed And selectively irradiates the photoresist layer 170 with light.

At this time, the multiple exposure mask 180 includes a first transmissive region I for transmitting all the irradiated light and a second transmissive region II consisting of a half-tone portion for transmitting only a part of light and blocking a part thereof, A third transmissive region III made of a slit portion and a blocking region IV blocking all the irradiated light are provided and only the light transmitted through the multiple exposure mask 180 is irradiated to the photoresist layer 170 .

6C, after the photoresist layer 170 exposed through the multiple exposure mask 180 is developed, the blocking region IV, the second transmissive region II, and the third transmissive region 170, A first photoresist pattern 170a to a fifth photoresist pattern 170e having a predetermined thickness are left in a region where light is entirely blocked or partially blocked through the third transparent region III, The photoresist layer is completely removed and the surface of the second conductive layer 130 is exposed.

The first photoresist pattern 170a to the third photoresist pattern 170c formed in the blocking region IV may include a fourth photoresist pattern 170a formed through the second transmissive region II and the third transmissive region III, 170d and the fifth photosensitive film pattern 170e. The fifth photoresist pattern 170e formed through the third transmissive area III is formed thicker than the fourth photoresist pattern 170d formed through the second transmissive area II, The photoresist film is completely removed in the region where light is entirely transmitted through the region I because the photoresist of the positive type is used and the present invention is not limited thereto and a negative type photoresist may be used .

6D, using the first photoresist pattern 170a to the fifth photoresist pattern 170e formed as described above as a mask, a part of the gate insulating film 115a formed under the photoresist pattern 170a and the amorphous silicon thin film A portion of the gate insulating layer 115a is removed from the gate pad portion of the array substrate 110 and the first pad hole H is formed so as to have a first thickness by selectively removing the n + amorphous silicon thin film and the second conductive film, .

6E, a portion of the first photoresist pattern 170a to the fifth photoresist pattern 170e is removed, and then a portion of the first photoresist pattern 170a is removed. The fifth photoresist pattern is completely removed.

At this time, the first to fourth photoresist patterns may be formed by removing the sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' corresponding to the thickness of the fifth photoresist pattern, The source / drain electrode region and the data line region corresponding to the third transmission region III and the channel region between the source region and the drain region.

6F, using the remaining sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' as a mask, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second The active pattern 124 of the amorphous silicon thin film is formed on the pixel portion of the array substrate 110 and the data line portion of the array substrate 110 is formed of the second conductive film The data line 117 is formed.

At this time, although not shown in the figure, a first data pad line 117p made of the second conductive film is formed on the data pad portion of the array substrate 110 (see FIG. 4B).

In addition, in the process of removing the amorphous silicon film and the n + amorphous silicon film, a part of the gate insulating film 115a having the first thickness is further removed from the gate pad portion of the array substrate 110, Two pad holes H 'are formed.

The first n + amorphous silicon thin film pattern 125 'formed of the n + amorphous silicon thin film and the second conductive film and patterned in the same manner as the active pattern 124 is formed on the active pattern 124, The conductive film pattern 130 'is formed.

The amorphous silicon thin film and the n + amorphous silicon thin film are formed under the data line 117 and the first data pad line 117p and have the same shape as the data line 117 and the first data pad line 117p, The first amorphous silicon thin film pattern 120 ', the second n + amorphous silicon thin film pattern 125', the second amorphous silicon thin film pattern 120 'and the third n + amorphous silicon thin film pattern 125' .

6G, when the ashing process for removing a portion of the sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' is performed, 9 photoresist pattern is completely removed.

At this time, the sixth through eighth photosensitive film patterns correspond to the blocking region III with the tenth photosensitive film pattern 170a " to the twelfth photosensitive film pattern 170c " removed by the thickness of the ninth photosensitive film pattern The source electrode region and the drain electrode region, and the data line 117, respectively.

6H, using the remaining tenth photoresist pattern 170a " to the twelfth photoresist pattern 170c "as a mask, a part of the second conductive film pattern is selectively removed, The source electrode 122 and the drain electrode 123, which are the second conductive film, are formed in the pixel portion of the substrate 110. [

The gate insulating layer 115a of the second thickness is selectively removed in the gate pad portion and the data pad portion of the array substrate 110 so that the gate pad line 116p and the second data pad line 117p ' A first contact hole 140a and a second contact hole 140b are formed to expose a part thereof.

At this time, on the active pattern 124, an ohmic contact layer (not shown) is formed of the n + amorphous silicon thin film and ohmic-contacted between the source / drain region of the active pattern 124 and the source / drain electrodes 122, (125n) is formed.

4C and 5C, a third conductive film is formed on the entire surface of the array substrate 110 on which the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 are formed. .

Here, the third conductive layer may have a transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a pixel electrode, a gate pad electrode, and a data pad electrode. Contains excellent transparent conductive materials.

Then, the third conductive film is selectively removed through a photolithography process (a third mask process), thereby forming the third conductive film in the pixel portion of the array substrate 110 and directly connecting to the drain electrode 123 The pixel electrode 118 is formed.

In addition, the gate pad portion and the data pad portion of the array substrate 110 through the third mask process are formed of the third conductive film, and are electrically connected to the gate pad line 116p through the first contact hole and the second contact hole. A gate pad electrode 126p and a data pad electrode 127p electrically connected to the second data pad line 117p 'are formed. At this time, a part of the data pad electrode 127p extends to the pixel portion and is directly connected to the first data pad line 117p.

In the embodiment of the present invention, a protective film is deposited only on the pixel portion of the array substrate 110 by using a metal mask. In this case, a protective film made of a predetermined insulating material is formed on the pixel portion of the array substrate 110 An additional photolithography process is not required and will be described in detail with reference to the following drawings.

7A and 7B are cross-sectional views sequentially illustrating a process of forming a protective film on a pixel portion of an array substrate using a metal mask according to an embodiment of the present invention.

7A, the gate pad portion and the data pad portion are covered with a metal layer covering the entire surface of the array substrate 110 on which the pixel electrode 118, the gate pad electrode 126p, and the data pad electrode 127p are formed. The mask M is placed.

In this case, the array substrate 110 may be loaded in a predetermined deposition apparatus for depositing a thin film. The metal mask M may be installed in the deposition apparatus, And is positioned to cover the entire gate pad portion 151 and the data pad portion 152 of the loaded array substrate 110.

7B, a predetermined insulating material is deposited on the entire surface of the array substrate 110 while the gate pad portion and the data pad portion of the array substrate 110 are covered with a metal mask M And a protective film 115b is formed on the pixel portion of the array substrate 110. [

At this time, in the embodiment of the present invention, since the protective layer 115b is formed on the pixel electrode 118, it is possible to prevent the short-circuit failure of the upper and lower substrates, which is a problem in realizing the low cell gap for improving the response speed.

In addition, in the embodiment of the present invention, an array substrate including a thin film transistor can be fabricated by three mask processes, thereby providing a manufacturing process and a cost reduction effect.

In addition, the liquid crystal display device and the manufacturing method thereof according to the present invention do not apply the lift-off process in the above-described three mask processes, thereby preventing defects caused by the lift-off process, thereby improving the yield .

The array substrate of the above-described embodiment of the present invention configured as described above is adhered to and opposed to the color filter substrate by a sealant formed on the outer periphery of the image display area. At this time, light is emitted from the color filter substrate to the thin film transistor, A black matrix for preventing leakage and a color filter for realizing red, green and blue colors are formed.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

Although the twisted nematic liquid crystal display device has been described as an example of the present invention as described above, the present invention is not limited to the twisted nematic liquid crystal display device, (Vertical Alignment) type liquid crystal display device.

In addition, although the amorphous silicon thin film transistor using the amorphous silicon thin film as the active pattern has been described as an example of the present invention, the present invention is not limited thereto, and the present invention can be applied to the active pattern using the polycrystalline silicon thin film And is also applied to a polycrystalline silicon thin film transistor.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are sectional views sequentially showing a manufacturing process of an array substrate in the liquid crystal display device shown in Fig.

3 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to an embodiment of the present invention.

4A to 4C are cross-sectional views sequentially showing a manufacturing process according to lines IIIa-IIIa ', IIIb-IIIb and IIIc-IIIc of the array substrate shown in FIG. 3;

FIGS. 5A to 5C are cross-sectional views sequentially showing manufacturing steps according to lines IIId-IIId 'of the array substrate shown in FIG. 3;

6A to 6H are cross-sectional views illustrating a second mask process according to an embodiment of the present invention shown in FIG. 4B.

7A and 7B are sectional views sequentially illustrating a process of forming a protective film on a pixel portion of an array substrate using a metal mask according to an embodiment of the present invention.

FIG. 8 is a plan view schematically showing a metal mask according to an embodiment of the present invention used in FIGS. 7A and 7B. FIG.

DESCRIPTION OF REFERENCE NUMERALS

110: array substrate 116: gate line

116p: gate pad line 117: data line

117p: first data pad line 117p ': second data pad line

118: pixel electrode 121: gate electrode

122: source electrode 123: drain electrode

126p: gate pad electrode 127p: data pad electrode

M: Metal mask

Claims (12)

Providing a first substrate, the first substrate being divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode and a gate line in a pixel portion of the first substrate through a first mask process and forming a gate pad line in a gate pad portion of the first substrate; Forming a gate insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a conductive film on a first substrate on which the gate electrode, the gate line, and the gate pad line are formed; Forming a first photoresist pattern to a fifth photoresist pattern on a first substrate on which the conductive layer is formed through a second mask process using a multiple exposure mask; Selectively removing a portion of the gate insulating film, the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the first to fifth photoresist patterns to form a gate pad portion of the first substrate, Forming a first pad hole such that a portion thereof is removed to have a first thickness; Forming a sixth photoresist pattern to a ninth photoresist pattern by removing the fifth photoresist pattern through a first ashing process and removing a portion of the thicknesses of the first photoresist pattern to the fifth photoresist pattern; Selectively removing the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the sixth photoresist pattern to the ninth photoresist pattern as masks to form an active pattern of the amorphous silicon thin film in the pixel portion of the first substrate, Forming a data line and a first data pad line made of the conductive film on the pixel portion and the data pad portion of the first substrate, respectively; The gate insulating layer is selectively removed by using the sixth to ninth photoresist pattern as a mask so that a part of the gate insulating layer of the first thickness is further removed from the gate pad portion of the first substrate, Forming two pad holes; Forming a tenth photosensitive film pattern to a twelfth photosensitive film pattern by removing the ninth photosensitive film pattern and removing a part of the thickness of the sixth photosensitive film pattern to the eighth photosensitive film pattern through a second ashing process; The conductive film is selectively removed by using the tenth photosensitive film pattern to the twelfth photosensitive film pattern as masks to form a source electrode and a drain electrode of the conductive film in the pixel portion of the first substrate, Forming a first contact hole exposing a portion of the gate pad line in the gate pad portion; Forming a pixel electrode directly connected to the drain electrode in the pixel portion of the first substrate through a third mask process and electrically connecting the gate pad portion of the first substrate with the gate pad line via the first contact hole Forming a gate pad electrode to be connected; Forming a protective layer on a pixel portion of the first substrate in a state where the data pad portion and the gate pad portion of the first substrate on which the pixel electrode and the gate pad electrode are formed are masked with a metal mask; And And bonding the first substrate and the second substrate on which the protective film is formed. The method of claim 1, further comprising forming a second data pad line in a data pad portion of the first substrate using the first mask process. The method of claim 2, further comprising forming a second contact hole exposing a portion of the second data pad line in a data pad portion of the first substrate using the second mask process Of the liquid crystal display device. 4. The method of claim 3, further comprising forming a data pad electrode electrically connected to the second data pad line through the second contact hole in the data pad portion of the first substrate using the third mask process And forming a second electrode on the second electrode. 5. The method of claim 4, wherein the data pad electrode extends partially to the pixel portion and is electrically connected to the first data pad line. delete The method of claim 1, wherein the first to third photosensitive film patterns are thicker than the fourth photosensitive film pattern and the fifth photosensitive film pattern, and the fifth photosensitive film pattern is thicker than the fourth photosensitive film pattern Of the liquid crystal display device. The method of claim 1, further comprising selectively removing the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the sixth photoresist pattern to the ninth photoresist pattern as masks, Wherein the first n + amorphous silicon thin film pattern and the conductive film pattern are patterned in the same manner as the active pattern. The method of claim 8, further comprising: selectively removing the amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film using the sixth photoresist pattern to the ninth photoresist pattern as masks, A first n + amorphous silicon thin film pattern, a second amorphous silicon thin film pattern, and a third n + amorphous silicon thin film pattern formed of a silicon thin film and an n + amorphous silicon thin film and patterned in the same pattern as the data line and the first data pad line, Thereby forming an amorphous silicon thin film pattern. delete delete delete

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