KR101680134B1 - In plane switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The In-Plane Switching (IPS) liquid crystal display device and the method of manufacturing the same of the present invention are characterized by depositing a protective film and a first transparent conductive film, forming a contact hole and a pixel electrode using diffraction exposure, And a common electrode is formed to be self-aligned with the pixel electrode through selective etching of a transparent conductive film.

The present invention provides the effect of reducing the number of masks and at the same time solving the afterimage problem.

A transparent conductive film, a diffraction exposure, a pixel electrode, a common electrode,

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a transverse electric field type liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field type liquid crystal display device and a manufacturing method thereof, and more particularly, to a transverse electric field type liquid crystal display device in which the number of masks is reduced to simplify a manufacturing process, .

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constituted as described above are adhered to each other so as to oppose each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal display panel, (Not shown) formed on the color filter substrate 5 or the array substrate 10.

In this case, there is a twisted nematic (TN) method in which a nematic liquid crystal molecule is driven in a direction perpendicular to a substrate by a driving method generally used in the liquid crystal display device. However, the twisted nematic liquid crystal display Has a disadvantage that the viewing angle is as narrow as 90 degrees. This is because of the refractive anisotropy of the liquid crystal molecules, and liquid crystal molecules aligned horizontally with the substrate are oriented in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

(In Plane Switching) type liquid crystal display device in which liquid crystal molecules are driven in a horizontal direction with respect to a substrate to have a viewing angle of 170 degrees or more. This will be described in detail with reference to the drawings.

FIG. 2 is a plan view showing a part of an array substrate of a general transverse electric field type liquid crystal display device, in which a fringe field formed between a pixel electrode and a common electrode passes through a slit to drive liquid crystal molecules located on a pixel region and a common electrode, For example, a fringe field switching (FFS) liquid crystal display device.

As shown in the drawing, a gate line 16 and a data line 17, which are vertically and horizontally arranged on the transparent array substrate 10 to define a pixel region, are formed on an array substrate 10 of a general fringe field type liquid crystal display device. And a thin film transistor, which is a switching element, is formed in an intersecting region of the gate line 16 and the data line 17. [

The thin film transistor includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. The thin film transistor is formed by a gate insulating film (not shown) for insulating between the gate electrode 21 and the source / drain electrodes 22 and 23 and a gate insulating film And an active layer (not shown) forming a conductive channel between the source electrode 22 and the drain electrode 23.

A common electrode 8 and a pixel electrode 18 are formed in the pixel region in the form of a box and the pixel electrode 18 is connected to the pixel electrode 18 includes a plurality of slits 18s.

At this time, the pixel electrode 18 is electrically connected to the drain electrode 23 through a contact hole 40 formed in a protective film (not shown), and the common electrode 8 is electrically connected to the gate line 16 And are connected to a common line 8l arranged in parallel.

Since a manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (i.e., photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required have.

3A to 3F are cross-sectional views sequentially illustrating a manufacturing process according to a line II-II 'of the array substrate shown in FIG.

A gate electrode 21 made of a conductive metal material, a common line 81 and a gate line (not shown) are formed on the array substrate 10 using a photolithography process (first mask process) .

3B, an insulating film, an amorphous silicon thin film and an n + amorphous silicon thin film are successively formed on the entire surface of the array substrate 10 on which the gate line 21, the common line 81 and the gate line are formed. / RTI >

Thereafter, the insulating film, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively patterned using a photolithography process (second mask process) to form the amorphous silicon thin film and the amorphous silicon thin film in the state where the gate insulating film 15a is interposed on the gate electrode 21. [ Thereby forming an active layer 24 made of a thin film.

At this time, an n + amorphous silicon thin film pattern 25 patterned in the same manner as the active layer 24 is formed on the active layer 24.

Thereafter, as shown in FIG. 3C, a transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (a third mask process) And a common electrode 8 electrically connected to the common line 81 is formed.

3D, a conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (a fourth mask process), thereby forming a source The electrode 22 and the drain electrode 23 are formed. In addition, the data line 17 defining the pixel region together with the gate line is formed through the fourth mask process.

At this time, the n + amorphous silicon thin film pattern formed on the active layer 24 is removed from the active layer 24 and the source / drain electrodes 22 and 23 by removing the predetermined region through the fourth mask process. Thereby forming an ohmic contact layer 25 'that makes an ohmic contact.

3E, a protective film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22, the drain electrode 23 and the data line 17 are formed, and then a photolithography process (A fifth mask process) to form a contact hole 40 for exposing a part of the drain electrode 23 by removing a part of the protective film 15b.

Finally, as shown in FIG. 3F, a transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (sixth mask process) to form the contact hole 40 A pixel electrode 18 electrically connected to the drain electrode 23 is formed. At this time, the pixel electrode 18 includes a plurality of slits 18s in the pixel electrode 18 to generate a fringe field together with the common electrode 8 thereunder.

As described above, the fabrication of the array substrate including the thin film transistor requires a total of six photolithography processes for patterning the gate electrode, the active layer, the common electrode, the source / drain electrode, the contact hole, and the pixel electrode.

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a photolithography process, a photolithography process, The yield is lowered.

In particular, the mask designed to form the pattern is very expensive, so that the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

The fringe field type liquid crystal display device has a wide viewing angle of about 160 degrees. However, as shown in FIG. 3F, a parasitic capacitance is generated between the pixel electrode 18 and the common electrode 8 It is disadvantageous in that the afterimage characteristic is poor for a high-transmittance panel of 10 " or higher.

An object of the present invention is to provide a transverse electric field type liquid crystal display device in which an array substrate is manufactured by four mask processes and a manufacturing method thereof.

Another object of the present invention is to provide a transverse electric field type liquid crystal display device and a method of manufacturing the same, which solve the afterimage problem of a 10 "

Other objects and features of the present invention will be described in the following description of the invention and the claims.

In order to achieve the above object, the transverse electric field type liquid crystal display device of the present invention is characterized in that a gate electrode composed of a first conductive film and a gate line, a common line, and a gate insulating film are interposed in the pixel portion of the first substrate, A source / drain electrode formed of a second conductive film on the active layer, and a data line crossing the gate line and defining a pixel region, A plurality of pixel electrodes formed of a transparent conductive film, a plurality of common electrodes formed of a second transparent conductive film on the first substrate surface between the pixel electrodes, a plurality of common electrodes formed on the first substrate through the first contact holes, A connection electrode pattern electrically connected to the first transparent conductive film and composed of the second transparent conductive film, And a connection electrode electrically connected to the connection electrode pattern and the pixel electrode, the connection electrode being composed of a third conductive layer of a material different from the first and second transparent conductive layers.

A method of manufacturing a transverse electric field type liquid crystal display device of the present invention includes forming a gate electrode and a gate line and a common line in a pixel portion of the first substrate through a first mask process, the gate electrode being a first conductive film.
In addition, an active layer may be formed on the gate electrode in a state where a gate insulating film is interposed through a second mask process, source / drain electrodes of a second conductive film may be formed on the active layer, To form a data line defining a data line.
In addition, a protective film and a first transparent conductive film are deposited on the active layer, the source and drain electrodes and the first substrate on which the data line is formed, and then selectively patterned through a third mask process, Forming a first contact hole exposing a part of the electrode, forming a plurality of pixel electrodes made of the first transparent conductive film in the pixel region with the protective film interposed therebetween, And forming a hole pattern for exposing the first substrate surface between the pixel electrodes by selectively patterning the first transparent conductive film.
In addition, a second transparent conductive film is deposited on the first substrate on which the pixel electrode is formed, and the second transparent conductive film is selectively patterned to form the second transparent conductive film on the pixel portion, And forming a common electrode in the hole pattern, which is made of the second transparent conductive film and is self-aligned with the pixel electrode, and a step of forming the common electrode and the pixel electrode, The second transparent conductive film pattern and the third conductive film are selectively patterned through a fourth mask process after depositing a third conductive film on the first substrate on which the second transparent conductive film pattern is formed, Forming a connection electrode pattern composed of a whole film, and forming the connection electrode pattern Through and forming a connection electrode for connecting the drain electrode and the pixel electrode electrically.

As described above, the transverse electric field type liquid crystal display device and the manufacturing method thereof according to the present invention can reduce the number of masks used in the manufacture of thin film transistors, thereby improving the yield and reducing the cost.

In addition, the transverse electric field type liquid crystal display device and the manufacturing method thereof according to the present invention improve the afterimage characteristic, thereby improving the image quality of the liquid crystal display panel.

Hereinafter, preferred embodiments of a transverse electric field type liquid crystal display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a plan view schematically showing a part of an array substrate of a transverse electric field type liquid crystal display according to an embodiment of the present invention. In order to simplify the description, FIG. 4 shows one pixel including a data pad, a gate pad, Respectively.

In an actual liquid crystal display device, there are MxN pixels intersecting N gate lines and M data lines, but one pixel is shown in the figure for simplicity of explanation.

As shown in the drawing, a gate line 116 and a data line 117 are formed on an array substrate 110 on the array substrate 110 in the vertical and horizontal directions to define pixel regions have. A thin film transistor, which is a switching element, is formed in an intersection region of the gate line 116 and the data line 117. A common electrode 108 (not shown) for generating a transverse electric field to drive a liquid crystal And a pixel electrode 118 are alternately formed.

The thin film transistor is electrically connected to the pixel electrode 118 through a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a connection electrode 195 And a drain electrode 123. The thin film transistor includes an active layer (not shown) which forms a conduction channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. Although the thin film transistor having the U-shaped shape of the source electrode 122 and the U-shaped channel is shown in the drawing, the present invention is not limited to this, It can be applied regardless of the channel type of the transistor.

A part of the source electrode 122 extends in one direction to form a part of the data line 117. A part of the drain electrode 123 extends toward the pixel region to form a first contact hole 140a and a second contact hole 140b. And is electrically connected to the pixel electrode 118 through the connection electrode 195.

As described above, in the pixel region, a plurality of common electrodes 108 and pixel electrodes 118 for generating a transverse electric field are alternately arranged.

At this time, a common line 108L is formed at one edge of the pixel region in a direction substantially parallel to the gate line 116, and the common line 108L has a protrusion protruding toward the pixel region And the common electrode 108 is connected to the protruding portion of the common line 108L.

A storage electrode 126 is formed on the common line 108L in a direction substantially parallel to the gate line 116. An upper portion of the storage line 126 is connected to the gate line 116 A pixel electrode line 1181 is formed in a substantially parallel direction. At this time, the storage electrode 126 overlaps with a part of the pixel electrode line 1181 thereabove to constitute a storage capacitor Cst, and the storage capacitor Cst applies a voltage applied to the liquid crystal capacitor And keeps it constant until the next signal arrives. These storage capacitors have effects such as stabilization of gray scale display and reduction of flicker and afterimage in addition to signal retention.

One of the plurality of common electrodes 108 is connected to the protruding portion of the common line 108L and one of the plurality of pixel electrodes 118 is connected to the pixel electrode line 1181, And is electrically connected to the drain electrode 123 through the electrode 195.

A data pad electrode 127p and a gate pad electrode 126p electrically connected to the data line 117 and the gate line 116 are formed in the edge region of the array substrate 110, The data line 117 and the gate line 116 receive a data signal and a scan signal, respectively, which are applied from a driver circuit portion (not shown)

That is, the data line 117 and the gate line 116 extend to the driving circuit portion and are connected to the corresponding data pad line 117p and the gate pad line 116p, The line 116p connects the data signal and the scan signal from the driving circuit through the data pad electrode 127p and the gate pad electrode 126p electrically connected to the data pad line 117p and the gate pad line 116p, .

For reference, reference numerals 140b and 140c denote a second contact hole and a third contact hole, respectively. Here, the data pad electrode 127p is electrically connected to the data pad line 117p through the second contact hole 140b And the gate pad electrode 126p is electrically connected to the gate pad line 116p through the third contact hole 140c.

Here, a transverse electric field type liquid crystal display device according to an embodiment of the present invention uses a half tone mask to perform a single mask process (a second mask process) on an active layer, a source / drain electrode, and a data line , And the array substrate can be manufactured by a total of four mask processes by forming the contact hole, the common electrode, and the pixel electrode in one mask process (third mask process) through selective etching of the diffraction mask and the transparent conductive film.

In particular, in the transverse electric field type liquid crystal display device according to the present invention, a protective film and a first transparent conductive film are deposited, a contact hole and a pixel electrode are formed using diffraction exposure, a second transparent conductive film is deposited thereon The problem of the afterimage of the high-transmittance panel can be solved by forming the common electrode to be self-aligned with the pixel electrode through selective etching of the transparent conductive film. This will be described in detail with reference to the following method of manufacturing the transverse electric field type liquid crystal display device.

5A to 5D are cross-sectional views sequentially showing a manufacturing process according to the A-A 'line, the BB line, and the CC line of the array substrate shown in FIG. 4. The left side shows a process of manufacturing the array substrate of the pixel portion, And a step of fabricating an array substrate of the data pad portion and the gate pad portion in turn.

6A to 6C are plan views sequentially showing the steps of manufacturing the array substrate shown in FIG.

5A and 6A, a gate electrode 121, a gate line 116, and a common line 1081 are formed in a pixel portion of an array substrate 110 made of a transparent insulating material such as glass, A gate pad line 116p is formed in the gate pad portion of the array substrate 110. [

At this time, the common line 108l is formed in a direction substantially parallel to the gate line 116 at the edge of the pixel region, while a predetermined protrusion protruded toward the pixel region for connection with a common electrode Lt; / RTI >

The gate electrode 121, the gate line 116, the common line 1081, and the gate pad line 116p are formed by depositing a first conductive film on the entire surface of the array substrate 110 and then performing a photolithography process A mask process).

Here, the first conductive layer may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum A low resistance opaque conductive material such as a molybdenum alloy can be used. The first conductive layer may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

5B and 6B, an insulating film is formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the common line 1081 and the gate pad line 116p are formed, An amorphous silicon thin film, an n + amorphous silicon thin film and a second conductive film are formed.

Thereafter, the insulating film, the amorphous silicon thin film, the n + amorphous silicon thin film and the second conductive film are selectively removed through a photolithography process (second mask process) to form a gate insulating film 115a on the gate electrode 121 The active layer 124 of the amorphous silicon thin film is formed while the source electrode 122 and the drain electrode 123 of the second conductive layer are formed on the active layer 124.

At this time, a data line 117 made of the second conductive film is formed in the data line region of the array substrate 110 through the second mask process, and a data line 117 made of the second conductive film is formed in the data pad portion of the array substrate 110, Thereby forming a data pad line 117p made of a conductive film.

In addition, the second mask process forms the storage electrode 126 on the common line 1081 in a direction substantially parallel to the gate line 116.

At this time, on the active layer 124, an n + amorphous silicon thin film is formed on the active layer 124, and an ohmic contact layer 123 is formed between the source / drain region of the active layer 124 and the source / (125n) is formed.

In addition, a first amorphous silicon thin film pattern 120 'and a fourth n + amorphous silicon thin film pattern 125' 'formed of the amorphous silicon thin film and the n + amorphous silicon thin film are formed below the storage electrode 126.

In addition, a second amorphous silicon thin film pattern 120 'and a fifth n + amorphous silicon thin film pattern 125' 'formed of the amorphous silicon thin film and the n + amorphous silicon thin film are formed below the data pad line 117p .

Here, the active layer 124, the source / drain electrodes 122 and 123, and the data line 117 according to the embodiment of the present invention can be formed by a single mask process (second mask process) by using a half-tone mask Which will be described in detail with reference to the following drawings.

7A to 7F are cross-sectional views showing the second mask process according to the embodiment of the present invention in the array substrate shown in FIG. 5B.

An insulating layer 115 and an amorphous silicon thin film 120 are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line, the common line 1081 and the gate pad line 116p are formed, the n + amorphous silicon thin film 125, and the second conductive film 130 are formed.

The second conductive layer 130 may be formed of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form a source electrode, a drain electrode, and a data line. The second conductive layer 130 may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

7B, a first photoresist layer 170 made of a photosensitive material such as photoresist is formed on the entire surface of the array substrate 110, and then a half-tone mask 180 And selectively irradiates the first photoresist layer 170 with light.

At this time, the half-tone mask 180 is provided with a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 180 is irradiated to the first photoresist layer 170.

7C, after the first photoresist layer 170 exposed through the half-tone mask 180 is developed, the first photoresist layer 170 is exposed through the blocking region III and the second transmissive region II, A first photoresist pattern 170a to a fifth photoresist pattern 170e having a predetermined thickness are left in a region where light is entirely blocked or partially blocked, and in the first transmission region I, The surface of the second conductive layer 130 is exposed.

The first photoresist pattern 170a to the fourth photoresist pattern 170d formed in the blocking region III are thicker than the fifth photoresist pattern 170e formed through the second transmissive region II. In addition, the first photoresist layer is completely removed in a region where light is entirely transmitted through the first transmissive region I because the photoresist of the positive type is used. The present invention is not limited to this, A photoresist may be used.

Next, as shown in FIG. 7D, using the first photoresist pattern 170a to the fifth photoresist pattern 170e formed as described above as a mask, an insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, When the second conductive layer is selectively removed, an active layer 124 made of the amorphous silicon thin film is formed on the gate electrode 121 with the gate insulation 115a interposed therebetween, and the gate pad portion is opened The gate pad line 116p is exposed.

The first n + amorphous silicon thin film pattern 125 ', which is composed of the n + amorphous silicon thin film and the second conductive film and is patterned substantially in the same manner as the active layer 124, is formed on the active layer 124 The first conductive film pattern 130 'is formed.

In addition, a first amorphous silicon thin film pattern 120 'composed of the amorphous silicon thin film, the n + amorphous silicon thin film and the second conductive film is formed on the common line 1081 with the gate insulating film 115a interposed therebetween, 2 n + amorphous silicon thin film pattern 125 " and the second conductive film pattern 130 "are formed.

A second amorphous silicon thin film pattern 120 'made of the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film is formed in the data pad portion of the array substrate 110 with the gate insulating film 115a interposed therebetween. The third n + amorphous silicon thin film pattern 125 '' and the third conductive film pattern 130 '' are formed.

7E, a portion of the first photoresist pattern 170a to the fifth photoresist pattern 170e is removed. As a result, as shown in FIG. 7E, The fifth photoresist pattern is completely removed.

At this time, the first to fourth photosensitive film patterns correspond to the blocking region III with the sixth photosensitive film pattern 170a 'to the ninth photosensitive film pattern 170d' removed by the thickness of the fifth photosensitive film pattern The source electrode region, the drain electrode region, the data pad line region, and the common line 108l.

Thereafter, as shown in FIG. 7F, the n + amorphous silicon thin film and the second conductive film are partially removed using the remaining sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' A source electrode 122, a drain electrode 123, and a data line (not shown), which are the second conductive film, are formed in a pixel portion of the substrate 110.

At this time, the active layer 124 is formed with the n + amorphous silicon thin film and is patterned substantially in the same shape as the source / drain electrodes 121 and 123, so that the source and drain regions of the active layer 124, And the ohmic-contact layer 125n for ohmic-contacting between the source / drain electrodes 122 and 123 are formed.

Also, a fourth n + amorphous silicon thin film pattern 125 "made of the n + amorphous silicon thin film and the second conductive film and a storage electrode 126 are formed on the first amorphous silicon thin film pattern 120 '.

The fifth n + amorphous silicon thin film pattern 125 '' 'and the data pad line 117 p are formed on the second amorphous silicon thin film pattern 120', respectively, and the n + amorphous silicon thin film and the second conductive film are formed on the second amorphous silicon thin film pattern 120 ' do.

As described above, the active layer 124, the source / drain electrodes 122 and 123, and the data line can be formed through a single mask process by using a half-tone mask.

5C, an array substrate 110 on which the active layer 124, the source / drain electrodes 122 and 123, the data lines, the storage electrodes 126, and the data pad lines 117p are formed, A protective film 115b and a first transparent conductive film are deposited on the entire surface and then selectively removed through a photolithography process (a third mask process), thereby forming a pixel portion, a data pad portion, and a gate pad portion of the array substrate 110 A first contact hole 140a and a second contact hole 140b and a third contact hole 140c are formed to expose a part of the drain electrode 123, the data pad line 117p and the gate pad line 116p And a plurality of pixel electrodes 118 made of the first transparent conductive film are formed in the pixel region.

At this time, a hole pattern for exposing the surface of the array substrate 110 is formed between the pixel electrodes 118 by selectively removing the protective film 115b and the first transparent conductive film through the third mask process.

A second transparent conductive film is deposited on the first transparent conductive film and the second transparent conductive film is selectively patterned to form the second transparent conductive film on the pixel portion and the drain electrode 123 and the second transparent conductive film are connected to each other through the first contact hole 140a. A second transparent conductive film pattern 155 'for electrical connection is formed while a common electrode 107 formed of the second transparent conductive film and self-aligned with the pixel electrode 118 is formed in the hole pattern.

The data pad portion and the gate pad portion are formed of the second transparent conductive film and are electrically connected to the data pad line 117p and the gate pad line 140b through the second contact hole 140b and the third contact hole 140c, A data pad electrode pattern 127p 'and a gate pad electrode pattern 126p' are formed. The third mask process will now be described in detail with reference to the accompanying drawings.

8A to 8J are cross-sectional views showing the third mask process according to the embodiment of the present invention in the array substrate shown in FIG. 5C.

8A, a protective film 110 is formed on an entire surface of the array substrate 110 on which the active layer 124, the source / drain electrodes 122 and 123, the data lines, the storage electrodes 126, and the data pad lines 117p are formed. The first transparent conductive film 115b and the first transparent conductive film 150 are deposited.

The first transparent conductive layer 150 may be formed of a transparent conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) .

8B, a second photoresist layer 270 made of a photosensitive material such as photoresist is formed on the entire surface of the array substrate 110, and then a diffraction mask 280 according to an embodiment of the present invention is formed. And selectively irradiates the second photoresist layer 270 with light.

At this time, the diffraction mask 280 is provided with a first transmission region I through which all the irradiated light is transmitted and a second transmission region II through which a slit pattern is applied to partially transmit only a part of light, And only the light transmitted through the diffraction mask 280 is irradiated to the second photoresist layer 270.

After the second photoresist layer 270 exposed through the diffraction mask 280 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 8C. A first photosensitive film pattern 270a to a ninth photosensitive film pattern 270i of a predetermined thickness remain in a region where all of the light is blocked or partially blocked and the second photosensitive film is completely And the surface of the first transparent conductive film 150 is exposed.

The first to third photoresist patterns 270a to 270c formed in the blocking region III may include a fourth photoresist pattern 270d through a ninth photoresist pattern 270i formed through the second transmissive region II, . In addition, the second photoresist layer is completely removed in a region where light is entirely transmitted through the first transmissive region I because the photoresist of the positive type is used. The present invention is not limited to this, A photoresist may be used.

8D, using the first photoresist pattern 270a to the ninth photoresist pattern 270i formed as described above as a mask, the protective film 115b and the first transparent conductive film 150 A portion of the drain electrode 123, the data pad line 117p, and the gate pad line 116p are electrically connected to the pixel portion, the data pad portion, and the gate pad portion of the array substrate 110, respectively, A first contact hole 140a, a second contact hole 140b and a third contact hole 140c are formed in the pixel region and a hole pattern H exposing a part of the array substrate 110 is formed in the pixel region, .

The hole pattern H may be formed in a common electrode region where a common electrode is to be formed and may be formed in a direction substantially parallel to the data line.

At this time, the first transparent conductive film 150 is selectively removed by using a wetting angle so that over etching is performed on the first photosensitive film pattern 270a to the ninth photosensitive film pattern 270i, Thus, the selective etching of the second transparent conductive film to be described later can proceed smoothly.

8E, when the ashing process for removing a portion of the first to ninth photoresist patterns 270a to 270i is performed, the fourth photoresist pattern 270a of the second transmissive area II, Pattern to the ninth photosensitive film pattern are completely removed.

In this case, the first to third photoresist patterns 270a 'to 270c' may be formed by removing the tenth photoresist pattern 270a 'to the ninth photoresist pattern 270a' Only the pixel electrode region corresponding to the pixel electrode (III) remains.

8F, a part of the first transparent conductive film is removed using the remaining tenth photosensitive film pattern 270a 'to the twelfth photosensitive film pattern 270c as masks, A plurality of pixel electrodes 118 made of the first transparent conductive film are formed on the pixel portion of the first transparent conductive film.

8G, a second transparent conductive film 155 is formed on the entire surface of the substrate 110 with the tenth photosensitive film pattern 270a 'to the twelfth photosensitive film pattern 270c remaining thereon .

At this time, the second transparent conductive layer 155 includes a transparent conductive material having high transmittance such as indium-tin-oxide or indium-zinc-oxide for forming a common electrode, a data pad electrode pattern and a gate pad electrode pattern. At this time, the surface of the tenth photosensitive film pattern 270a 'to the twelfth photosensitive film pattern 270c may be hydrophobized by plasma or heat treatment before the deposition of the second transparent conductive film 155. This is because the surface of the second transparent conductive film 155 is hydrophilic and the state of interface with the tenth photosensitive film pattern 270a 'to the twelfth photosensitive film pattern 270c is deteriorated and then the tenth photosensitive film pattern 270a' 12 photosensitive film pattern 270c 'of the second transparent conductive film 155. The second transparent conductive film 155 is formed on the photoresist pattern 270c'.

8H, a third photoresist layer 370 made of a photosensitive material such as photoresist is formed on the entire surface of the substrate 110 on which the second transparent conductive layer 155 is formed.

As shown in FIG. 8I, the ashing process for removing a portion of the third photoresist layer is performed so that the second transparent conductive film 270c 'on the tenth photoresist pattern 270a' to the twelfth photoresist pattern 270c ' (155) is exposed to the outside. At this time, a part of the thickness of the third photoresist layer is removed through the ashing process, and remains as the thirteenth photoresist pattern 370 '.

If the exposed second transparent conductive film 155 and the tenth photosensitive film patterns 270a 'to the twelfth photosensitive film patterns 270c' and the 13th photosensitive film pattern 370 'are selectively removed, A plurality of common electrodes 108 made of the second transparent conductive film are formed in the common electrode region and a second transparent conductive film pattern made of the second transparent conductive film is formed in the pixel portion, 155 ', the data pad electrode pattern 127 p', and the gate pad electrode pattern 126 p 'are formed.

At this time, the common electrode 108 is formed in the hole pattern between the pixel electrodes 118, so that the common electrode 108 is self-aligned with the pixel electrode 118, and the second transparent conductive film pattern 155 ' 1 through the contact hole.

One side of the common electrode 108 is connected to the protruding portion of the lower common line 1081.

The common electrode 108 and the pixel electrode 118 are formed to be self-aligned in the same layer and the parasitic capacitance generated between the common electrode 108 and the pixel electrode 118 is remarkably reduced, It is possible to solve the afterimage problem on the high-transmittance panel.

The data pad electrode pattern 127p 'and the gate pad electrode pattern 126p' are electrically connected to the data pad line 17p and the gate pad line 116p through the second contact hole and the third contact hole, Respectively.

Referring to FIG. 10, it can be seen that the pixel electrode and the common electrode are self-aligned according to the embodiment of the present invention, wherein the pixel electrode is formed as a first transparent conductive film, Is formed as a whole film.

5D and 6C, the common electrode 108, the pixel electrode 118, the second transparent conductive film pattern 155 ', the data pad electrode pattern 127p', and the gate pad electrode pattern A third conductive film is formed on the array substrate 110 on which the first transparent conductive film 126 p 'is formed, and then the second transparent conductive film and the third conductive film are selectively removed through a photolithography process (fourth mask process) And a connection electrode 195 formed of a third conductive film and electrically connecting the drain electrode 123 and the pixel electrode 118 is formed.

At this time, the data pad electrode pattern (127p ') and the gate pad electrode pattern (126p'), which are formed of the fourth conductive film on the data pad portion and the gate pad portion of the array substrate (110) A data pad electrode 127p and a gate pad electrode 126p are formed.

Here, the connection electrode 195 and the gate pad electrode 126p according to the embodiment of the present invention can be simultaneously formed through a single mask process (fourth mask process) by using a half-tone mask. Will be described in detail with reference to the following drawings.

9A to 9F are cross-sectional views illustrating the fourth mask process according to the embodiment of the present invention in the array substrate shown in FIG. 5D.

9A, the common electrode 108, the pixel electrode 118, the second transparent conductive film pattern 155 ', the data pad electrode pattern 127 p', and the gate pad electrode pattern 126 p ' A third conductive film 190 is formed on the formed array substrate 110.

The third conductive layer 190 may be formed of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form a connection electrode, a data pad electrode, have. In addition, the third conductive layer 190 may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

9B, a fourth photoresist layer 470 made of a photosensitive material such as photoresist is formed on the entire surface of the array substrate 110, and then a half-tone mask 480 according to an embodiment of the present invention is formed. And selectively irradiates the fourth photoresist layer 470 with light.

At this time, the half-tone mask 480 is provided with a first transmission region I for transmitting all the irradiated light and a second transmission region II for transmitting only a part of light and partially blocking the light, And only the light transmitted through the half-tone mask 480 is irradiated onto the fourth photosensitive film 470.

9C, after the fourth photoresist layer 470 exposed through the half-tone mask 480 is developed, the second photoresist layer 470 is exposed through the blocking region III and the second transmissive region II A first photoresist pattern 470a to a fourth photoresist pattern 470d having a predetermined thickness remain in a region where light is entirely blocked or partially blocked, and in the first transmission region I, The surface of the third conductive layer 190 is exposed.

At this time, the first photosensitive film pattern 470a to the third photosensitive film pattern 470c formed in the blocking region III are formed thicker than the fourth photosensitive film pattern 470d formed through the second transmission region II. In addition, the fourth photoresist layer is completely removed in the region where the light is entirely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, A photoresist may be used.

Next, as shown in FIG. 9D, using the first photosensitive film pattern 470a to the fourth photosensitive film pattern 470d formed as described above as a mask, the second transparent conductive film and the third conductive film formed thereunder are selectively The connection electrode pattern 155 '' of the second transparent conductive film is formed on the pixel portion and the third conductive layer 155 '' of the third conductive film is formed on the pixel region including the connection electrode pattern 155 ' The conductive film pattern 190 'is formed.

The data pad electrode part and the gate pad part may include a data pad electrode 127p connected to the data pad electrode pattern 127p 'and the gate pad electrode pattern 126p' And the gate pad electrode 126p are formed.

9E, when the ashing process for removing a portion of the first photoresist pattern 470a to the fourth photoresist pattern 470d is performed, the fourth photoresist pattern 470a of the second transmissive area II, The pattern is completely removed.

At this time, the first to third photosensitive film patterns correspond to the blocking region (III) with the fifth photosensitive film pattern (470a ') to the seventh photosensitive film pattern (470c') removed by the thickness of the fourth photosensitive film pattern And only on the data pad electrode 127p and the gate pad electrode 126p.

Then, as shown in FIG. 9F, the third conductive film is selectively removed using the remaining fifth photoresist pattern 470a 'to the seventh photoresist pattern 470c' as a mask to form the third conductive film And the connection electrode 195 electrically connects the drain electrode 123 and the pixel electrode 118 through the connection electrode pattern 155 'while the common electrode 108 and the pixel electrode 118 are formed. The pixel region is opened so as to be exposed to the outside.

The array substrate of the above-described embodiment of the present invention configured as described above is adhered to and opposed to the color filter substrate by a sealant formed on the outer periphery of the image display area. At this time, light is emitted from the color filter substrate to the thin film transistor, A black matrix for preventing leakage and a color filter for realizing red, green and blue colors are formed.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

The transverse electric field type liquid crystal display device according to the embodiment of the present invention has an amorphous silicon thin film transistor using an amorphous silicon thin film as an active layer. However, the present invention is not limited thereto, A polycrystalline silicon thin film transistor using a polycrystalline silicon thin film and an oxide thin film transistor using an oxide semiconductor.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a plan view showing a part of an array substrate of a general transverse electric field type liquid crystal display device.

FIGS. 3A to 3F are cross-sectional views sequentially showing a manufacturing process according to a line II-II 'of the array substrate shown in FIG. 2; FIG.

4 is a plan view schematically showing a part of an array substrate of a transverse electric field type liquid crystal display device according to an embodiment of the present invention.

FIGS. 5A to 5D are cross-sectional views sequentially showing a manufacturing process along line A-A ', line B-B, and line C-C of the array substrate shown in FIG.

6A to 6C are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.

FIGS. 7A to 7F are cross-sectional views showing the second mask process according to the embodiment of the present invention, in the array substrate shown in FIG. 5B. FIG.

8A to 8J are cross-sectional views showing the third mask process according to the embodiment of the present invention in the array substrate shown in FIG. 5C.

FIGS. 9A to 9F are cross-sectional views showing the fourth mask process according to the embodiment of the present invention, in the array substrate shown in FIG. 5D. FIG.

10 is a scanning electron microscope (SEM) image showing a state in which a pixel electrode and a common electrode are self-aligned according to an embodiment of the present invention.

DESCRIPTION OF REFERENCE NUMERALS

108: common electrode 108l: common line

110: array substrate 116: gate line

117: Data line 118: Pixel electrode

118l: pixel electrode line 121: gate electrode

122: source electrode 123: drain electrode

124: active layer 126: storage electrode

195: connecting electrode

Claims (14)

Providing a first substrate, the first substrate being divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode, a gate line, and a common line in a pixel portion of the first substrate through a first mask process; Forming an active layer on the gate electrode in a state where a gate insulating film is interposed through a second mask process; forming a source / drain electrode made of a second conductive film on the active layer and a pixel region crossing the gate line Forming a data line on the substrate; A protective film and a first transparent conductive film are deposited on the active layer, the source and drain electrodes, and the first substrate on which the data line is formed, and then selectively patterned through a third mask process, Forming a first contact hole for exposing a part of the pixel region and forming a plurality of pixel electrodes made of the first transparent conductive film in the pixel region with the protective film interposed therebetween; Forming a hole pattern for exposing the first substrate surface between the pixel electrodes by selectively patterning the protective film and the first transparent conductive film through the third mask process; A second transparent conductive film is deposited on the first substrate on which the pixel electrode is formed and the second transparent conductive film is selectively patterned to form the second transparent conductive film on the pixel portion and electrically connected to the drain electrode through the first contact hole And forming a common electrode in the hole pattern, the common electrode being made of the second transparent conductive film and being self-aligned with the pixel electrode; And A third conductive film is deposited on the first substrate on which the common electrode, the pixel electrode, and the second transparent conductive film pattern are formed, and then the second transparent conductive film pattern and the third conductive film are selectively Forming a connection electrode pattern made of the second transparent conductive film on the pixel portion by patterning and forming a connection electrode composed of the third conductive film and electrically connecting the drain electrode and the pixel electrode through the connection electrode pattern The method comprising the steps of: The method according to claim 1, further comprising forming a gate pad line made of the first conductive film on a gate pad portion of the first substrate through the first mask process . The method of claim 1, further comprising forming a storage electrode in a direction parallel to the gate line on the common line through the second mask process. The method according to claim 2, further comprising forming a data pad line made up of the second conductive film on a data pad portion of the first substrate through the second mask process . The method of claim 4, further comprising forming a second contact hole and a third contact hole exposing a portion of the data pad line and the gate pad line to the data pad portion and the gate pad portion through the third mask process The method further comprising the step of: 6. The method of claim 5, wherein the data pad portion and the gate pad portion are formed of the second transparent conductive film through the third mask process and are electrically connected to the data pad line and the data pad line through the second contact hole and the third contact hole, respectively. And forming a data pad electrode pattern and a gate pad electrode pattern electrically connected to the gate pad line. [7] The method of claim 6, further comprising forming the third conductive layer on the data pad portion and the gate pad portion of the first substrate through the fourth mask process and connecting the data pad electrode pattern and the gate pad electrode pattern, Forming a data pad electrode and a gate pad electrode on the gate insulating layer. A first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; A gate electrode formed of a first conductive film in a pixel portion of the first substrate; a gate line and a common line; An active layer formed on the gate electrode in a state where a gate insulating film is interposed, source / drain electrodes composed of a second conductive film on the active layer, and a data line crossing the gate line and defining a pixel region; A protective film formed on the active layer, the first substrate on which the source / drain electrode and the data line are formed; A plurality of pixel electrodes formed of a first transparent conductive film in the pixel region with the protective film interposed therebetween; A plurality of common electrodes formed on the first substrate surface between the pixel electrodes, the common electrodes being formed of a second transparent conductive film; A connection electrode pattern that is electrically connected to the drain electrode through a first contact hole provided in a part of the protective film and is formed of the second transparent conductive film; And And a connection electrode electrically connected to the connection electrode pattern and the pixel electrode, the connection electrode pattern being made of a third conductive film of a material different from that of the first and second transparent conductive films on the first substrate on which the connection electrode pattern is formed, Electric field type liquid crystal display device. The transverse electric field type liquid crystal display of claim 8, further comprising a gate pad line formed of the first conductive film on a gate pad portion of the first substrate. The transverse electric field type liquid crystal display of claim 8, further comprising a storage electrode formed on the common line in a direction parallel to the gate line. The liquid crystal display of claim 9, further comprising a data pad line formed of the second conductive film on a data pad of the first substrate. 12. The method of claim 11, further comprising the steps of: electrically connecting the data pad line and the gate pad line through second contact holes and third contact holes provided in other portions of the protective film, A data pad electrode pattern, and a gate pad electrode pattern. 9. The liquid crystal display of claim 8, wherein the common line has a protruding portion protruding toward the pixel region, and the plurality of common electrodes are connected to the protruding portion of the common line. 13. The transverse electric field type liquid crystal display of claim 12, further comprising a data pad electrode and a gate pad electrode which are formed of the third conductive film and connected to the data pad electrode pattern and the gate pad electrode pattern, respectively.

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