KR101369258B1 - Method of fabricating in plane switching mode liquid crystal display device - Google Patents

Abstract

According to the present invention, the active pattern, the source electrode and the drain electrode are formed in one mask process, and the pixel electrode is formed to directly connect the drain electrode without a separate contact hole, thereby reducing the number of masks and simplifying the manufacturing process. The present invention relates to a method of manufacturing a transverse electric field type liquid crystal display device.

In this case, the present invention blocks the back channel of the active pattern by removing the n + amorphous silicon thin film pattern formed in the channel region of the active pattern through a mask process for forming the pixel electrode. It is characterized in that the deterioration of characteristics of the thin film transistor can be prevented.

In addition, the present invention can form the pixel electrode adjacent to the data line by forming the common electrode in a single pattern over the entire pixel portion and having a plurality of slits in each pixel region. The transmittance of the pixel portion is improved.

Active pattern, drain electrode, pixel electrode, common electrode, number of masks

Description

Manufacturing method of transverse electric field type liquid crystal display device {METHOD OF FABRICATING IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE}

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a plan view showing a part of an array substrate of a transverse electric field type liquid crystal display device;

3A to 3F are cross-sectional views sequentially illustrating a manufacturing process along the line II-II ′ of the array substrate shown in FIG. 2.

4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention;

5A to 5E are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate shown in FIG.

6A to 6E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A to 7F are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5B and 6B.

8A to 8F are cross-sectional views illustrating a third mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5C and 6C.

9 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a second exemplary embodiment of the present invention.

10A to 10E are cross-sectional views sequentially showing manufacturing processes taken along lines IXa-IXa ', IXb-IXb, and IXc-IXc of the array substrate shown in FIG.

11A to 11E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 9.

DESCRIPTION OF REFERENCE NUMERALS

108,208 Common electrode 108s, 208s Slit

110, 210: array substrate 116, 216: gate line

117, 217: Data lines 118, 218:

121, 221: gate electrodes 122, 222: source electrode

123, 223: drain electrode 124, 224: active pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transverse electric field liquid crystal display device. More particularly, a transverse electric field liquid crystal display capable of reducing the number of masks, simplifying the manufacturing process, improving yield, and preventing deterioration of characteristics of the thin film transistor. A method of manufacturing a device.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 which distinguishes between the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode which applies a voltage to the liquid crystal layer 30. It consists of (8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constituted as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal display panel, 5 and the array substrate 10 are bonded together through a cemented key (not shown) formed on the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is as narrow as 90 degrees. This is because of the refractive anisotropy of the liquid crystal molecules, and liquid crystal molecules aligned horizontally with the substrate are oriented in a direction substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel.

Accordingly, there is an in-plane switching (IPS) type liquid crystal display device in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate to improve the viewing angle to 170 degrees or more.

2 is a plan view illustrating a part of an array substrate of a transverse electric field type liquid crystal display device.

As shown in the figure, a gate line 16 and a data line 17 are formed on the array substrate 10 of the transverse electric field type liquid crystal display device, which is arranged vertically and horizontally on the transparent array substrate 10 to define a pixel area. The thin film transistor, which is a switching element, is formed at the intersection of the gate line 16 and the data line 17.

The thin film transistor includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor may include a gate insulating film (not shown) for insulation between the gate electrode 21 and the source / drain electrodes 22 and 23 and the source electrode by a gate voltage supplied to the gate electrode 21. An active pattern (not shown) for forming a conductive channel between the 22 and the drain electrode 23 is included.

A box-shaped common electrode 8 and a pixel electrode 18 are formed in the pixel region, and the pixel electrode 18 together with the common electrode 8 generates the transverse electric field together with the pixel electrode ( 18, a plurality of slits 18s are included.

In this case, the pixel electrode 18 is electrically connected to the drain electrode 23 through a contact hole 40 formed in a passivation layer (not shown), and the common electrode 8 is connected to the gate line 16. It is connected to the common line 8l arranged in parallel.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. It is done.

3A through 3F are cross-sectional views sequentially illustrating a manufacturing process along the line II-II ′ of the array substrate illustrated in FIG. 2.

As shown in FIG. 3A, a gate electrode 21 made of a conductive metal material, a common line 8l, and a gate line (not shown) are formed on the array substrate 10 using a photolithography process (first mask process). Form.

3B, an insulating film, an amorphous silicon thin film, and an n + amorphous silicon thin film are sequentially formed on the entire surface of the array substrate 10 on which the gate electrode 21, the common line 8l, and the gate line are formed. Deposit.

Thereafter, the insulating film, the amorphous silicon thin film, and the n + amorphous silicon thin film are selectively patterned by using a photolithography process (second mask process) to form the amorphous silicon in the state where the gate insulating film 15a is interposed on the gate electrode 21. An active pattern 24 made of a thin film is formed.

At this time, an n + amorphous silicon thin film pattern 25 patterned in the same manner as the active pattern 24 is formed on the active pattern 24.

Thereafter, as illustrated in FIG. 3C, the transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (third mask process) to form the upper portion on the common line 8l. The common electrode 8 which is electrically connected to the common line 8l is formed.

As shown in FIG. 3D, a conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned using a photolithography process (a fourth mask process) to form a source on the active pattern 24. The electrode 22 and the drain electrode 23 are formed. In addition, a data line 17 defining a pixel region is formed along with the gate line through the fourth mask process.

In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 is removed between the active pattern 24 and the source / drain electrodes 22 and 23 by removing a predetermined region through the fourth mask process. An ohmic contact layer 25 'for ohmic contact is formed.

Next, as shown in FIG. 3E, a protective film 15b is deposited on the entire surface of the array substrate 10 on which the source electrode 22, the drain electrode 23, and the data line 17 are formed, and then a photolithography process. Through the fifth mask process, a portion of the passivation layer 15b is removed to form a contact hole 40 exposing a portion of the drain electrode 23.

Finally, as illustrated in FIG. 3F, the contact hole 40 is formed by depositing a transparent conductive metal material on the entire surface of the array substrate 10 and then selectively patterning the same by using a photolithography process (sixth mask process). The pixel electrode 18 is formed to be electrically connected to the drain electrode 23. In this case, the pixel electrode 18 includes a plurality of slits 18s in the pixel electrode 18 to generate a parabolic transverse electric field together with the common electrode 8 thereunder.

As described above, fabrication of an array substrate including thin film transistors requires a total of six photolithography processes for patterning a gate electrode, an active pattern, a common electrode, a source / drain electrode, a contact hole, and a pixel electrode. .

The photolithography process is a series of processes for transferring a pattern drawn on a mask onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as a photoresist application, an exposure, and a development process. There is a drawback that it drops.

In particular, the mask designed to form the pattern is very expensive, so that the manufacturing cost of the liquid crystal display device increases proportionally as the number of masks applied to the process increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device in which an array substrate is manufactured by five mask processes.

Another object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device which prevents contamination of a back channel of an active pattern generated in a process of reducing the number of masks.

Another object of the present invention is to provide a method of manufacturing a transverse electric field type liquid crystal display device to improve the transmittance of a liquid crystal display panel.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above object, a method of manufacturing a transverse electric field type liquid crystal display device of the present invention comprises the steps of providing a first substrate divided into a pixel portion, a data pad portion and a gate pad portion; Forming a gate electrode and a gate line on the pixel portion of the first substrate through a first mask process; Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming an active pattern and a source / drain electrode on the pixel portion of the first substrate through a second mask process, and forming an n + amorphous silicon thin film pattern patterned on the active pattern in the same form as the active pattern; Forming a data line defining a pixel region by crossing the gate line in the pixel portion of the first substrate using the second mask process; Forming a third conductive film on an entire surface of the first substrate on which the active pattern, the source / drain electrode, and the data line are formed, with the n + amorphous silicon thin film pattern remaining on the channel region of the active pattern; Forming a second photosensitive film on the first substrate on which the third conductive film is formed; Exposing and developing the second photoresist film through a third mask process to form first to sixth photoresist patterns; The third conductive layer and the n + amorphous silicon thin film pattern may be selectively removed by using the first to sixth photoresist patterns including the second photoresist layer as masks, and the pixel portion of the first substrate may be the same as the source / drain electrodes. Forming an ohmic contact layer patterned into a shape; An ashing process of removing a portion of the thickness of the first to sixth photoresist patterns to remove the second to sixth photoresist patterns, and leaving a seventh photoresist pattern in the pixel electrode region. ; Removing a portion of the third conductive layer using the remaining seventh photoresist pattern as a mask to form a pixel electrode in the pixel electrode region, the pixel electrode being directly connected to the drain electrode; Forming a passivation layer on the first substrate on which the pixel electrode is formed; Forming a common electrode over the entire pixel portion of the first substrate on which the passivation layer is formed, and having a plurality of slits in the pixel region; And bonding the first substrate and the second substrate to each other.

Hereinafter, a preferred embodiment of a method of manufacturing a transverse electric field type liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view schematically illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device according to a first embodiment of the present invention. The pixel of is shown.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the drawing, in the array substrate 110 according to the first embodiment of the present invention, a gate line 116 and a data line 117 are arranged vertically and horizontally on the array substrate 110 to define a pixel area. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 116 and the data line 117, and a plurality of slits for generating a transverse electric field to drive a liquid crystal (not shown). A common electrode (not shown) having a 108s and a pixel electrode 118 in the form of a box are formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

In this case, a part of the source electrode 122 extends in one direction to form a part of the data line 117, and a part of the drain electrode 123 extends toward the pixel area to directly contact the pixel electrode without a separate contact hole. 118 is electrically connected.

As described above, a common electrode and a pixel electrode 118 having a plurality of slits 108s for generating a transverse electric field are formed in the pixel region, wherein the pixel electrode 118 is formed in a box shape in the pixel region. The common electrode is formed in a single pattern over the entire pixel portion, and has a plurality of slits 108s in each pixel region.

In this case, the liquid crystal display according to the first exemplary embodiment of the present invention causes a fringe field (Fringe Field), a parabolic transverse electric field, to drive liquid crystal molecules in a liquid crystal layer (Fringe Field Switching (FFS)). For example, the liquid crystal display of FIG. 1 is shown. For this purpose, the electrode gap of the common electrode, that is, the width of the slit 108s is densely formed compared to the width of the electrode of the common electrode.

In addition, when the common electrode is formed in a single pattern over the entire pixel portion, it is necessary to form a common line for electrically connecting the common electrodes as compared with the case where the common electrode is formed in each pixel region. There will be no. As a result, the number of masks required to fabricate the array substrate 110 can be reduced by one.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

For reference, reference numerals 140a and 140b indicate a first contact hole and a second contact hole, respectively, wherein the data pad electrode 127p is electrically connected to the data pad line 117p through the first contact hole 140a. The gate pad electrode 126p is electrically connected to the gate pad line 116p through the second contact hole 140b.

Here, the transverse electric field type liquid crystal display device according to the first embodiment of the present invention uses an active pattern using a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask). By forming the source / drain electrodes and the data line in one mask process and forming a pixel electrode to directly connect the drain electrode without a separate contact hole, an array substrate may be manufactured in a total of five mask processes.

In this case, the transverse electric field type liquid crystal display device according to the first embodiment of the present invention removes the n + amorphous silicon thin film pattern formed in the channel region of the active pattern only through a mask process for forming the pixel electrode. The back channel of the pattern may be blocked to prevent contamination of the thin film transistor.

When the active pattern, the source electrode and the drain electrode are formed in one mask process to reduce the number of masks, the conductive layer is deposited to form a pixel electrode when the n + amorphous silicon thin film formed in the channel region of the active pattern is removed. In order to prevent the back channel of the active pattern from being contaminated during the etching of the conductive layer, this will be described in detail through a method of manufacturing a transverse electric field type liquid crystal display device.

5A through 5E are cross-sectional views sequentially illustrating a manufacturing process along lines IVa-IVa ', IVb-IVb, and IVc-IVc of the array substrate illustrated in FIG. 4, and on the left side, a process of manufacturing an array substrate of a pixel portion is shown. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

6A to 6E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

As shown in FIGS. 5A and 6A, a gate electrode 121 and a gate line 116 are formed in a pixel portion of the array substrate 110 made of a transparent insulating material such as glass, and the array substrate 110 may be formed. A gate pad line 116p is formed in the gate pad portion.

In this case, the gate electrode 121, the gate line 116, and the gate pad line 116p are selectively deposited through a photolithography process (first mask process) after depositing a first conductive layer on the entire surface of the array substrate 110. It is formed by patterning.

Here, the first conductive layer may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum A low resistance opaque conductive material such as a molybdenum alloy can be used. The first conductive layer may have a multi-layer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIGS. 5B and 6B, the gate insulating layer 115a and the amorphous silicon are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, and the gate pad line 116p are formed. A thin film, an n + amorphous silicon thin film and a second conductive film are formed.

Thereafter, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (second mask process) to form an active pattern including the amorphous silicon thin film in the pixel portion of the array substrate 110 ( 124 is formed, and a source electrode 122 and a drain electrode 123 formed of the second conductive layer are formed on the active pattern 124.

In this case, a data line 117 made of the second conductive layer is formed on the data line portion of the array substrate 110 through the second mask process, and the second data pad portion of the array substrate 110 is formed on the data pad portion of the array substrate 110. A data pad line 117p made of a conductive film is formed.

In this case, a first n + amorphous silicon thin film pattern 125 ′ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 124 is formed on the active pattern 124.

In addition, a lower portion of the data line 117 and the data pad line 117p is formed of the amorphous silicon thin film and the n + amorphous silicon thin film, respectively, and is patterned in the same form as the data line 117 and the data pad line 117p. The first amorphous silicon thin film pattern 120 ', the second n + amorphous silicon thin film pattern 125 ", and the second amorphous silicon thin film pattern 120" and the third n + amorphous silicon thin film pattern 125' "are formed.

Here, the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 according to the first exemplary embodiment of the present invention use a half-tone mask to perform one mask process (second mask). Process), and the second mask process will be described in detail with reference to the accompanying drawings.

7A to 7F are cross-sectional views illustrating a second mask process according to the first embodiment of the present invention in the array substrate illustrated in FIGS. 5B and 6B.

As shown in FIG. 7A, the gate insulating layer 115a, the amorphous silicon thin film 120, and n + are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, and the gate pad line 116p are formed. An amorphous silicon thin film 125 and a second conductive film 130 are formed.

The second conductive layer 130 may be formed of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, or molybdenum alloy to form a source electrode, a drain electrode, and a data line.

As shown in FIG. 7B, after the first photosensitive film 170 formed of the photosensitive material such as photoresist is formed on the entire surface of the array substrate 110, the first half- according to the first embodiment of the present invention is formed. Light is selectively irradiated to the first photosensitive layer 170 through a tone mask 180.

In this case, the first half-tone mask 180 blocks the first transmission region I transmitting all of the irradiated light and the second transmission region II transmitting only a part of the light and blocking part of the light and all the irradiated light. The blocking region III is provided, and only the light passing through the first half-tone mask 180 is irradiated to the first photosensitive film 170.

Subsequently, after developing the first photoresist layer 170 exposed through the first half-tone mask 180, as shown in FIG. 7C, the blocking region III and the second transmission region II are formed. The first photoresist pattern 170a to the fifth photoresist pattern 170e having a predetermined thickness remain in an area where all of the light is blocked or partially blocked by the light, and the first transmission area I through which all the light is transmitted The first photoresist film is completely removed to expose the surface of the second conductive film 130.

The first photoresist pattern 170a to the fourth photoresist pattern 170d formed in the blocking region III are thicker than the fifth photoresist pattern 170e formed through the second transmissive region II. In addition, the first photoresist film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto, and a negative photoresist is used. You may.

Next, as shown in FIG. 7D, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second formed on the lower portion of the first photosensitive film pattern 170a to the fifth photosensitive film pattern 170e formed as described above are used as a mask. When the conductive film is selectively removed, an active pattern 124 made of the amorphous silicon thin film is formed on the pixel portion of the array substrate 110, and the second conductive layer is formed on the data line portion of the array substrate 110. The formed data line 117 is formed.

In addition, a data pad line 117p formed of the second conductive layer is formed in the data pad part of the array substrate 110.

The first n + amorphous silicon thin film pattern 125 'formed of the n + amorphous silicon thin film and the second conductive film and patterned in the same manner as the active pattern 124 is formed on the active pattern 124, The conductive film pattern 130 'is formed.

In addition, a lower portion of the data line 117 and the data pad line 117p is formed of the amorphous silicon thin film and the n + amorphous silicon thin film, respectively, and is patterned in the same form as the data line 117 and the data pad line 117p. The first amorphous silicon thin film pattern 120 ', the second n + amorphous silicon thin film pattern 125 ", and the second amorphous silicon thin film pattern 120" and the third n + amorphous silicon thin film pattern 125' "are formed.

Subsequently, as shown in FIG. 7E, an ashing process of removing a portion of the first to fifth photoresist patterns may be performed to completely remove the fifth photoresist pattern of the second transmission region II. .

In this case, the first photoresist pattern to the fourth photoresist pattern correspond to the blocking region III by the sixth photoresist pattern 170a 'through the ninth photoresist pattern 170d' where the thickness of the fifth photoresist pattern is removed. Only the source electrode region and the drain electrode region and the upper portion of the data line 117 and the data pad line 117p remain.

Subsequently, as shown in FIG. 7F, the array substrate 110 is removed by removing a portion of the second conductive film pattern using the remaining sixth photoresist pattern 170a ′ through the ninth photoresist pattern 170d ′ as a mask. A source electrode 122 and a drain electrode 123 formed of the second conductive film are formed in the pixel portion.

In this case, the first n + amorphous silicon thin film pattern 125 ′ formed of an n + amorphous silicon thin film remains on the active pattern 124, and is formed on the entire surface of the array substrate 110 to form a pixel electrode to be described later. When the third conductive layer is deposited, the channel region of the active pattern 124, specifically, the back channel, may be prevented from being contaminated by the third conductive layer.

As described above, according to the exemplary embodiment of the present invention, the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 may be formed through a single mask process by using a half-tone mask.

Next, as illustrated in FIGS. 5C and 6C, a third conductive layer is formed on the entire surface of the array substrate 110 on which the active patterns 124, the source / drain electrodes 122 and 123, and the data lines 117 are formed. do.

Thereafter, the third conductive film is selectively patterned using a photolithography process (third mask process) to form a pixel electrode 118 directly connected to the drain electrode 123 in the pixel portion of the array substrate 110. do.

In this case, the first n + amorphous silicon thin film pattern may be selectively removed through the third mask process to ohmic contact between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123. The ohmic contact layer 125n is formed.

As described above, according to the first exemplary embodiment of the present invention, the pixel electrode 118 and the ohmic contact layer 125n can be formed through a single mask process by using a half-tone mask in the third mask process. This will be described in detail with reference to the drawings.

8A through 8F are cross-sectional views illustrating a third mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 5C and 6C.

As shown in FIG. 8A, a third conductive layer 150 is formed on the entire surface of the array substrate 110 on which the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 are formed.

In this case, the third conductive layer includes a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a pixel electrode.

In this case, when the first n + amorphous silicon thin film pattern 125 ′ remains on the channel region of the active pattern 124 as in the second embodiment of the present invention, the active pattern 124 is formed by the deposition of the third conductive layer. ) Back channel can be prevented.

As shown in FIG. 8B, after forming the second photosensitive film 270 made of the photosensitive material such as photoresist on the entire surface of the array substrate 110, the second half- according to the first embodiment of the present invention is formed. Light is selectively irradiated to the second photosensitive layer 270 through a tone mask 280.

In this case, the second half-tone mask 280 blocks the first transmission region I that transmits all of the irradiated light and the second transmission region II that transmits only a part of the light and blocks some of the light. The blocking region III is provided, and only the light passing through the second half-tone mask 280 is irradiated to the second photosensitive film 270.

Subsequently, after the second photoresist layer 270 exposed through the second half-tone mask 280 is developed, as shown in FIG. 8C, the blocking region III and the second transmission region II are formed. The first photoresist pattern 270a to the sixth photoresist pattern 270f having a predetermined thickness remain in an area where all light is partially blocked or partially blocked by the light, and the first transmission region I through which all light is transmitted The second photoresist film is completely removed to expose the surface of the third conductive film 150.

In this case, the first photoresist pattern 270a formed in the blocking region III is formed thicker than the second photoresist pattern 270b through the sixth photoresist pattern 270f formed through the second transmission region II. In addition, the second photoresist film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto. You may.

Next, as shown in FIG. 8D, the second conductive film and the first n + amorphous silicon thin film formed below the first photosensitive film pattern 270a to the sixth photosensitive film pattern 270f formed as a mask are used as a mask. When the pattern is selectively removed, an ohmic contact layer 125n formed of the n + amorphous silicon thin film and patterned in the same shape as the source / drain 122 and 123 is formed in the pixel portion of the array substrate 110. Will be.

In this case, the ohmic contact layer 125n serves to ohmic contact between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123.

Subsequently, as illustrated in FIG. 8E, an ashing process of removing a portion of the first to sixth photoresist patterns may be performed to completely complete the second to sixth photoresist patterns of the second transmission region II. Remove

In this case, the first photoresist pattern may be the seventh photoresist pattern 270a ′ removed by the thickness of the second photoresist pattern to the sixth photoresist pattern, remaining only in the pixel electrode region corresponding to the blocking region III.

Subsequently, as shown in FIG. 8F, a portion of the third conductive film is removed by using the remaining seventh photoresist pattern 270a ′ as a mask to the third conductive film in the pixel portion of the array substrate 110. The pixel electrode 118 thus formed is formed.

In this case, the pixel electrode 118 may be directly connected to a part of the drain electrode 123 without a separate contact hole, thereby eliminating a mask process required to form the contact hole.

Next, as shown in FIGS. 5D and 6D, the protective film 115b is formed on the entire surface of the array substrate 110 on which the pixel electrode 118 is formed, and then selectively selected through a photolithography process (fourth mask process). The first contact hole 140a and the second contact hole exposing a part of the data pad line 117p and the gate pad line 116p, respectively, by removing the first and second portions of the data pad portion and the gate pad portion of the array substrate 110. 140b is formed.

5E and 6E, after forming a fourth conductive film made of a transparent conductive material on the entire surface of the passivation layer 115b in which the first contact hole 140a and the second contact hole 140b are formed. By selectively patterning the photolithography process (a fifth mask process), a common electrode 108 having a plurality of slits 108s is formed in the pixel region.

In this case, by selectively patterning the fourth conductive layer using the fifth mask process, the data is formed through the first contact hole 140a and the second contact hole 140b by the data pad part and the gate pad part, respectively. The data pad electrode 127p and the gate pad electrode 126p electrically connected to the pad line 117p and the gate pad line 116p are formed.

In this case, the fourth conductive layer is a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide to form the common electrode 108, the data pad electrode 127p, and the gate pad electrode 126p. It includes.

In addition, the common electrode 108 according to the first embodiment of the present invention is formed in a single pattern over the entire pixel portion, and a plurality of common electrodes 108 are disposed in the pixel region in which the pixel electrode 118 is formed. Slits 108s are formed.

In this case, since the common electrode 108 is formed in a single pattern over the entire pixel portion, the common electrode 108 is also formed on the gate line 116, the data line 117, and the thin film transistor, in which the plurality of slits 108s are not formed. It is characterized by that.

For reference, the pixel unit refers to an image display area of the array substrate 110 in which all pixel areas are collected to display an image.

FIG. 9 is a plan view schematically illustrating a part of an array substrate of a transverse electric field type liquid crystal display according to a second exemplary embodiment of the present invention, except that the viewing angle is further improved by having a multi-domain structure. It consists of the same components as the transverse electric field type liquid crystal display device of the first embodiment.

As shown in the figure, the array substrate 210 according to the second embodiment of the present invention includes a gate line 216 and a data line 217 arranged vertically and horizontally on the array substrate 210 to define a pixel area. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 216 and the data line 217, and a plurality of slits for generating a transverse electric field to drive a liquid crystal (not shown) in the pixel area. A common electrode (not shown) having 208s and a pixel electrode 218 in the form of a box are formed.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 electrically connected to the pixel electrode 218. It is. In addition, the thin film transistor includes an active pattern (not shown) that forms a conductive channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

In this case, a part of the source electrode 222 extends in one direction to form a part of the data line 217, and a part of the drain electrode 223 extends toward the pixel area to directly contact the pixel electrode without a separate contact hole. 218 is electrically connected.

As described above, a common electrode and a pixel electrode 218 having a plurality of slits 208s for generating a transverse electric field are formed in the pixel region, wherein the pixel electrode 218 has a box shape in the pixel region. The common electrode is formed in a single pattern over the entire pixel portion, and has a plurality of slits 208s in each pixel region.

In this case, the liquid crystal display according to the second exemplary embodiment of the present invention is the same as the liquid crystal display of the first exemplary embodiment by using a fringe field switching type liquid crystal display, and for this purpose, the electrode spacing of the common electrode. That is, the width of the slit 208s is densely formed compared to the width of the electrode of the common electrode.

In the liquid crystal display according to the second exemplary embodiment, the slits 208s of the common electrode have a predetermined inclination with respect to the gate line 216 and are symmetrical with respect to the center of the pixel area. The liquid crystal molecules are arranged in two directions to form 2-domains, thereby further improving the viewing angle compared to the mono-domain. For reference, an IPS structure for forming a multi-domain of two or more domains is referred to as an S-IPS (Super-IPS) structure.

A gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in the edge region of the array substrate 210, The gate line 216 and the data line 217 transmit the scan signal and the data signal, respectively, to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, respectively, and the gate pad line 216p and the data pad The line 217p receives a scan signal and a data signal from a driving circuit unit through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, respectively. You will be authorized.

For reference, reference numerals 240a and 240b denote first contact holes and second contact holes, respectively, wherein the data pad electrode 227p and the data pad line 217p through the first contact hole 240a. The gate pad electrode 226p is electrically connected to the gate pad line 216p through the second contact hole 240b.

Hereinafter, a method of manufacturing a transverse electric field type liquid crystal display device according to a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

10A through 10E are cross-sectional views sequentially illustrating a manufacturing process along lines IXa-IXa ', IXb-IXb, and IXc-IXc of the array substrate illustrated in FIG. 9, and on the left side, a process of manufacturing an array substrate of a pixel portion is shown. The right side shows a step of manufacturing an array substrate of a data pad part and a gate pad part in order.

11A to 11E are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 9.

As shown in FIGS. 10A and 11A, a gate electrode 221 and a gate line 216 are formed in a pixel portion of the array substrate 210 made of a transparent insulating material such as glass, and the array substrate 210 may be formed. A gate pad line 216p is formed in the gate pad portion.

In this case, the gate electrode 221, the gate line 216, and the gate pad line 216p may be selectively deposited through a photolithography process (first mask process) after depositing a first conductive layer on the entire surface of the array substrate 210. It is formed by patterning.

Next, as shown in FIGS. 10B and 11B, the gate insulating layer 215a and the amorphous silicon are formed on the entire surface of the array substrate 210 on which the gate electrode 221, the gate line 216, and the gate pad line 216p are formed. A thin film, an n + amorphous silicon thin film and a second conductive film are formed.

Thereafter, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (second mask process), thereby forming an active pattern formed of the amorphous silicon thin film in the pixel portion of the array substrate 210 ( 224 is formed, and a source electrode 222 and a drain electrode 223 formed of the second conductive layer are formed on the active pattern 224.

In this case, a data line 217 made of the second conductive layer is formed in the data line portion of the array substrate 210 through the second mask process, and at the same time, the second data pad portion of the array substrate 210 is formed. A data pad line 217p made of a conductive film is formed.

In this case, a first n + amorphous silicon thin film pattern 225 ′ formed of the n + amorphous silicon thin film and patterned in the same shape as the active pattern 124 is formed on the active pattern 124.

In addition, the amorphous silicon thin film and the n + amorphous silicon thin film are formed under the data line 217 and the data pad line 217p, respectively, and are patterned in the same form as the data line 217 and the data pad line 217p. A first amorphous silicon thin film pattern (not shown), a second n + amorphous silicon thin film pattern (not shown), a second amorphous silicon thin film pattern 220 'and a third n + amorphous silicon thin film pattern 225 "are formed.

Here, the active pattern 224, the source / drain electrodes 222 and 223, and the data line 217 according to the second exemplary embodiment of the present invention use a half-tone mask to perform one mask process (second mask process). ) Can be formed at the same time.

Next, as shown in FIGS. 10C and 11C, a third conductive layer is formed on the entire surface of the array substrate 210 on which the active patterns 224, the source / drain electrodes 222 and 223, and the data lines 217 are formed. do.

Thereafter, the third conductive layer is selectively patterned using a photolithography process (third mask process) to form a pixel electrode 218 directly connected to the drain electrode 223 in the pixel portion of the array substrate 210. do.

In this case, the first n + amorphous silicon thin film pattern may be selectively removed through the third mask process to ohmic contact between the source / drain region of the active pattern 224 and the source / drain electrodes 222 and 223. The ohmic contact layer 225n is formed.

As described above, the second embodiment of the present invention uses the half-tone mask in the third mask process as in the case of the first embodiment, so that the pixel electrode 218 and the ohmic-contact layer 225n are separated once. It can be formed through the mask process.

In this case, the pixel electrode 218 may be directly connected to a part of the drain electrode 223 without a separate contact hole, thereby eliminating a mask process required to form the contact hole.

Next, as shown in FIGS. 10D and 11D, a protective film 215b is formed on the entire surface of the array substrate 210 on which the pixel electrode 218 is formed, and then selectively selected through a photolithography process (fourth mask process). The first contact hole 240a and the second contact hole exposing portions of the data pad line 217p and the gate pad line 216p, respectively, by removing the first and second portions of the data pad portion and the gate pad portion of the array substrate 210. 240b is formed.

10E and 11E, after forming a fourth conductive layer made of a transparent conductive material on the entire surface of the passivation layer 215b in which the first contact hole 240a and the second contact hole 240b are formed, By selectively patterning the photolithography process (fifth mask process), a common electrode 208 having a plurality of slits 208s is formed in the pixel region.

In this case, by selectively patterning the fourth conductive layer by using the fifth mask process, the data pad part and the gate pad part respectively pass through the first contact hole 240a and the second contact hole 240b. A data pad electrode 227p and a gate pad electrode 226p electrically connected to the line 217p and the gate pad line 216p are formed.

In this case, in the transverse electric field type liquid crystal display according to the second exemplary embodiment of the present invention, the slit 208s of the common electrode 208 has a predetermined slope with respect to the gate line 216. Since the liquid crystal molecules are arranged in two directions so as to be symmetrical with respect to the central portion of the pixel region, the viewing angle is further improved compared to the mono-domain by forming two-domains.

The array substrate of the first and second embodiments of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outer side of the image display area, wherein the thin film transistor and the gate are attached to the color filter substrate. A black matrix is formed to prevent light leakage into lines and data lines, and a color filter is formed to realize colors of red, green, and blue.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

As described above, the first and second embodiments of the present invention describe an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern as an example, but the present invention is not limited thereto. The present invention is also applied to a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as an active pattern.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

As described above, the method of manufacturing the transverse electric field type liquid crystal display device according to the present invention provides the effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost.

In addition, the manufacturing method of the transverse electric field type liquid crystal display device according to the present invention can prevent the degradation of the characteristics of the thin film transistor by blocking the back channel of the active pattern is contaminated.

Claims (15)

Providing a first substrate, the first substrate being divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode and a gate line on the pixel portion of the first substrate through a first mask process; Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming an active pattern and a source / drain electrode on the pixel portion of the first substrate through a second mask process, and forming an n + amorphous silicon thin film pattern patterned on the active pattern in the same form as the active pattern; Forming a data line defining a pixel region by crossing the gate line in the pixel portion of the first substrate using the second mask process; Forming a third conductive film on an entire surface of the first substrate on which the active pattern, the source / drain electrode, and the data line are formed, with the n + amorphous silicon thin film pattern remaining on the channel region of the active pattern; Forming a second photosensitive film on the first substrate on which the third conductive film is formed; Exposing and developing the second photoresist film through a third mask process to form first to sixth photoresist patterns; The third conductive layer and the n + amorphous silicon thin film pattern may be selectively removed by using the first to sixth photoresist patterns including the second photoresist layer as masks, and the pixel portion of the first substrate may be the same as the source / drain electrodes. Forming an ohmic contact layer patterned into a shape; An ashing process of removing a portion of the thickness of the first to sixth photoresist patterns to remove the second to sixth photoresist patterns, and leaving a seventh photoresist pattern in the pixel electrode region. ; Removing a portion of the third conductive layer using the remaining seventh photoresist pattern as a mask to form a pixel electrode in the pixel electrode region, the pixel electrode being directly connected to the drain electrode; Forming a passivation layer on the first substrate on which the pixel electrode is formed; Forming a common electrode over the entire pixel portion of the first substrate on which the passivation layer is formed, and having a plurality of slits in the pixel region; And And bonding the first substrate and the second substrate to each other. The transverse electric field liquid crystal display of claim 1, further comprising forming a gate pad line using a first conductive layer forming the gate electrode and the gate line in a gate pad portion of the first substrate. Method of manufacturing the device. The method of claim 2, wherein the gate electrode, the gate line, and the gate pad line are formed through the same first mask process. The transverse electric field method of claim 2, further comprising forming a data pad line using a second conductive layer forming the source / drain electrode and the data line in a data pad of the first substrate. Method of manufacturing a liquid crystal display device. The method of claim 1, wherein the forming of the active pattern, the source / drain electrodes, and the n + amorphous silicon thin film pattern through the second mask process is performed. Forming a gate insulating film, an amorphous silicon thin film, an n + amorphous silicon thin film, and a second conductive film on an entire surface of the first substrate on which the gate electrode and the gate line are formed; Forming a first photoresist film on the first substrate on which the second conductive film is formed; Exposing and developing the first photoresist film through a second mask process to form first to fourth photoresist patterns; The amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film may be selectively removed by using the first to fourth photosensitive film patterns including the first photosensitive film as a mask, and the amorphous silicon thin film may be formed in the pixel portion of the first substrate. Forming an n + amorphous silicon thin film pattern and a second conductive film pattern formed of the n + amorphous silicon thin film and the second conductive film on the active pattern, respectively, and patterned in the same form as the active pattern. step; Removing the fifth photoresist pattern by forming an ashing process of removing a portion of the thickness of the first photoresist pattern to the fifth photoresist pattern, and forming the sixth photoresist pattern to the ninth photoresist pattern; And Removing a portion of the second conductive film pattern using the sixth to ninth photosensitive film patterns as a mask to form a source electrode and a drain electrode formed of the second conductive film on the pixel portion of the first substrate; Method of manufacturing a transverse electric field type liquid crystal display device comprising a. 5. The method of claim 4, further comprising removing a partial region of the passivation layer to form a first contact hole and a second contact hole exposing portions of the data pad line and the gate pad line, respectively. 6. Method of manufacturing a transverse electric field liquid crystal display device. The data pad electrode and the gate of claim 6, wherein the data pad electrode and the gate pad are electrically connected to the data pad line and the gate pad line through the first contact hole and the second contact hole, respectively. A method of manufacturing a transverse electric field type liquid crystal display device further comprising the step of forming a pad electrode. The method of claim 7, wherein the common electrode, the data pad electrode, and the gate pad electrode are formed through the same second mask process. The method of claim 1, wherein the pixel electrode and the ohmic contact layer are formed through the same third mask process. The method of manufacturing a transverse electric field type liquid crystal display device according to claim 1, wherein the pixel electrode is formed in a box shape. delete delete delete The method of claim 1, wherein the slit of the common electrode has a predetermined slope with respect to the gate line and is formed to be symmetrical with respect to a central portion of the pixel area. . The method of claim 1, wherein the common electrode is formed on the gate line, the data line, and the thin film transistor.

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