KR20120075111A - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A fringe field switching liquid crystal display device and a manufacturing method thereof are provided to reduce the size of a thin film transistor. CONSTITUTION: A gate electrode(121), a gate line(116), a data line(117), and a pixel electrode(118) are formed on a first substrate. A gate insulating film is formed on the first substrate. An active layer(124) is formed on the gate electrode. The pixel electrode is exposed to the outside through a first contact hole(140a). A source electrode(122) and a drain electrode(123) are formed on the active layer. A passivation film is formed on the first substrate.

Description

Fringe field type liquid crystal display device and manufacturing method therefor {FRINGE FIELD SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same. More particularly, a fringe that prevents short defects between the data line and the pixel electrode and reduces the load of the data line. A field type liquid crystal display device and a method of manufacturing the same.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a panel, and the color filter substrate 5 And the bonding of the array substrate 10 is made through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

At this time, the driving method generally used in the liquid crystal display device is a twisted nematic (TN) method for driving the nematic liquid crystal molecules in a vertical direction with respect to the substrate, but the liquid crystal display device of the twisted nematic method Has the disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules oriented horizontally with the substrate are oriented almost perpendicular to the substrate when a voltage is applied to the panel.

Accordingly, there is an in-plane switching (IPS) type liquid crystal display device in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate to improve the viewing angle to 170 degrees or more.

FIG. 2 is a cross-sectional view illustrating a portion of an array substrate of a transverse electric field type liquid crystal display device, in which a fringe field formed between the pixel electrode and the common electrode passes through the slit to drive the liquid crystal molecules positioned on the pixel region and the common electrode. A portion of an array substrate of a fringe field switching (FFS) liquid crystal display is shown.

In the fringe field type liquid crystal display, the liquid crystal molecules are horizontally aligned, and as the pixel electrode is formed at the bottom and the common electrode is formed at the top, an electric field is generated in the horizontal and vertical directions so that the liquid crystal molecules are twisted. It is tilted and driven.

As shown in the drawing, a gate line (not shown) and a data line 17 are arranged in the array substrate 10 of a typical fringe field type liquid crystal display device to be vertically and horizontally arranged on the transparent array substrate 10 to define a pixel area. And a thin film transistor, which is a switching element, is formed in an intersection region of the gate line and the data line 17.

The thin film transistor includes a gate electrode 21 connected to the gate line, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor is formed by the gate insulating film 15a for insulation between the gate electrode 21 and the source / drain electrodes 22 and 23 and the gate electrode supplied by the gate voltage supplied to the gate electrode 21. An active layer 24 is formed between the 22 and the drain electrode 23 to form a conductive channel.

In this case, the source / drain regions of the active layer 24 form ohmic contacts with the source / drain electrodes 22 and 23 through an ohmic contact layer 25n.

The common electrode 8 and the pixel electrode 18 are formed in the pixel region, and the common electrode 8 is formed together with the pixel electrode 18 in a box shape to generate a fringe field. 8, a plurality of slits 8s are included.

In this case, the pixel electrode 18 is positioned below the drain electrode 23 to be directly and electrically connected to the drain electrode 23.

The gate pad electrode 26p and the data pad electrode 27p electrically connected to the gate line and the data line 17 are formed in the edge region of the array substrate 10 configured as described above. The scan signal and the data signal applied from (not shown) are transferred to the gate line and the data line 17, respectively.

That is, the gate line and the data line 17 extend toward the driving circuit part and are connected to the corresponding gate pad line 16p and the data pad line 17p, respectively, and the gate pad line 16p and the data pad line 17p. The scan signal and the data signal are respectively applied from the driving circuit unit through the gate pad electrode 26p and the data pad electrode 27p electrically connected to the gate pad line 16p and the data pad line 17p, respectively. .

For reference, reference numeral 15b denotes a protective film.

Hereinafter, a method of manufacturing a fringe field type liquid crystal display device configured as described above will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 2.

As shown in FIG. 3A, a gate electrode 21 made of a conductive metal material, a gate line (not shown), and a gate pad line 16p are formed on the array substrate 10 using a photolithography process (first mask process). To form.

Next, as shown in FIG. 3B, the gate insulating film 15a and the amorphous silicon thin film are sequentially formed on the entire surface of the array substrate 10 on which the gate electrode 21, the gate line, and the gate pad line 16p are formed. And n + amorphous silicon thin film.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively patterned using a photolithography process (second mask process) to form an active layer 24 formed of the amorphous silicon thin film on the gate electrode 21. .

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same manner as the active layer 24 is formed on the active layer 24.

Next, as illustrated in FIG. 3C, the transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned by using a photolithography process (third mask process) to form the transparent conductive material in the pixel region. A pixel electrode 18 made of a metal material is formed.

As shown in FIG. 3D, a conductive metal material is deposited on the entire surface of the array substrate 10 on which the pixel electrode 18 is formed, and then selectively patterned using a photolithography process (fourth mask process). The source electrode 22 and the drain electrode 23 are formed on the active layer 24, and the data line 17 defining the pixel region is formed together with the gate line.

In addition, the conductive metal material is selectively patterned through the fourth mask process to form a data pad line 17p formed of the conductive metal material.

In this case, the n + amorphous silicon thin film pattern formed on the active layer 24 is removed between the active layer 24 and the source / drain electrodes 22 and 23 by removing a predetermined region through the fourth mask process. The ohmic contact layer 25n to be contacted is formed. In addition, the drain electrode 23 is directly and electrically connected to the pixel electrode 18 positioned below the drain electrode 23.

Next, as shown in FIG. 3E, after the protective film 15b is formed on the entire surface of the array substrate 10, the protective film 15b and the gate insulating film 15a are formed using a photolithography process (a fifth mask process). The first contact hole 40a and the second contact hole 40b exposing a part of the data pad line 17p and the gate pad line 16p are formed by selectively patterning a part of the region.

In this case, the passivation layer 15b may be formed of an organic insulating material having a low dielectric constant (˜3.5) such as photoacryl to reduce parasitic capacitance due to overlap between the data line 17 and the common electrode, which will be described later. It can form using. In addition, the protective film 15b may be formed of an inorganic insulating film such as silicon nitride film (SiNx) or silicon oxide film (SiO ₂ ). To form.

Next, as illustrated in FIG. 3F, a transparent conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (sixth mask process) to common the entire pixel portion. A data pad electrode which forms an electrode 8 and is electrically connected to the data pad line 17p and the gate pad line 16p through the first contact hole 40a and the second contact hole 40b, respectively. 27p and the gate pad electrode 26p are formed.

In this case, the common electrode 8 includes a plurality of slits 8s in the common electrode 8 to generate a fringe field together with the pixel electrode 18 under the common electrode 8.

The fringe field type liquid crystal display device has a wide viewing angle, and when the common electrode 8 is formed even on the data line 17, the black matrix area can be reduced and the aperture ratio is improved.

However, parasitic capacitance is generated by the overlap between the common electrode 8 and the data line 17. In order to reduce this, even when a photoacryl having a low dielectric constant is applied, it is compared with a conventional transverse electric field type liquid crystal display device. Large capacitance will occur. This causes a decrease in charging characteristics, an increase in size of the thin film transistor, and an increase in power consumption as the load of the data line 17 increases. In addition, when applying an inorganic insulating film having a thickness increased by two to three times as compared to the conventional problem has a problem that the tack time increases by that much.

In addition, in the above case, there is an advantage in that an array substrate including thin film transistors may be manufactured using six masks. However, short circuits are caused when the data line 17 and the pixel electrode 18 are formed on the same layer. This is likely to occur. In this case, increasing the distance between the data line 17 and the pixel electrode 18 can prevent the short circuit defect, but there is a problem that the brightness of the panel is lowered while the aperture ratio is reduced.

An object of the present invention is to provide a fringe field type liquid crystal display and a method of manufacturing the same to reduce the load on a data line.

Another object of the present invention is to provide a fringe field type liquid crystal display device and a method of manufacturing the same to improve the design freedom of the wiring.

Another object of the present invention is to provide a fringe field type liquid crystal display device and a method of manufacturing the same, which improves the aperture ratio and prevents short circuit failure between the data line and the pixel electrode.

Other objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the fringe field type liquid crystal display device of the present invention comprises a gate electrode, a gate line and a data line formed in the pixel portion of the first substrate; A pixel electrode formed on the same layer of the first substrate on which the gate electrode, the gate line and the data line are formed, and an insulating film pattern formed thereon; A gate insulating film formed on the first substrate on which the gate electrode, gate line, data line, pixel electrode, and insulating film pattern are formed; An active layer formed on the gate electrode; A source / drain electrode formed on the active layer and electrically connected to a source / drain region of the active layer; A protective film formed on the first substrate on which the source / drain electrodes are formed; A common electrode formed to overlap the data line in the pixel portion of the first substrate on which the first passivation layer is formed; And a second substrate bonded to and opposed to the first substrate.

In this case, an n + amorphous silicon thin film is formed on the active layer, and further includes an ohmic contact layer which ohmic-contacts the source / drain region of the active layer and the source / drain electrode.

The common electrode is formed in a single pattern over the entire pixel portion in which an image is displayed, and has a plurality of slits in each pixel region.

The gate insulating layer and the insulating layer pattern of the pixel portion may be selectively removed to further include a first contact hole exposing the pixel electrode.

In this case, the drain electrode is electrically connected to a pixel electrode thereunder through the first contact hole.

The data line may be separated for each pixel in an area crossing the gate line.

In this case, one end of the source electrode may extend to the data line region to connect the data lines separated for each pixel.

The gate line may be separated for each pixel in an area crossing the data line.

In this case, one end of the source electrode extends to the data line region to be electrically connected to the data line, and the gate line separated through the connection electrode is connected to each other.

A method of manufacturing a fringe field type liquid crystal display device according to the present invention comprises the steps of: providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode, a gate line, and a data line on the pixel portion of the first substrate using a lift-off, and simultaneously forming a pixel electrode having an insulating layer pattern formed of an insulating material thereon; Forming a gate insulating film on the first substrate on which the gate electrode, the gate line, the data line and the pixel electrode are formed; Forming an active layer on the gate electrode on which the gate insulating film is formed; Selectively removing the gate insulating film and the insulating film pattern of the pixel portion to form a first contact hole exposing the pixel electrode; Forming a source electrode and a drain electrode on the active layer; Forming a protective film on the first substrate on which the source electrode and the drain electrode are formed; Forming a common electrode on the pixel portion of the first substrate on which the first passivation layer is formed to overlap the data line; And bonding the first substrate and the second substrate to each other.

In this case, the drain electrode is electrically connected to a pixel electrode thereunder through the first contact hole.

The common electrode may be formed to have a single pattern over the entire pixel portion and to have a plurality of slits in each pixel region.

When the gate electrode, the gate line and the data line are formed, the first substrate may further include forming a data pad line and a gate pad line in the data pad portion and the gate pad portion.

In this case, forming the gate electrode, the gate line, the data line and the pixel electrode on the first substrate may include depositing a first conductive layer and an insulating layer on the first substrate; Forming a photoresist pattern on the insulating layer except for a region where wiring is to be formed; Selectively removing the first conductive layer and the insulating layer below the photoresist pattern with a mask to form a pixel electrode pattern made of the first conductive layer in the pixel portion of the first substrate, and as the insulating layer on the pixel electrode pattern Forming an insulating film pattern; Depositing a second conductive film on the entire surface of the first substrate without removing the photoresist pattern; Selectively removing the photoresist pattern and the second conductive layer formed on the photoresist pattern through lift-off to form a gate electrode, a gate line, and a data line formed of the second conductive layer; And forming a box-type pixel electrode having a width smaller than that of the pixel electrode pattern by over-etching the first conductive layer.

In this case, the photoresist pattern may be formed between separate data lines between neighboring pixels.

In this case, the second conductive layer between the pixel electrode patterns remaining without being removed through the lift-off may form the gate electrode, the gate line, and the data line.

The photoresist pattern may be formed between the data line and the gate electrode / gate line.

In this case, when the photosensitive film pattern is formed between the data line and the gate electrode / gate line, a first conductive film pattern made of the first conductive film remains between the data line and the gate electrode / gate line. .

In this case, the second conductive layer between the pixel electrode patterns remaining without being removed through the lift-off and between the pixel electrode pattern and the first conductive layer pattern forms the gate electrode, the gate line, and the data line. It is done.

And selectively removing the gate insulating layer of the pad part to form a second contact hole and a third contact hole exposing the data pad line and the gate pad line, respectively.

In this case, the method may further include forming a data pad line pattern and a gate pad line pattern electrically connected to the data pad line and the gate pad line through the second contact hole and the third contact hole.

In this case, the data line is separated for each pixel in an area crossing the gate line.

In this case, the method may further include selectively removing the gate insulating layer to form a fourth contact hole exposing the data line at both ends of the separated data line.

In this case, one end of the source electrode may extend to the data line region to connect the data lines separated for each pixel through the fourth contact hole.

The method may further include selectively removing the passivation layer to form a fifth contact hole and a sixth contact hole exposing the data pad line pattern and the gate pad line pattern to the data pad part and the gate pad part. It features.

In this case, a data pad electrode and a gate pad electrode are electrically connected to the data pad line pattern and the gate pad line pattern through the fifth contact hole and the sixth contact hole in the data pad part and the gate pad part of the array substrate. Characterized in that it further comprises the step.

The gate line is separated for each pixel in an area crossing the data line, and an insulating layer pattern made of an insulating material is formed on the pixel electrode.

In this case, selectively removing the gate insulating layer to form a fourth contact hole exposing the data line, and forming a fifth contact hole exposing the gate line at both ends of the separated gate line. It is characterized by including.

In this case, one end of the source electrode may extend to the data line region to be electrically connected to the data line through the fourth contact hole.

And forming a connection electrode connecting the gate lines separated through the fifth contact hole to each other.

And selectively removing the passivation layer to form a sixth contact hole and a seventh contact hole exposing the data pad line pattern and the gate pad line pattern to the data pad part and the gate pad part. do.

In this case, a data pad electrode and a gate pad electrode electrically connected to the data pad line pattern and the gate pad line pattern are formed through the sixth and seventh contact holes in the data pad part and the gate pad part of the array substrate. Characterized in that it further comprises the step.

And forming an ohmic contact layer formed of an n + amorphous silicon thin film on the active layer and ohmic-contacting the source / drain region of the active layer and the source / drain electrode.

As described above, in the fringe field type liquid crystal display device and the manufacturing method thereof, the charging characteristic of the pixel is improved as the load of the data line is reduced. As a result, the performance of the thin film transistor can be improved, while the size of the thin film transistor can be reduced, thereby improving the aperture ratio. In addition, as the load on the data line is reduced, the power consumption required to drive the panel is reduced.

The fringe field type liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect of improving the design freedom of the wiring and preventing the short circuit between the data line and the pixel electrode, thereby improving the yield. In this case, as the separation distance between the wiring and the pixel electrode is reduced, the aperture ratio is improved to provide an effect of increasing the luminance of the panel.

1 is an exploded perspective view schematically showing a general liquid crystal display device.
2 is a cross-sectional view showing a part of an array substrate of a typical fringe field type liquid crystal display device.
3A to 3F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 2.
4 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a portion of an array substrate of a fringe field type liquid crystal display device according to a first exemplary embodiment of the present invention. FIG.
6A to 6G are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.
7A to 7F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 5.
8A to 8F are cross-sectional views showing in detail a first mask process according to the first embodiment of the present invention shown in FIG. 7A.
9 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a second exemplary embodiment of the present invention.
10 is a schematic cross-sectional view of a portion of an array substrate of a fringe field type liquid crystal display device according to a second exemplary embodiment of the present invention.
11A to 11F are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 9.
12A to 12F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 10.
13A to 13F are cross-sectional views showing in detail a first mask process according to a second embodiment of the present invention shown in FIG. 12A.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the fringe field type liquid crystal display device and a method of manufacturing the same.

FIG. 4 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a first embodiment of the present invention, in which a fringe field formed between the pixel electrode and the common electrode penetrates the slit and passes through the pixel region and the pixel electrode. A portion of an array substrate of a fringe field type liquid crystal display device for realizing an image by driving liquid crystal molecules positioned on is shown.

In this case, for convenience of description, one pixel including a pixel unit, a data pad unit, and a gate pad unit is illustrated. In an actual LCD device, N gate lines and M data lines intersect to form MxN pixels. Although present, one pixel is shown in the drawing for simplicity of explanation.

FIG. 5 is a cross-sectional view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a first exemplary embodiment of the present invention. FIG. It shows the cut along the cross section.

As shown in the drawing, in the array substrate 110 according to the first embodiment of the present invention, a gate line 116 and a data line 117 are arranged vertically and horizontally on the array substrate 110 to define a pixel area. Formed. In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 116 and the data line 117, and a plurality of slits 108s for generating a fringe field to drive liquid crystal molecules are formed in the pixel area. The common electrode 108 and the box-shaped pixel electrode 118 are formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. It is. In addition, the thin film transistor includes an active layer 124 that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

In this case, the source / drain regions of the active layer 124 form ohmic contacts with the source / drain electrodes 122 and 123 through the ohmic contact layer 125n.

A portion of the source electrode 122 extends in one direction to be electrically connected to the data line 117 separated for each pixel, and a portion of the drain electrode 123 extends in the pixel direction to extend the pixel electrode ( 118) electrically. In this case, the source electrode 122 is electrically connected to the separated data line 117 through the fourth contact hole 140d formed in the gate insulating film 115a and the insulating film pattern 115, and the drain electrode 123. ) Is electrically connected to the pixel electrode 118 through the first contact hole 140a formed in the gate insulating film 115a and the insulating film pattern 115.

As described above, the common electrode 108 and the pixel electrode 118 for generating a fringe field are formed in the pixel region, wherein the pixel electrode 118 is formed in a box shape in the pixel region. The common electrode 108 is formed in a single pattern over the entire pixel portion and is formed to have a plurality of slits 108s in each pixel region. However, the present invention is not limited thereto.

In this case, the liquid crystal display device according to the first embodiment of the present invention shows a fringe field type liquid crystal display device which drives a liquid crystal molecule by inducing a fringe field having a parabolic transverse electric field in the liquid crystal layer.

As the common electrode 108 is formed on the data line 117 as described above, the black matrix area can be reduced and the aperture ratio is improved. The left and right ends of the pixel electrode 118 are the outermost edges around the data line 117. It is present in the slit 108s to maximize the transmittance around the data line 117.

In addition, in the fringe field type liquid crystal display device according to the first embodiment of the present invention, the wiring (ie, the gate wiring and the data wiring) and the pixel electrode 118 are simultaneously formed by using a lift-off technique. The design freedom of the wiring can be improved, and a short circuit defect between the data line 117 and the pixel electrode 118 can be prevented. That is, the thickness of the wiring may be adjusted according to the thickness of the insulating layer pattern 115 formed on the pixel electrode 118, and a short circuit defect therebetween as the data line 117 and the pixel electrode 118 are simultaneously patterned. There is no room for this.

In this case, as the gate line 116 and the data line 117 are formed on the same layer together with the pixel electrode 118, the data line 117 intersects the gate line 116 and the data line 117. Each pixel is separated from each other in the region, and as described above, the separated data lines 117 are connected to each other through the source electrode 122. However, the present invention is not limited thereto, and the gate line 116 may be separated for each pixel in a region where the gate line 116 and the data line 117 cross each other.

In addition, in the fringe field type liquid crystal display according to the first exemplary embodiment of the present invention, the aperture ratio is improved as the distance between the wiring and the pixel electrode 118 is reduced, while the data line 117 and the common electrode 108 are improved. The parasitic capacitance therebetween can be reduced by placing the gate insulating film 115a having a thickness of about 4000 mV as well as the protective film 115b having a thickness of about 6000 mW. As a result, the performance of the thin film transistor can be improved, while the size of the thin film transistor can be reduced, thereby improving the aperture ratio.

In addition, as the load on the data line 117 is reduced, power consumption required to drive the panel is also reduced.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad The line 117p receives the scan signal and the data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

In this case, the data pad line 117p and the gate pad line 116p are formed through the second contact hole (not shown) and the third contact hole (not shown) formed in the gate insulating film 115a. ') And the gate pad line pattern 116p', respectively, and the data pad line pattern 117p 'and the gate pad line pattern 116p' each include a fifth contact hole 140e formed in the passivation layer 115b; The data pad electrode 127p and the gate pad electrode 126p are respectively connected through the sixth contact hole 140f.

Hereinafter, a method of manufacturing a fringe field type liquid crystal display device according to a first embodiment of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

6A to 6G are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

7A through 7F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 5, and a process of manufacturing an array substrate of a pixel portion is shown on the left side, and an array substrate of a data pad portion and a gate pad portion are sequentially formed on the right side. The manufacturing process is shown.

As shown in FIGS. 6A, 6B, and 7A, the gate electrode 121, the gate line 116, and the data line 117 are formed on the pixel portion of the array substrate 110 made of a transparent insulating material such as glass. The gate pad line 116p and the data pad line 117p are formed in the gate pad portion and the data pad portion of the array substrate 110, and the pixel electrode 118 is disposed in the pixel region of the array substrate 110. Form.

In this case, the data line 117 is separated for each pixel in an area crossing the gate line 116, and an insulating layer pattern 115 made of a predetermined insulating material is formed on the pixel electrode 118. It is done.

In this case, the gate electrode 121, the gate line 116, the data line 117, the gate pad line 116p, the data pad line 117p and the pixel electrode 118 is a photolithography process using a lift-off technique. It is formed simultaneously through the (first mask process), which will be described in detail with reference to the following drawings.

8A to 8F are cross-sectional views illustrating in detail a first mask process according to the first embodiment of the present invention illustrated in FIG. 7A.

As shown in FIG. 8A, the first conductive layer 130 and the insulating layer 115 ′ are deposited on the array substrate 110 made of a transparent insulating material such as glass.

In this case, the first conductive layer 130 is a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a pixel electrode. It includes.

The insulating film 115 'may be formed of an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ), and the thickness of the wiring to be formed later is determined according to the thickness thereof. Here, the wiring includes a gate electrode, a gate line, a gate pad line, a data line, and a data pad line.

Subsequently, as illustrated in FIG. 8B, a predetermined photoresist pattern 170 made of a photoresist such as photoresist is formed on the insulating layer 115 ′ using a photolithography process (first mask process).

In this case, the photoresist pattern 170 may be formed in a pixel region except for a region where wiring is to be formed. Referring to FIG. 6A, the photoresist pattern 170 may be formed between separate data lines between neighboring pixels. . However, the present invention is not limited thereto.

Next, as shown in FIG. 8C, the first conductive layer and the insulating layer below the photosensitive layer pattern 170 are selectively removed to form the first conductive layer in the pixel region of the array substrate 110. The formed pixel electrode pattern 118 'is formed.

As described above, when the photoresist pattern 170 is formed even between the separated data lines between neighboring pixels, the pixel electrode pattern 118 ′ may be connected to each other between neighboring pixels. However, the present invention is not limited thereto.

In addition, a first conductive layer pattern 130 ′ formed of the first conductive layer remains on the array substrate 110 of the data pad unit and the gate pad unit, and the pixel electrode pattern 118 ′ and the first conductive layer are formed. An insulating layer pattern 115 formed of the insulating layer is formed on the pattern 130 ′.

Here, the pixel electrode pattern 118 ′, the first conductive layer pattern 130 ′, and the insulating layer pattern 115 may have a photoresist layer pattern 170 thereon to secure a penetration path of the release agent when the lift-off is performed. It can be formed in a form having a width smaller than), but the present invention is not limited thereto.

Subsequently, as shown in FIG. 8D, the second conductive layer 180 is deposited on the entire surface of the array substrate 110 without removing the photoresist pattern 170.

In this case, the second conductive layer 180 may be formed of aluminum (Al), aluminum alloy, tungsten (W) to form a gate electrode, a gate line, a gate pad line, a data line, and a data pad line. ), Low resistance opaque conductive materials such as copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloys may be used. In addition, the second conductive layer 180 may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Thereafter, a predetermined heat treatment is performed to facilitate the lift-off prior to the lift-off, thereby generating a predetermined crack in the second conductive layer 180 formed on the photoresist pattern 170. However, the present invention is not limited thereto.

Next, as shown in FIG. 8E, the photoresist pattern is removed through lift-off, wherein the second conductive layer formed on the photoresist pattern is removed together with the photoresist pattern.

6A, the second conductive layer between the pixel electrode pattern 118 ′ remaining without being removed through the lift-off may be a gate electrode 121, a gate line 116, and a data line 117. The second conductive layer between the first conductive layer pattern 130 ′ constitutes the gate pad line 116p and the data pad line 117p.

The lift-off may deposit a conductive metal material, such as the second conductive film, on a photosensitive material, such as the photosensitive film pattern, to a predetermined thickness, and then deposit the same on a photoresist pattern by depositing a metal material deposited on a surface of the photosensitive film pattern. And the second conductive layer deposited between the pixel electrode pattern 118 'is not removed to form the gate electrode 121, the gate line 116, and the data line 117. The second conductive layer deposited between the first conductive layer pattern 130 ′ is not removed to form the gate pad line 116p and the data pad line 117p.

In this case, as described above, the data line 117 is separated for each pixel in an area crossing the gate line 116, and the data line 117 and the pixel electrode 118 are simultaneously patterned therebetween. There is no room for short circuit failure. However, the present invention is not limited thereto, and the gate line 116 may be separated for each pixel in a region where the gate line 116 and the data line 117 cross each other.

Subsequently, as illustrated in FIGS. 8F and 6B, the first conductive layer is over-etched to form a pixel electrode 118 from which a portion of the pixel electrode pattern connected between neighboring pixels is removed. 118 may have a box shape in which the width of the first conductive film pattern is partially reduced than that of the pixel electrode pattern, and the width of the first conductive film pattern is partially reduced to form the second conductive film pattern 130 ″.

Next, as shown in FIGS. 6C and 7B, the gate electrode 121, the gate line 116, the gate pad line 116p, the data line 117, the data pad line 117p and the pixel electrode ( The gate insulating layer 115a, the amorphous silicon thin film, and the n + amorphous silicon thin film are formed on the entire surface of the array substrate 110 on which the 118 is formed.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 124 made of the amorphous silicon thin film on the pixel portion of the array substrate 110. do.

In this case, the n + amorphous silicon thin film pattern 125 is formed on the active layer 124 and patterned in substantially the same shape as the active layer 124.

6D and 7C, the gate insulating film 115a and the insulating film pattern 115 of the pixel portion may be selectively removed through a photolithography process (third mask process) to form the pixel electrode 118. A second contact hole exposing a portion of the first contact hole 140a and selectively removing the gate insulating layer 115a of the pad part to expose the data pad line 117p and the gate pad line 116p, respectively. 140b and the third contact hole 140c are formed.

In this case, the fourth contact hole 140d exposing a portion of the data line 117 on both ends of the separated data line 117 by selectively removing the gate insulating film 115a through the third mask process. To form.

In this case, when using a half-tone mask or a diffraction mask, the active layer 124 and the first contact hole 140a to the fourth contact hole 140d may be simultaneously formed through one mask process. Will be.

Next, as shown in FIGS. 6E and 7D, a third conductive film is formed on the entire surface of the array substrate 110. In this case, the third conductive layer may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source electrode, a drain electrode, and a data line. The third conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Thereafter, the n + amorphous silicon thin film and the third conductive film are selectively removed through a photolithography process (a fourth mask process), so that the source electrode 122 and the drain electrode formed of the third conductive film on the active layer 124. 123 is formed.

In this case, the drain electrode 123 is electrically connected to the lower pixel electrode 118 through the first contact hole 140a, and one end of the source electrode 122 extends into the data line region. The data lines 117 separated for each pixel are connected to each other through a fourth contact hole 140d.

At this time, the third conductive layer is formed of the data pad part and the gate pad part of the array substrate 110 through the fourth mask process, and the second contact hole 140b and the third contact hole 140c are formed. The data pad line pattern 117p 'and the gate pad line pattern 116p' are electrically formed to be electrically connected to the data pad line 117p and the gate pad line 116p.

In addition, an n + amorphous silicon thin film is formed on the active layer 124 through the fourth mask process, and between the source / drain regions of the active layer 124 and the source / drain electrodes 122 and 123. An ohmic contact layer 125n for ohmic contact is formed.

Next, as illustrated in FIGS. 6F and 7E, the front surface of the array substrate 110 on which the source / drain electrodes 122 and 123, the data pad line pattern 117p ′, and the gate pad line pattern 116p ′ are formed. After the passivation layer 115b is formed on the passivation layer, the passivation layer 115b is selectively removed through a photolithography process (a fifth mask process), thereby respectively disposing the data pad line pattern 117p 'in the data pad portion and the gate pad portion of the array substrate 110. And a fifth contact hole 140e and a sixth contact hole 140f exposing a portion of the gate pad line pattern 116p '.

In this case, the protective film 115b may be formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film or an organic insulating material such as photoacrylic.

6G and 7F, after forming a fourth conductive film made of a transparent conductive material on the entire surface of the array substrate 110 on which the protective film 115b is formed, a photolithography process (a sixth mask process) is performed. By selectively patterning the same, a common electrode 108 having a plurality of slits 108s is formed in the pixel portion.

In this case, by selectively patterning the fourth conductive layer using the sixth mask process, the data pad portion and the gate pad portion respectively pass through the fifth contact hole 140e and the sixth contact hole 140f. The data pad electrode 127p and the gate pad electrode 126p electrically connected to the line pattern 117p 'and the gate pad line pattern 116p' are formed.

As described above, in the fringe field type liquid crystal display according to the first exemplary embodiment, the aperture ratio is improved as the separation distance between the wiring and the pixel electrode 118 is reduced, while the data line 117 and the common electrode 108 are improved. The parasitic capacitance therebetween can be reduced by placing the gate insulating film 115a having a thickness of about 4000 mV as well as the protective film 115b having a thickness of about 6000 mW.

The load reduction of the data line 117 has an effect similar to that of improving the performance of the thin film transistor. The size of the thin film transistor in the pixel can be reduced, thereby increasing the aperture ratio. In addition, as the load of the data line 117 decreases, power consumption required to drive the panel is reduced. In addition, the embodiment of the present invention has the advantage that it can use the existing process line.

In addition, the fringe field type liquid crystal display according to the first exemplary embodiment of the present invention prevents a short circuit failure between the data line 117 and the pixel electrode 118 and includes an array substrate 110 including thin film transistors with six masks. ) Can be manufactured.

Meanwhile, as described above, the first embodiment of the present invention shows an example in which the data line 117 is separated for each pixel in a region where the gate line 116 and the data line 117 cross each other. However, the present invention is not limited thereto. The present invention can be applied to the case where the gate line 116 is separated for each pixel in a region where the gate line 116 and the data line 117 intersect, which will be described in detail through the following second embodiment of the present invention. Explain.

9 is a plan view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a second exemplary embodiment of the present invention.

In this case, for convenience of description, one pixel including a pixel unit, a data pad unit, and a gate pad unit is illustrated. In an actual LCD device, N gate lines and M data lines intersect to form MxN pixels. Although present, one pixel is shown in the drawing for simplicity of explanation.

FIG. 10 is a cross-sectional view schematically illustrating a portion of an array substrate of a fringe field type liquid crystal display device according to a second exemplary embodiment of the present invention. FIG. It shows the cut along the cross section.

As shown in the figure, in the array substrate 210 according to the second embodiment of the present invention, a gate line 216 and a data line 217 arranged vertically and horizontally on the array substrate 210 to define a pixel area are provided. Formed. In addition, a thin film transistor, which is a switching element, is formed at an intersection of the gate line 216 and the data line 217, and a plurality of slits 208s for generating a fringe field to drive liquid crystal molecules are formed in the pixel area. The common electrode 208 and the box-shaped pixel electrode 218 are formed.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 122 connected to the data line 217, and a drain electrode 223 electrically connected to the pixel electrode 218. It is. In addition, the thin film transistor includes an active layer 224, which forms a conductive channel between the source electrode 222 and the drain electrode 223 by a gate voltage supplied to the gate electrode 221.

In this case, the source / drain regions of the active layer 224 form ohmic contacts with the source / drain electrodes 222 and 223 through the ohmic contact layer 225n.

A portion of the source electrode 222 extends in one direction to be electrically connected to the data line 217, and a portion of the drain electrode 223 extends in the pixel direction to be electrically connected to the pixel electrode 218. You will be connected to In this case, the source electrode 222 is electrically connected to the data line 217 through a fourth contact hole 240d formed in the gate insulating film 215a, and the drain electrode 223 is connected to the gate insulating film 215a. And a first contact hole 240a formed in the insulating layer pattern 215 to be electrically connected to the pixel electrode 218.

The gate line 216 is separated for each pixel at a portion crossing the data line 217, and is connected to the connection electrode 250 and the gate line through a fifth contact hole 240e formed in the gate insulating layer 215a. 216 is electrically connected. Accordingly, the gate lines 216 separated by pixels are connected to each other.

As described above, the common electrode 208 and the pixel electrode 218 for generating a fringe field are formed in the pixel region, wherein the pixel electrode 218 is formed in a box shape in the pixel region. The common electrode 208 is formed in a single pattern over the entire pixel portion, and is formed to have a plurality of slits 208s in each pixel region. However, the present invention is not limited thereto.

In this case, the liquid crystal display according to the second exemplary embodiment of the present invention shows a fringe field type liquid crystal display device which drives a liquid crystal molecule by inducing a fringe field having a parabolic transverse electric field in the liquid crystal layer.

As the common electrode 208 is formed on the data line 217 as described above, the black matrix area can be reduced and the aperture ratio is improved, and the left and right ends of the pixel electrode 218 are the outermost edges around the data line 217. It is present in the slit 208s to maximize the transmittance around the data line 217.

In addition, the fringe field type liquid crystal display according to the second exemplary embodiment of the present invention uses the lift-off technique as in the first exemplary embodiment of the present invention to provide wiring (ie, gate wiring and data wiring) and pixels. By simultaneously forming the electrodes 218, it is possible to improve the design freedom of the wiring and to prevent a short circuit failure between the data line 217 and the pixel electrode 218. That is, the thickness of the wiring can be adjusted according to the thickness of the insulating film pattern 215 formed on the pixel electrode 218, and a short circuit defect therebetween as the data line 217 and the pixel electrode 218 are simultaneously patterned. There is no room for this.

In this case, as the gate line 216 and the data line 217 are formed on the same layer together with the pixel electrode 218, the gate line 216 crosses the gate line 216 and the data line 217. Each pixel is separated from each other in the region, and as described above, the separated gate lines 216 are connected to each other through the connection electrode 250.

In addition, in the fringe field type liquid crystal display according to the second exemplary embodiment of the present invention, the aperture ratio is improved as the distance between the wiring and the pixel electrode 218 is reduced, while the data line 217 and the common electrode 208 are improved. The parasitic capacitance therebetween can be reduced by placing the gate insulating film 215a having a thickness of about 4000 mV as well as the protective film 215b having a thickness of about 6000 mW. As a result, the performance of the thin film transistor can be improved, while the size of the thin film transistor can be reduced, thereby improving the aperture ratio.

In addition, as the load of the data line 217 is reduced, power consumption required to drive the panel is also reduced.

The gate pad electrode 226p and the data pad electrode 227p electrically connected to the gate line 216 and the data line 217 are formed in the edge region of the array substrate 210 configured as described above. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 216 and the data line 217, respectively.

That is, the gate line 216 and the data line 217 extend toward the driving circuit portion and are connected to the corresponding gate pad line 216p and the data pad line 217p, respectively, and the gate pad line 216p and the data pad The line 217p receives a scan signal and a data signal from a driving circuit unit through a gate pad electrode 226p and a data pad electrode 227p electrically connected to the gate pad line 216p and the data pad line 217p, respectively. You will be authorized.

In this case, the data pad line 217p and the gate pad line 216p are formed through the second contact hole (not shown) and the third contact hole (not shown) formed in the gate insulating layer 215a. ') And the gate pad line pattern 216p', respectively, and the data pad line pattern 217p 'and the gate pad line pattern 216p' each include a sixth contact hole 240f formed in the passivation layer 215b; The data pad electrode 227p and the gate pad electrode 226p are respectively connected through the seventh contact hole 240g.

Hereinafter, a method of manufacturing a fringe field type liquid crystal display device according to a second embodiment of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

11A to 11F are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 9.

12A through 12F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 10, and a process of manufacturing an array substrate of a pixel portion is shown on the left side, and an array substrate of a data pad portion and a gate pad portion are sequentially formed on the right side. The manufacturing process is shown.

11A and 12A, a gate electrode 221, a gate line 216, and a data line 217 are formed on the pixel portion of the array substrate 210 made of a transparent insulating material such as glass. The gate pad line 216p and the data pad line 217p are formed in the gate pad portion and the data pad portion of the array substrate 210, and the pixel electrode 218 is formed in the pixel region of the array substrate 210.

In this case, the gate line 216 is separated for each pixel in an area crossing the data line 217, and an insulating layer pattern 215 made of a predetermined insulating material is formed on the pixel electrode 218. It is done.

In this case, the gate electrode 221, the gate line 216, the data line 217, the gate pad line 216p, the data pad line 217p and the pixel electrode 218 is a photolithography process using a lift-off technique. It is formed simultaneously through the (first mask process), which will be described in detail with reference to the following drawings.

13A to 13F are cross-sectional views illustrating in detail a first mask process according to a second exemplary embodiment of the present invention illustrated in FIG. 12A.

As shown in FIG. 13A, the first conductive layer 230 and the insulating layer 215 ′ are deposited on the array substrate 210 made of a transparent insulating material such as glass.

In this case, the first conductive layer 230 includes a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide to form a pixel electrode.

The insulating film 215 'may be formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film, and the thickness of the wiring to be formed later is determined according to the thickness thereof. Here, the wiring includes a gate electrode, a gate line, a gate pad line, a data line, and a data pad line.

Subsequently, as shown in FIG. 13B, a predetermined photosensitive film pattern 270 made of a photosensitive material such as a photoresist is formed on the insulating film 215 ′ using a photolithography process (first mask process).

In this case, the photoresist pattern 270 may be formed in a pixel region except for a region where wiring is to be formed. For example, the photoresist pattern 270 may be formed between the data line and the gate electrode / gate line. However, the present invention is not limited thereto.

Next, as shown in FIG. 13C, the first conductive layer and the insulating layer below the photosensitive layer pattern 270 are selectively removed to form the first conductive layer in the pixel region of the array substrate 210. The formed pixel electrode pattern 218 'is formed.

In this case, when the photosensitive film pattern 270 is formed between the data line and the gate electrode / gate line as described above, the first conductive film pattern including the first conductive film between the data line and the gate electrode / gate line. 230 'remains. In addition, the second conductive film pattern 230 ″ formed of the first conductive film remains on the array substrate 210 of the data pad part and the gate pad part, and the pixel electrode pattern 218 ′ and the first conductive film. An insulating layer pattern 215 formed of the insulating layer is formed on the pattern 230 ′ and the second conductive layer pattern 230 ″. However, the present invention is not limited thereto.

The pixel electrode pattern 218 ′, the first conductive layer pattern 230 ′, the second conductive layer pattern 230 ″, and the insulating layer pattern 215 may pass through the release path of the release agent when the lift-off is performed. In order to ensure the width can be formed in a form that is reduced in width than the upper photosensitive film pattern 270, the present invention is not limited thereto.

Thereafter, as illustrated in FIG. 13D, the second conductive layer 280 is deposited on the entire surface of the array substrate 210 without removing the photoresist pattern 270.

In this case, the second conductive layer 280 has a low resistance such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a gate electrode, a gate line, a gate pad line, a data line and a data pad line. Opaque conductive materials can be used. In addition, the second conductive layer 280 may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Subsequently, a predetermined heat treatment may be performed to facilitate the lift-off prior to the lift-off to generate a predetermined crack in the second conductive film 280 formed on the photoresist pattern 270. However, the present invention is not limited thereto.

Next, as shown in FIG. 13E, the photoresist pattern is removed through lift-off, wherein the second conductive layer formed on the photoresist pattern is removed together with the photoresist pattern.

In this case, referring to FIG. 11A, between the pixel electrode patterns 218 ′ remaining without being removed through the lift-off, and between the pixel electrode pattern 218 ′ and the first conductive layer pattern 230 ′. The second conductive film forms a gate electrode 221, a gate line 216, and a data line 217. The second conductive film between the second conductive film pattern 230 ″ is a gate pad line 216p and data. The pad line 217p is formed.

The lift-off may deposit a conductive metal material, such as the second conductive film, on a photosensitive material, such as the photosensitive film pattern, to a predetermined thickness, and then deposit the same on a photoresist pattern by depositing a metal material deposited on a surface of the photosensitive film pattern. And a second conductive layer deposited between the pixel electrode pattern 218 'and between the pixel electrode pattern 218' and the first conductive layer pattern 230 '. The gate electrode 221, the gate line 216, and the data line 217, and the second conductive layer deposited between the second conductive layer pattern 230 ″ is not removed and remains on the gate pad line ( 216p) and the data pad line 217p.

In this case, as described above, the gate line 216 is separated for each pixel in an area crossing the data line 217, and the data line 217 and the pixel electrode 218 are simultaneously patterned therebetween. There is no room for short circuit failure.

Thereafter, as illustrated in FIG. 13F, the pixel electrode 218 is formed by over-etching the first conductive layer, wherein the pixel electrode 218 has a box shape in which the width thereof is partially reduced than that of the pixel electrode pattern. In addition, the first conductive film pattern is removed and at the same time the width of the second conductive film pattern is partially reduced to form the third conductive film pattern 230 ′ ″. However, the present invention is not limited thereto. 1 The conductive film pattern may not be completely removed and may remain in a form in which the width is partially reduced.

Next, as shown in FIGS. 11B and 12B, the gate electrode 221, the gate line 216, the gate pad line 216p, the data line 217, the data pad line 217p and the pixel electrode ( The gate insulating layer 215a, the amorphous silicon thin film, and the n + amorphous silicon thin film are formed on the entire surface of the array substrate 210 on which the 218 is formed.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 224 made of the amorphous silicon thin film on the pixel portion of the array substrate 210. do.

In this case, an n + amorphous silicon thin film pattern 225 is formed on the active layer 224 and patterned in substantially the same shape as the active layer 224.

11C and 12C, the gate insulating film 215a and the insulating film pattern 215 of the pixel portion are selectively removed through a photolithography process (third mask process) to remove the pixel electrode 218. A second contact hole exposing a portion of the first contact hole 240a and selectively removing the gate insulating layer 215a of the pad part to expose the data pad line 217p and the gate pad line 216p, respectively. 240b and a third contact hole 240c are formed.

In this case, a fourth contact hole 240d exposing a portion of the data line 217 is formed by selectively removing the gate insulating layer 215a through the third mask process, and the separated gate line 216 is formed. The fifth contact hole 240e exposing a part of the gate line 216 is formed at both ends of the gate line 216.

In this case, when the half-tone mask or the diffraction mask is used, the active layer 224 and the first contact hole 240a to the fifth contact hole 240e may be simultaneously formed through one mask process.

Next, as shown in FIGS. 11D and 12D, a third conductive film is formed on the entire surface of the array substrate 210. In this case, the third conductive layer may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source electrode, a drain electrode, and a data line. The third conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Thereafter, the n + amorphous silicon thin film and the third conductive film are selectively removed through a photolithography process (a fourth mask process), so that the source electrode 222 and the drain electrode formed of the third conductive film on the active layer 224. 223 is formed.

In this case, the drain electrode 223 is electrically connected to the lower pixel electrode 218 through the first contact hole 240a, and one end of the source electrode 222 extends to the data line region. It is electrically connected to the data line 217 through the fourth contact hole 240d.

In this case, the third conductive layer is formed of the data pad portion and the gate pad portion of the array substrate 210 through the fourth mask process, and the second contact hole 240b and the third contact hole 240c are formed. The data pad line pattern 217p 'and the gate pad line pattern 216p' are formed to be electrically connected to the data pad line 217p and the gate pad line 216p. In addition, a connection electrode 250 formed of the third conductive layer through the fourth mask process and connecting the gate lines 216 separated through the fifth contact hole 240e is formed.

In addition, an n + amorphous silicon thin film is formed on the active layer 224 through the fourth mask process, and between the source / drain regions of the active layer 224 and the source / drain electrodes 222 and 223. An ohmic contact layer 225n for ohmic contact is formed.

Next, as shown in FIGS. 11E and 12E, the source / drain electrodes 222 and 223, the data pad line pattern 217p ′, the gate pad line pattern 216p ′, and the connection electrode 250 are formed. After the protective film 215b is formed on the entire surface of the array substrate 210, the protective film 215b is selectively removed through a photolithography process (fifth mask process), thereby respectively providing the data pad portion and the gate pad portion of the array substrate 210. A sixth contact hole 240f and a seventh contact hole 240g exposing portions of the line pattern 217p 'and the gate pad line pattern 216p' are formed.

In this case, the passivation layer 215b may be formed of an inorganic insulating layer such as a silicon nitride layer or a silicon oxide layer or an organic insulating material such as photoacrylic.

11F and 12F, after forming a fourth conductive film made of a transparent conductive material on the entire surface of the array substrate 210 on which the protective film 215b is formed, a photolithography process (a sixth mask process) is performed. By selectively patterning, the common electrode 208 having a plurality of slits 208s is formed in the pixel portion.

In this case, by selectively patterning the fourth conductive layer using the sixth mask process, the data pad portion and the gate pad portion respectively pass through the sixth contact hole 240f and the seventh contact hole 240g. The data pad electrode 227p and the gate pad electrode 226p electrically connected to the line pattern 217p 'and the gate pad line pattern 216p' are formed.

As described above, in the fringe field type liquid crystal display device according to the second embodiment of the present invention, the aperture ratio is improved as the separation distance between the wiring and the pixel electrode 218 is reduced as in the first embodiment of the present invention. Meanwhile, the parasitic capacitance between the data line 217 and the common electrode 208 as well as the protective insulating film 215b having a thickness of about 6000 μs as well as the gate insulating film 215a having a thickness of about 4000 μs can be reduced.

The load reduction of the data line 217 has an effect similar to that of improving the performance of the thin film transistor. The size of the thin film transistor in the pixel can be reduced, thereby improving the aperture ratio. For example, in the case of the 9.7 ″ QXGA (Quad eXtended Graphics Array) model, the parasitic capacitance of the data line 217 is reduced by about 27% to 106.00pF compared to the conventional transverse liquid crystal display (~ 181.00pF). Can be.

As the load of the data line 217 decreases as described above, power consumption required to drive the panel is reduced. In addition, the embodiment of the present invention has the advantage that it can use the existing process line.

In addition, the fringe field type liquid crystal display according to the second exemplary embodiment of the present invention is an array substrate 210 including thin film transistors with six masks while preventing short circuit between the data line 217 and the pixel electrode 218. ) Can be manufactured.

The array substrates of the first and second embodiments of the present invention configured as described above are bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor, the gate line, A black matrix is formed to prevent light leakage from the data line, and a color filter is formed to realize red, green, and blue colors.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

In the fringe field type liquid crystal display device according to the embodiment of the present invention, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active layer is described as an example. However, the present invention is not limited thereto, and the present invention is not limited thereto. The same applies to polycrystalline silicon thin film transistors using thin films.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

108,208 Common electrode 108s, 208s Slit
110,210: array substrate 116,216: gate line
116p, 216p: Gate pad line 116p ', 216p': Gate pad line pattern
117,217: Data line 117p, 217p: Data pad line
117p ', 217p': Data pad line pattern 118,218: Pixel electrode
121,221 gate electrode 122,222 source electrode
123,223 Drain electrode 124,224 Active layer
126p, 226p: Gate pad electrode 127p, 227p: Data pad electrode
250: connecting electrode

Claims (33)

Providing a first substrate divided into a pixel portion, a data pad portion, and a gate pad portion;
Forming a gate electrode, a gate line, and a data line on the pixel portion of the first substrate using a lift-off, and simultaneously forming a pixel electrode having an insulating layer pattern formed of an insulating material thereon;
Forming a gate insulating film on the first substrate on which the gate electrode, the gate line, the data line and the pixel electrode are formed;
Forming an active layer on the gate electrode on which the gate insulating film is formed;
Selectively removing the gate insulating film and the insulating film pattern of the pixel portion to form a first contact hole exposing the pixel electrode;
Forming a source electrode and a drain electrode on the active layer;
Forming a protective film on the first substrate on which the source electrode and the drain electrode are formed;
Forming a common electrode on the pixel portion of the first substrate on which the first passivation layer is formed to overlap the data line; And
A method of manufacturing a fringe field type liquid crystal display device comprising the step of bonding the first substrate and the second substrate. The method of claim 1, wherein the drain electrode is electrically connected to a pixel electrode thereunder through the first contact hole. 2. The method of claim 1, wherein the common electrode is formed in a single pattern over the entire pixel portion and has a plurality of slits in each pixel region. The method of claim 1, further comprising: forming the data pad line and the gate pad line in the data pad part and the gate pad part when the gate electrode, the gate line, and the data line are formed. A method of manufacturing a fringe field type liquid crystal display device. The method of claim 4, wherein the forming of the gate electrode, the gate line, the data line and the pixel electrode on the first substrate is performed.
Depositing a first conductive film and an insulating film on the first substrate;
Forming a photoresist pattern on the insulating layer except for a region where wiring is to be formed;
Selectively removing the first conductive layer and the insulating layer below the photoresist pattern with a mask to form a pixel electrode pattern made of the first conductive layer in the pixel portion of the first substrate, and as the insulating layer on the pixel electrode pattern Forming an insulating film pattern;
Depositing a second conductive film on the entire surface of the first substrate without removing the photoresist pattern;
Selectively removing the photoresist pattern and the second conductive layer formed on the photoresist pattern through lift-off to form a gate electrode, a gate line, and a data line formed of the second conductive layer; And
And over-etching the first conductive layer to form a box-shaped pixel electrode having a width smaller than that of the pixel electrode pattern. 6. The method of claim 5, wherein the photoresist pattern is also formed between separate data lines between neighboring pixels. 7. The fringe field type liquid crystal display of claim 6, wherein the second conductive layer between the pixel electrode patterns remaining without being removed through the lift-off forms the gate electrode, the gate line, and the data line. Manufacturing method. 6. The method of claim 5, wherein the photoresist pattern is also formed between the data line and the gate electrode / gate line. 10. The method of claim 8, wherein when the photoresist pattern is formed between the data line and the gate electrode / gate line, a first conductive layer pattern including the first conductive layer remains between the data line and the gate electrode / gate line. A method of manufacturing a fringe field type liquid crystal display device. 10. The gate electrode of claim 9, wherein the second conductive layer between the pixel electrode patterns remaining without being removed through the lift-off and between the pixel electrode pattern and the first conductive layer pattern includes the gate electrode, the gate line, and the data line. Forming a fringe field type liquid crystal display device characterized in that it is formed. The method of claim 5, further comprising selectively removing the gate insulating layer of the pad part to form a second contact hole and a third contact hole exposing the data pad line and the gate pad line, respectively. Method for manufacturing fringe field type liquid crystal display device. The method of claim 11, further comprising forming a data pad line pattern and a gate pad line pattern electrically connected to the data pad line and the gate pad line through the second contact hole and the third contact hole. A method of manufacturing a fringe field type liquid crystal display device. 13. The method of claim 12, wherein the data lines are separated for each pixel in an area crossing the gate line. 15. The fringe field type liquid crystal display of claim 13, further comprising selectively removing the gate insulating layer to form a fourth contact hole exposing the data line across the separated data line. Manufacturing method. 15. The method of claim 14, wherein one end of the source electrode extends into the data line region to connect the data lines separated for each pixel through the fourth contact hole. . The method of claim 15, further comprising selectively removing the passivation layer to form a fifth contact hole and a sixth contact hole exposing the data pad line pattern and the gate pad line pattern to the data pad part and the gate pad part. Method for manufacturing a fringe field type liquid crystal display device comprising a. The data pad electrode and the gate of claim 16, wherein the data pad electrode and the gate pad are electrically connected to the data pad line pattern and the gate pad line pattern through the fifth contact hole and the sixth contact hole. A method of manufacturing a fringe field type liquid crystal display further comprising the step of forming a pad electrode. 13. The fringe field type liquid crystal display device of claim 12, wherein the gate line is separated for each pixel in an area crossing the data line, and an insulating layer pattern made of an insulating material is formed on the pixel electrode. Way. 19. The method of claim 18, wherein the gate insulating layer is selectively removed to form a fourth contact hole for exposing the data line, and a fifth contact hole for exposing the gate line is formed at both ends of the separated gate line. A method of manufacturing a fringe field type liquid crystal display, further comprising the step. 20. The method of claim 19, wherein one end of the source electrode extends into the data line region and is electrically connected to the data line through the fourth contact hole. 20. The method of claim 19, further comprising forming a connection electrode connecting the gate lines separated through the fifth contact hole to each other. The method of claim 19, further comprising selectively removing the passivation layer to form a sixth contact hole and a seventh contact hole exposing the data pad line pattern and the gate pad line pattern to the data pad part and the gate pad part. Method for manufacturing a fringe field type liquid crystal display device comprising a. The data pad electrode and the gate of claim 22, wherein the data pad line and the gate pad line pattern are electrically connected to the data pad line pattern and the gate pad line pattern through the sixth and seventh contact holes of the data pad portion and the gate pad portion of the array substrate. A method of manufacturing a fringe field type liquid crystal display further comprising the step of forming a pad electrode. The method of claim 1, further comprising: forming an ohmic contact layer formed of an n + amorphous silicon thin film on the active layer and ohmic contacting a source / drain region of the active layer and the source / drain electrode. A method of manufacturing a fringe field type liquid crystal display device. A gate electrode, a gate line, and a data line formed in the pixel portion of the first substrate;
A pixel electrode formed on the same layer of the first substrate on which the gate electrode, the gate line and the data line are formed, and an insulating film pattern formed thereon;
A gate insulating film formed on the first substrate on which the gate electrode, gate line, data line, pixel electrode, and insulating film pattern are formed;
An active layer formed on the gate electrode;
A source / drain electrode formed on the active layer and electrically connected to a source / drain region of the active layer;
A protective film formed on the first substrate on which the source / drain electrodes are formed;
A common electrode formed to overlap the data line in the pixel portion of the first substrate on which the first passivation layer is formed; And
A fringe field type liquid crystal display device comprising a second substrate bonded to and opposed to the first substrate. 27. The semiconductor device of claim 25, further comprising an ohmic contact layer formed of an n + amorphous silicon thin film on the active layer and ohmic contacting a source / drain region of the active layer and the source / drain electrode. Fringe field type liquid crystal display device. 27. The fringe field type liquid crystal display device according to claim 25, wherein the common electrode is formed in a single pattern over the entire pixel portion where the image is displayed and has a plurality of slits in each pixel region. 26. The fringe field type liquid crystal display device according to claim 25, further comprising a first contact hole for selectively removing the gate insulating film and the insulating film pattern of the pixel portion to expose the pixel electrode. 29. The fringe field type liquid crystal display device of claim 28, wherein the drain electrode is electrically connected to a pixel electrode thereunder through the first contact hole. 27. The fringe field type liquid crystal display of claim 25, wherein the data lines are separated for each pixel in a region crossing the gate line. 31. The fringe field type liquid crystal display of claim 30, wherein one end of the source electrode extends into a data line region to connect data lines separated by pixels. 27. The fringe field type liquid crystal display of claim 25, wherein the gate lines are separated for each pixel in areas crossing the data lines. 33. The fringe field type liquid crystal of claim 32, wherein one end of the source electrode extends into the data line region to be electrically connected to the data line, and the gate lines separated through a connection electrode are connected to each other. Display.

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