KR102062801B1 - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

In the fringe-field switching (FFS) liquid crystal display of the present invention and a method of manufacturing the same, a common voltage between adjacent pixels is connected up and down by using data wiring to reduce ripple of a common voltage without changing transmittance. It is characterized by improving.
This provides an effect of improving image quality by improving horizontal crosstalk.

Description

Fringe-field type liquid crystal display device and manufacturing method therefor {FRINGE FIELD SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fringe-field type liquid crystal display device and a manufacturing method thereof, and more particularly, to a fringe-field type liquid crystal display device and a method of manufacturing the same that can simultaneously realize high resolution and high transmittance.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

Hereinafter, a general liquid crystal display device will be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display.

Referring to FIG. 1, a general liquid crystal display device includes a color filter substrate 5 and an array substrate 10, and a liquid crystal layer 30 formed between the color filter substrate 5 and the array substrate 10. It consists of.

The color filter substrate 5 is a sub-color filter C and a sub-color filter 7 composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B). A black matrix 6 that separates the color filters 7 and blocks light that passes through the liquid crystal layer 30, and a transparent common electrode 8 that applies a voltage to the liquid crystal layer 30. consist of.

The array substrate 10 is formed in a cross region of the gate lines 16 and the data lines 17 and the gate lines 16 and the data lines 17 which are arranged in a vertical direction and define a plurality of pixel regions P. FIG. A thin film transistor (TFT) T, which is a switching element, and a pixel electrode 18 formed in the pixel region P are included.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal panel. The bonding of the array substrate 10 is performed through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

A driving method generally used in a liquid crystal display device is a twisted nematic (TN) method for driving nematic liquid crystal molecules in a direction perpendicular to a substrate.

Twisted nematic liquid crystal display has a disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules because the liquid crystal molecules oriented horizontally with the substrate are oriented almost perpendicular to the substrate when a voltage is applied to the liquid crystal panel.

Accordingly, there is an in-plane switching (IPS) type liquid crystal display device in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve a viewing angle to 170 degrees or more.

Of the in-plane switching methods, fringe-field switching (FFS) liquid crystal displays have an advantage of improved viewing angle and transmittance compared to conventional twisted nematic methods.

However, since a plurality of mask processes (ie, photolithography processes) are required to fabricate an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required.

In order to form an upper and lower electric field between the common electrode and the pixel electrode, the common electrode and the pixel electrode should be formed on different layers with a protective layer interposed therebetween, and thus, at least two or more than the twisted nematic liquid crystal display device. More mask processing is needed.

Meanwhile, in the fringe-field type liquid crystal display, since the common electrode is formed on a lower array substrate in pixel units, a common line and a connection line for transferring common voltage between pixels to the array substrate are required.

In general, the common line is formed of a gate line to transfer a common voltage between adjacent pixels to the left and right. In addition, the connection line is formed of the same indium tin oxide (ITO) as the common electrode to transfer a common voltage between adjacent pixels up and down.

In this case, the common voltage is shaken whenever the gate or data voltage is changed by the resistance of the connection line, which is called a ripple phenomenon of the common voltage.

In particular, in the case of a square model having a resolution such as 1920x1920, the ripple of the common voltage increases as the resistance in the vertical direction increases. This may cause image defects such as horizontal crosstalk.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fringe-field type liquid crystal display device and a method of manufacturing the same, which reduce the ripple of the common voltage by reducing the resistance in the vertical direction.

Another object of the present invention is to provide a fringe-field type liquid crystal display device and a method of manufacturing the same, which produce an array substrate by six mask processes.

Other objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, a fringe-field type liquid crystal display device according to an embodiment of the present invention is connected to a gate electrode and a common line and a pixel electrode on a substrate, an active layer and a source / drain electrode and a connection on a gate insulating layer. And a common electrode having a plurality of slits on the line and the protective layer, wherein the common electrode may be electrically connected to the common line, and the common electrodes between pixels adjacent to each other up and down through the connection line may be connected to each other. have.

In this case, the connection line may be made of the same low resistance conductive material as the source electrode and the drain electrode.

In this case, the fringe-field type liquid crystal display according to the exemplary embodiment of the present invention may be disposed on the protective layer and further include a connection electrode electrically connecting the drain electrode and the pixel electrode.

In this case, the connection electrode may be contacted (connected) not only on the upper surface of the drain electrode but also on the side surface thereof.

One side of the connection line may be connected to the common electrode and the common line of the lower pixel, and the other side may be connected to the common electrode of the upper pixel.

The common electrode may be contacted (connected) at the side as well as the upper surface of the connection line.

A method of manufacturing a fringe-field type liquid crystal display according to an exemplary embodiment of the present invention includes forming a common line with a gate electrode on a substrate on which a pixel electrode is formed, and forming an active layer, a source / drain electrode, and a connection line on the gate insulating layer. The method may include forming a common electrode on the passivation layer and electrically connecting the common line to the common layer, and connecting the common electrodes between adjacent pixels up and down through the connection line.

In this case, the method of manufacturing a fringe-field type liquid crystal display according to an exemplary embodiment of the present invention may further include forming a connection electrode connecting the pixel electrode and the drain electrode through the third contact hole on the protective layer. have.

As described above, the fringe-field type liquid crystal display device and the method of manufacturing the same according to the embodiment of the present invention connect the common electrodes between up and down neighboring pixels using data lines to reduce the ripple of the common voltage without changing the transmittance. It can be improved. This provides an effect of improving image quality by improving horizontal crosstalk.

In addition, the fringe-field type liquid crystal display device and the method of manufacturing the same according to an embodiment of the present invention provide the effect of reducing the number of masks, simplifying the manufacturing process and reducing the manufacturing cost.

1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display.
2 is a plan view schematically illustrating a portion of an array substrate of a fringe-field type liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view taken along line AA ′ of the array substrate of the fringe-field type liquid crystal display device shown in FIG. 2. FIG.
4 is a schematic cross-sectional view taken along line B-B 'of the array substrate of the fringe-field type liquid crystal display device according to the exemplary embodiment of the present invention shown in FIG.
5 is a graph showing a change in common voltage over time as an example.
6A to 6F are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 2.
7A to 7F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.
8A through 8F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

Hereinafter, exemplary embodiments of the fringe-field type liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. .

Advantages and features of the present invention, and methods for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments to make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout. In the drawings, the size and relative size of layers and regions may be exaggerated for clarity.

When an element or layer is referred to as another element or "on" or "on", it includes both instances of another element or layer interposed therebetween, as well as other elements or layers. do. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that it does not intervene with another device or layer in between.

The spatially relative terms "below, beneath", "lower", "above", "upper", and the like, as shown in the figures, are one element or component. It may be used to easily describe the correlation between and other elements or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprise” and / or “comprising” refers to a component, step, operation and / or element that is present in one or more other components, steps, operations and / or elements. Or does not exclude additions.

2 is a plan view schematically illustrating a portion of an array substrate of a fringe-field type liquid crystal display according to an exemplary embodiment of the present invention.

2 illustrates an array substrate of a fringe-field type liquid crystal display device in which an fringe-field formed between the pixel electrode and the common electrode is driven through a slit to drive liquid crystal molecules positioned on the pixel region and the pixel electrode. Showing some.

In the fringe-field type liquid crystal display, the liquid crystal molecules are horizontally aligned, and as the pixel electrode is formed at the bottom and the common electrode having the slit is formed at the top, an electric field is generated in the horizontal and vertical directions so that the liquid crystal molecules are twisted. It is driven by a twist and a tilt. However, the present invention is not limited to the above structure.

At this time, in the actual liquid crystal display device, N gate lines and M data lines cross each other, and there are M × N pixels. However, one pixel is shown in FIG.

3 is a diagram schematically illustrating a cross section taken along line AA ′ of the array substrate of the fringe-field type liquid crystal display device shown in FIG. 2.

FIG. 4 is a schematic cross-sectional view taken along line B-B 'of the array substrate of the fringe-field type liquid crystal display according to the exemplary embodiment of the present invention shown in FIG. 2.

2 to 4, the fringe-field type liquid crystal display according to the exemplary embodiment of the present invention has a gate line 116 and a data line arranged vertically and horizontally on the array substrate 110 to define a pixel area. 117 is formed.

In addition, a thin film transistor, which is a switching element, is formed in an intersection area between the gate line 116 and the data line 117. In the pixel area, a pixel electrode 118 for generating a fringe-field to drive liquid crystal molecules and a plurality of pixel electrodes The common electrode 108 having the slit 108s is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118 through the connection electrode 130. )

That is, the connection electrode 130 is the pixel electrode 118 and the drain electrode 123 through the first contact hole 140a and the third contact hole 140c formed in the gate insulating layer 115a and the protective layer 115b. Is electrically connected.

At this time, the connection electrode 130 according to the embodiment of the present invention has an effect of lowering the contact resistance as the contact (connection) is made not only on the upper surface of the drain electrode 123 but also on the side of the drain electrode 123. This is because the third contact hole 140c is formed on the first contact hole 140a to expose one side of the drain electrode 123.

The drain electrode 123 according to the exemplary embodiment of the present invention has a case in which the surface of the drain electrode 123 is just patterned with the side of the first contact hole 140a at the bottom, but for convenience of description, the drain electrode 123 is provided. A portion of the silver may be formed in the first contact hole 140a.

In addition, the thin film transistor is connected to the source electrode 122 by a gate voltage supplied to the gate insulating layer 115a and the gate electrode 121 for insulation between the gate electrode 121 and the source / drain electrodes 122 and 123. The active layer 124 forms a conductive channel between the drain electrodes 123.

In this case, an amorphous silicon thin film may be used as the active layer 124. In this case, the source / drain region of the active layer 124 may be a source / drain through an ohmic contact layer 125. The ohmic contact is formed with the electrodes 122 and 123.

However, the present invention is not limited thereto. In addition to the amorphous silicon thin film, a polycrystalline silicon thin film obtained by crystallizing amorphous silicon, an organic semiconductor, an oxide semiconductor, or the like may be used.

In this case, an amorphous silicon thin film and an n + amorphous silicon thin film are formed below the data line 117, and the first amorphous silicon thin film pattern 124 ′ and the first n + amorphous silicon patterned in substantially the same shape as the data line 117. The thin film pattern 125 'is formed. However, the present invention is not limited thereto, and the active layer 124 and the data line (that is, the source electrode 122, the drain electrode 123, and the data line 117) are formed by using different mask processes. In this case, the data line 117 may be formed directly on the gate insulating layer 115a.

As described above, the common electrode 108 and the pixel electrode 118 are formed in the pixel region to generate a fringe-field, wherein the rectangular common electrode 108 is formed together with the pixel electrode 118. In order to generate a field, the common electrode 108 includes a plurality of slits 108s. However, the present invention is not limited to the structures of the common electrode 108 and the pixel electrode 118. The present invention is also applicable to a case in which a common electrode is formed at the bottom and a pixel electrode having a plurality of slits is formed at the top. It is possible.

In this case, the common electrode 108 includes a first common electrode 108a and a second common electrode 108b.

The first common electrode 108a may be positioned at the edge of the pixel region to form a frame having a vertical shape. The second common electrode 108b may have a finger shape with the slits 108s therebetween in the pixel area.

In addition, the second common electrode 108b may be configured to be inclined to be symmetrical with respect to the center of the common electrode 108, and in this case, may form a two-domain structure.

In the fringe-field type liquid crystal display according to the exemplary embodiment of the present invention configured as described above, as the common electrode 108 is formed on the lower array substrate 110 in units of pixels, the common line 108L for transferring the common voltage between pixels is provided. And it characterized in that it comprises a connection line (135).

The common line 108L may be made of the same conductive material as the gate line (that is, the gate electrode 121 and the gate line 116). The common line 108L may be formed in a direction parallel to the gate line 116 to transfer a common voltage between pixels adjacent to left and right.

The connection line 135 may be made of the same conductive material as the data line. The connection line 135 may be formed in a direction crossing the gate line 116 to transfer a common voltage between adjacent pixels up and down.

One side of the connection line 135 is connected to the first common electrode 108a and the common line 108L on the lower side through the second contact hole 140b and the fifth contact hole 140e, and the other side of the connection line 135 is formed. Four contact holes 140d are connected to the upper first common electrode 108a.

A second amorphous silicon thin film pattern 124 ″ and a second n + amorphous silicon thin film pattern formed of an amorphous silicon thin film and an n + amorphous silicon thin film under the connection line 135 and patterned in substantially the same shape as the connection line 135. 125 "is formed. However, as described above, the present invention is not limited thereto.

At this time, in the case of the embodiment of the present invention, the first common electrode 108a has the effect of lowering the contact resistance as the contact (connection) is made not only on the upper surface of the connection line 135 but also on the side of the connection line 135. Have This is because the fourth contact hole 140d and the fifth contact hole 140e are formed to expose one side of the connection line 135.

Although the connection line 135 according to an embodiment of the present invention is also patterned to be just (just) with the side of the second contact hole 140b at the bottom, this is for convenience of description and the connection line 135 A portion of the silver may be formed in the second contact hole 140b.

As such, since the connection line 135 according to the embodiment of the present invention is formed of a low resistance data line, the overall resistance of the common electrode 108 may be reduced without changing transmittance. Therefore, the ripple of the common voltage can be improved, and the image quality is improved by improving the horizontal crosstalk.

5 is a graph showing a change in common voltage over time as an example.

At this time, Figure 5 shows the change in the common voltage over time when the common voltage is set to about 5.25V, showing a simulation result of a 26.5 inch square model having a resolution of 1920x1920 as an example.

In this case, the comparative example shows a case where the connection line is composed of ITO, and the embodiment shows a case where the connection line is composed of copper (Cu) as an example.

The resistivity of ITO can be seen that 100 times greater of Cu with a resistivity of 2.47x10 ^-6 [Ωm] to 248x10 ^-6 [Ωm].

In this case, the resistance of the common electrode with respect to one pixel in the vertical direction is about 1346 kW in the comparative example, but the 29% decrease is about 959 kV in the exemplary embodiment.

In addition, the resistance of the common electrode with respect to one line in the vertical direction is about 2585 kW in the comparative example, while the example is about 1840 kW, which is reduced by about 29%.

Therefore, referring to FIG. 5, the ripple of the common voltage is measured to be about 22 mV in the comparative example, while the measurement is about 19 mV in the example, which is about 14% improvement.

As described above, in the exemplary embodiment of the present invention, the ripple of the common voltage can be reduced without changing transmittance by changing the connection structure of the common electrode in the vertical direction.

For reference, in the ripple of the common voltage, parasitic capacitance exists between the common line, the gate wiring, and the data wiring, and coupling occurs when the voltage changes. At this time, the magnitude of the ripple of the common voltage increases in proportion to the magnitude of the resistance and the parasitic capacitance of the common electrode.

In particular, in the case of the square model, as the vertical resolution increases, the resistance of the common electrode in the vertical direction increases, thereby causing a ripple of the common voltage in the center region of the liquid crystal panel.

As such, the fringe-field type liquid crystal display device according to the embodiment of the present invention maintains the advantages of high resolution and high transmittance, and connects common electrodes between pixels adjacent to each other up and down by using data wiring to change the common voltage without changing transmittance. It is characterized by improving the ripple of.

At this time, in the improved structure, the fourth contact hole and the fifth contact hole are formed in the protective layer in order to connect between the common electrode of ITO and the connection line of Cu. In order to form the fourth contact hole, the design of the common electrode may be changed from a comb teeth to a tubular shape. However, this part is covered by the black matrix, so there is no change in transmittance according to the design change.

In addition, in the fringe-field type liquid crystal display device according to the embodiment of the present invention, the number of masks required to manufacture the array substrate is reduced, thereby simplifying the manufacturing process and reducing the manufacturing cost.

In addition, in the fringe-field type liquid crystal display according to the exemplary embodiment of the present invention, the resistance of the common electrode may be further reduced by contacting the connection line with the common electrode using side contacts.

Hereinafter, a method of manufacturing a fringe-field type liquid crystal display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6A through 6F are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 2.

7A to 7F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

8A through 8F are cross-sectional views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 4.

6A, 7A, and 8A, the pixel electrode 118 is formed on the array substrate 110 made of a transparent insulating material such as glass.

The pixel electrode 118 is formed by depositing a first conductive layer on the entire surface of the array substrate 110 and then selectively patterning the same through a photolithography process (first mask process).

The first conductive layer may be formed of a transparent conductive metal material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The pixel electrode 118 may be formed in a quadrangular shape.

6B, 7B, and 8B, the gate electrode 121, the gate line 116, and the common line 108L are formed on the array substrate 110 on which the pixel electrode 118 is formed.

The gate electrode 121, the gate line 116, and the common line 108L are formed by depositing a second conductive layer on the entire surface of the array substrate 110 and then selectively patterning the same through a photolithography process (second mask process). .

In this case, the second conductive layer may be formed of aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (chromium) to form a gate wiring and a common line 108L. Low resistance opaque conductive materials such as Cr), molybdenum (Mo), and molybdenum alloys. In addition, the second conductive film may have a multilayer structure in which two or more low-resistance conductive materials are stacked.

The common line 108L may be formed in a direction parallel to the gate line 116 to transfer a common voltage between pixels adjacent to left and right.

In this embodiment, the gate wiring and the common line 108L are formed after the pixel electrode 118 is formed as an example, but the present invention is not limited thereto. The pixel electrode 118 may be formed after the gate wiring and the common line 108L are formed, and the pixel electrode 118 and the gate wiring and the common line 108L may be formed in one mask process.

6C, 7C, and 8C, the gate insulating layer 115a is formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, and the common line 108L are formed. .

Thereafter, the gate insulating layer 115a is selectively removed through a photolithography process (third mask process) to form a first contact hole 140a exposing a part of the pixel electrode 118.

In addition, by selectively removing the gate insulating layer 115a through a third mask process, the second contact hole 140b exposing a part of the common line 108L is formed.

Next, referring to FIGS. 6D, 7D, and 8D, an amorphous silicon thin film, an n + amorphous silicon thin film, and a third conductive film are formed on the entire surface of the array substrate 110 on which the gate insulating layer 115a is formed.

In this case, the third conductive layer may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form the source electrode, the drain electrode, and the data line. In addition, the third conductive film may have a multilayer structure in which two or more low-resistance conductive materials are stacked.

Subsequently, the active layer 124 formed of the amorphous silicon thin film is formed on the gate electrode 121 by selectively removing the amorphous silicon thin film, the n + amorphous silicon thin film and the third conductive film through a photolithography process (fourth mask process).

At the same time, the source electrode 122 and the drain electrode 123 formed of the third conductive layer are formed on the active layer 124 through the fourth mask process. In this case, as described above, the drain electrode 123 may be just patterned with the side surface of the first contact hole 140a below, or a part thereof may be formed in the first contact hole 140a.

In addition, a data line 117 made of a third conductive layer is formed in the data line region of the array substrate 110 through a fourth mask process.

In addition, a connection line 135 made of a third conductive layer is formed through a fourth mask process.

The connection line 135 is formed in a direction crossing the gate line 116. In this case, the connection line 135 may be just patterned with the lower side of the second contact hole 140b or a part thereof may be formed in the second contact hole 140b.

In this case, an n + amorphous silicon thin film is formed on the active layer 124, and the ohmic contact layer 125 that ohmic-contacts the source / drain region of the active layer 124 and the source / drain electrodes 122 and 123. Is formed.

In addition, the first amorphous silicon thin film pattern 124 ′ and the first n + amorphous pattern formed of an amorphous silicon thin film and an n + amorphous silicon thin film, respectively, and are patterned to have substantially the same shape as the data line 117. The silicon thin film pattern 125 ′ is formed. However, the present invention is not limited thereto, and when the active layer 124 and the data line are formed using different mask processes, the data line 117 may be formed directly on the gate insulating layer 115a.

In addition, the second amorphous silicon thin film pattern 124 ″ and the second n + amorphous pattern formed of an amorphous silicon thin film and an n + amorphous silicon thin film, respectively, and are patterned to have substantially the same shape as the connection line 135. A silicon thin film pattern 125 "is formed. However, as described above, the present invention is not limited thereto.

In this case, the fourth mask process according to the embodiment of the present invention may use a half-tone mask. However, as described above, the present invention is not limited thereto.

6E, 7E, and 8E, the front surface of the array substrate 110 on which the active layer 124, the source / drain electrodes 122 and 123, the data line 117, and the connection line 135 are formed. The protective layer 115b is formed in this.

In this case, the protective layer 115b may be formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film.

In addition, the protective layer 115b may be formed using an organic insulating material having a low dielectric constant such as photoacrylic.

Thereafter, the protective layer 115b is selectively removed through a photolithography process (a fifth mask process) to form a third contact hole 140c exposing a part of the drain electrode 123 and the pixel electrode 118. In this case, the third contact hole 140c may be formed to expose not only the upper surface of the drain electrode 123 but also one side surface on the first contact hole 140a.

In addition, the protective layer 115b is selectively removed through a fifth mask process to form a fourth contact hole 140d exposing one side of the connection line 135 and a fifth contact hole 140e exposing the other side. do. In this case, the fourth contact hole 140d may be formed to expose one side as well as the upper surface of the connection line 135. In addition, the fifth contact hole 140e may be formed to expose not only the upper surface of the connection line 135 but also the other side surface on the second contact hole 140b.

Next, referring to FIGS. 6F, 7F, and 8F, after depositing a fourth conductive film on the entire surface of the array substrate 110, the fourth conductive film is selectively patterned using a photolithography process (sixth mask process). And a common electrode 108 electrically connected to the common line 108L.

At the same time, the connection electrode 130 made of the fourth conductive layer is formed through the sixth mask process. In this case, the connection electrode 130 electrically connects the pixel electrode 118 and the drain electrode 123 through the first contact hole 140a and the third contact hole 140c.

In this case, the fourth conductive layer may be made of a transparent conductive metal material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The quadrangular common electrode 108 may include a plurality of slits 108s in the common electrode 108 to generate a fringe-field along with the pixel electrode 118.

As described above, the common electrode 108 includes a first common electrode 108a and a second common electrode 108b.

The first common electrode 108a may be positioned at the edge of the pixel region to form a frame having a vertical shape. The second common electrode 108b may have a finger shape with the slits 108s therebetween in the pixel area.

In addition, the second common electrode 108b may be configured to be inclined to be symmetrical with respect to the center of the common electrode 108, and in this case, may form a two-domain structure. However, the present invention is not limited thereto.

One side of the connection line 135 is connected to the lower first common electrode 108a and the common line 108L through the second contact hole 140b and the fifth contact hole 140e, and the other side of the connection line 135 is fourth. The first common electrode 108a is connected to the upper side through the contact hole 140d.

At this time, in the case of the embodiment of the present invention, the first common electrode 108a has the effect of lowering the contact resistance as the contact (connection) is made not only on the upper surface of the connection line 135 but also on the side of the connection line 135. Have

In addition, the connection electrode 130 according to the embodiment of the present invention has an effect of lowering the contact resistance as the contact (connection) is made not only on the upper surface of the drain electrode 123 but also on the side of the drain electrode 123.

The array substrate according to the embodiment of the present invention configured as described above is bonded to face the color filter substrate by a sealant formed on the outside of the image display area, wherein the color filter substrate is a color for implementing red, green, and blue colors. A filter is formed.

At this time, the bonding of the color filter substrate and the array substrate is performed through an alignment key formed on the color filter substrate or the array substrate.

In the fringe-field type liquid crystal display according to the embodiment of the present invention, an amorphous silicon thin film transistor using an amorphous silicon thin film as an active layer has been described as an example, but the present invention is not limited thereto, and the present invention is a polycrystalline active layer. The same applies to polycrystalline silicon thin film transistors using silicon thin films and oxide thin film transistors using oxide.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. .

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

108: common electrode 108s: slit
118: pixel electrode 121: gate electrode
122 source electrode 123 drain electrode
124: active layer 130: connecting electrode
135: connection line

Claims (13)

A gate line, a common line, and a pixel electrode on the substrate;
A gate insulating layer on the gate line, the common line, and the pixel electrode;
A data line and a connection line on the gate insulating layer;
A protective layer on the data line and the connection line; And
It includes a common electrode having a plurality of slits on the protective layer,
The connection line is parallel to the data line,
The common line is parallel to the gate line,
The common electrode is in direct contact with the connection line and the common line through the contact hole of the protective layer and the contact hole of the gate insulating layer. The method of claim 1,
And the common line is formed of the same material as the gate line. The method of claim 1,
And the connection line is made of the same material as the data line. The method of claim 1,
And a resistance of the connection line is smaller than that of the common electrode. The method of claim 4, wherein
The connection line is made of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloy. Consisting of one or more substances selected from the group,
The common electrode may include at least one material selected from the group consisting of indium tin oxide (ITO) or indium zinc oxide (IZO). Board;
A plurality of gate lines, a plurality of data lines, and a plurality of common lines on the substrate;
A protective layer on the gate line and the data line;
A plurality of common electrodes and a plurality of pixel electrodes positioned on different layers with the protective layer interposed therebetween;
A connection line connecting the common electrodes adjacent to each other;
The common line is connected to the common electrode,
The connection line is parallel to the data line,
And the common line is parallel to the gate line. The method of claim 6,
And the common line is formed of the same material as the gate line. The method of claim 6,
And the connection line is made of the same material as the data line. The method of claim 6,
And a resistance of the connection line is smaller than that of the common electrode. The method of claim 9,
The connection line is made of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloy. Consisting of one or more substances selected from the group,
The common electrode may include at least one material selected from the group consisting of indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 6,
The common electrode and the pixel electrode are in a pixel area. The method of claim 6,
The common electrodes are spaced apart from each other,
And the connection line connects the common electrodes in a direction parallel to the data line. The method of claim 6,
The common electrodes are spaced apart from each other,
The common line connects the common electrodes adjacent to each other,
And a plurality of common electrodes connected to each other in a direction parallel to the gate line.

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